The previously-proposed model of the writing process in TDMR is modified based on the Stoner-Wohlfarth reversal mechanism. The BER performance for a neuro-ITI canceller is obtained via computer simulation using the R/W channel model based on the writing process, and it is compared to those for well-known TDMR equalization techniques.

This paper presents a new scalable method to considerably reduce the rollback propagation effect of the conventional optimistic message logging by utilizing positive features of reliable FIFO group communication links. To satisfy this goal, the proposed method forces group members to replicate different receive sequence numbers (RSNs), which they assigned for each identical message to their group respectively, into their volatile memories. As the degree of redundancy of RSNs increases, the possibility of local recovery for each crashed process may significantly be higher. Experimental results show that our method can outperform the previous one in terms of the rollback distance of non-faulty processes with a little normal time overhead.

This paper presents a method of reducing excitation error in sidelobe canceller without increasing the resolution of the digital phase shifters and the digital attenuators. In general sidelobe canceller, the null direction is shifted because of the excitation error (quantization error and random error, etc.) and the suppression capability degrades. The proposed method can alleviate the influence of the excitation error by vector composition of some quantized excitation weights. Computer simulation results show that the output signal to interference and noise power ratio (SINR) using the proposed method can improve greatly in comparison with that using conventional quantized excitation weight.

The classification of human motion is an important aspect of monitoring pedestrian traffic. This requires the development of advanced surveillance and monitoring systems. Methods to achieve this have been proposed using micro-Doppler radars. However, reliable long-term data and/or complicated procedures are needed to classify motion accurately with these conventional methods because their accuracy and real-time capabilities are invariably inadequate. This paper proposes an accurate and real-time method for classifying the movements of pedestrians using ultra wide-band (UWB) Doppler radar to overcome these problems. The classification of various movements is achieved by extracting feature parameters based on UWB Doppler radar images and their radial velocity distributions. Experiments were carried out assuming six types of pedestrian movements (pedestrians swinging both arms, swinging only one arm, swinging no arms, on crutches, pushing wheelchairs, and seated in wheelchairs). We found they could be classified using the proposed feature parameters and a k-nearest neighbor algorithm. A classification accuracy of 96% was achieved with a mean calculation time of 0.55s. Moreover, the classification accuracy was 99% using our proposed method for classifying three groups of pedestrian movements (normal walkers, those on crutches, and those in wheelchairs).

In this letter, we consider the global exponential stabilization problem by output feedback for a class of nonlinear systems. Along with a newly proposed matrix inequality condition, the proposed control method has improved flexibility in dealing with nonlinearity, over the existing methods. Analysis and examples are given to illustrate the improved features of our control method.

The authors have developed a mechanism that applies real vibration to electrical contacts by hammering oscillation in the vertical direction similar to that in real cases, and they have studied the effects of micro-oscillation on the contacts using the mechanism. It is shown that the performance of the hammering oscillation mechanism (HOM) for measuring acceleration and force is superior to that of other methods in terms of the stability of data. Using the mechanism, much simpler and more practical protocols are proposed for evaluating acceleration, force, and mass using only the measured acceleration. It is also indicated that the relationship between the inertial force generated by the hammering oscillation mechanism and the frictional force in electrical devices attached on a board is related to one of the causes of the degradation of electrical contacts under the effect of external micro-oscillation.

This paper introduces open-wire fault-resilient multiple-valued codes for reliable asynchronous point-to-point global communication links. In the proposed encoding, two communication modules assign complementary codewords that change between two valid states without an open-wire fault. Under an open-wire fault, at each module, the codewords don't reach to one of the two valid states and remains as “invalid” states. The detection of the invalid states makes it possible to stop sending wrong codewords caused by an open-wire fault. The detectability of the open-wire fault based on the proposed encoding is proven for m-of-n codes. The proposed code used in the multiple-valued asynchronous global communication link is capable of detecting a single open-wire fault with 3.08-times higher coding efficiency compared with a conventional multiple-valued code used in a triple-modular redundancy (TMR) link that detects an open-wire fault under the same dynamic range of logical values.

Nowadays, fault tolerance has been playing a progressively important role in covering increasing soft/hard error rates in electronic devices that accompany the advances of process technologies. Research shows that wear-out faults have a gradual onset, starting with a timing fault and then eventually leading to a permanent fault. Error detection is thus a required function to maintain execution correctness. Currently, however, many highly dependable methods to cover permanent faults are commonly over-designed by using very frequent checking, due to lack of awareness of the fault possibility in circuits used for the pending executions. In this research, to address the over-checking problem, we introduce a metric for permanent defects, as operation defective probability (ODP), to quantitatively instruct the check operations being placed only at critical positions. By using this selective checking approach, we can achieve a near-100% dependability by having about 53% less check operations, as compared to the ideal reliable method, which performs exhaustive checks to guarantee a zero-error propagation. By this means, we are able to reduce 21.7% power consumption by avoiding the non-critical checking inside the over-designed approach.

As mobile multimedia services expand, user behavior will become more diverse and the control of service quality from the user's perspective will become more important in service design. The quality of the network is one of the critical factors determining mobile service quality. However, this has mainly been evaluated in objective physical terms, such as delay reduction and bandwidth expansion. It is less common to use a human-centered design viewpoint when improving network performance. In this paper, we discuss ways to improve the quality of web services using time-fillers that actively address the human factors to improve the subjective quality of a mobile network. A field experiment was conducted, using a prototype. The results of the field experiment show that time-fillers can significantly decrease user dissatisfaction with waiting, but that this effect is strongly influenced by user preferences concerning content. Based on these results, we discuss the design requirements for effective use of time-fillers.

In order to execute coherent Doppler processing in a high range-rate scenario, whether it is for detection, estimation or imaging, range walk embedded in target return should be compensated first. In case of a bistatic radar geometry where a transmitter, a receiver and a target can be all moving, the extent of range walk depends on their relative positions and velocities. This paper presents a coherent Doppler processing algorithm to achieve target detection and Doppler frequency estimation of a target under a bistatic radar geometry. This algorithm is based on the assumption that a target has constant Doppler frequency during a coherent processing interval (CPI). Thus, we first show under what condition the assumption could be valid. We next develop an algorithm, along with its implementation procedures where the region of range walk, called a window, is manipulated. Finally, the performance of a proposed algorithm is examined through simulations.

A plane coupler has been developed for a two-dimensional (2D) wireless power transmission. This coupler can construct a continuous wireless power transmission system for mobile devices due to its small, light characteristics. This coupler has two elements connected with a 2D waveguide sheet, and coupling capacitances between the elements and the sheet decrease the coupler size by reducing their resonance frequencies. A propagation loss of -10.0 dB is obtained using the small 0.025-λ2 coupler. Continuous operation of the mobile device is demonstrated by applying wireless power transmission to the 2D waveguide sheet with the small plane coupler.

Network traffic keeps increasing due to the increasing popularity of video streaming services. Routers and switches in wire-line networks require guaranteed line rates as high as 20 Gbp/s as well as advanced quality of service (QoS). Hybrid SRAM and DRAM architecture previously presented with the benefit of high-speed and high-density, but it requires complex memory management. As a result, it has hardly supported large numbers of queue, which is an effective approach to satisfying the QoS requirements. This paper proposes an intelligent memory management unit (MMU) which is based on the hybrid architecture, where over 16k multi queues are integrated. The performance examined by the system board is zero-packet loss under the seamless traffic with 60–1.5 kByte packet-length (deterministic manner). Noticeable feature in this paper's architecture is eliminating the need for any premium memories but only low-cost commodity SRAMs and DRAMs are used. The intelligent MMU employs the head buffer architecture, which is suitable for supporting a large numbers of FIFO queues. An experimental board based on this architecture is embedded into a Router system to evaluate the performance. Using 16k queues at 20 Gbps, zero-packet loss is examined with 64-Byte to 1,500-Byte packet-length.

Gopalan, Klivans, and Zuckerman proposed a list-decoding algorithm for Reed-Muller codes. Their algorithm works up to a given list-decoding radius. Dumer, Kabatiansky, and Tavernier improved the complexity of the algorithm for binary Reed-Muller codes by using the well-known Plotkin construction. In this study, we propose a list-decoding algorithm for non-binary Reed-Muller codes as a generalization of Dumer et al.'s algorithm. Our algorithm is based on a generalized Plotkin construction, and is more suitable for parallel computation than the algorithm of Gopalan et al. Since the list-decoding algorithms of Gopalan et al., Dumer et al., and ours can be applied to more general codes than Reed-Muller codes, we give a condition for codes under which these list-decoding algorithms works.

In this paper, we propose a step size control method capable of quickly canceling acoustic echo even when double talk continues from the echo path change. This method controls the step size by substituting the norm of the difference vector between the coefficient vectors of a main adaptive filter (Main-ADF) and a sub-adaptive filter (Sub-ADF) for the estimation error provided by the former. Actually, the number of taps of Sub-ADF is limited to a quarter of that of Main-ADF, and the larger step size than that applied to Main-ADF is given to Sub-ADF; accordingly the norm of the difference vector quickly approximates to the estimation error. The estimation speed can be improved by utilizing the norm of the difference vector for the step size control in Main-ADF. We show using speech signals that in single talk the proposed method can provide almost the same estimation speed as the method whose step size is fixed at the optimum one and verify that even in double talk the estimation error, quickly decreases.

Traditional imperfect fault coverage models only consider the coverage (including identification and isolation) of faulty components, and they do not consider the coverage of irrelevant (operational) components. One potential reason for the omission is that in these models the system is generally assumed to be coherent in which each component is initially relevant. In this paper, we first point out that an initially relevant component could become irrelevant afterwards due to the failures of some other components, and thus it is important to consider the handling of irrelevancy even the system is originally coherent. We propose an irrelevancy coverage model (IRCM) in which the coverage is extended to the irrelevant components in addition to the faulty components. The IRCM can not only significantly enhance system reliability by preventing the future system failures resulting from the not-covered failures of the irrelevant components, but may also play an important role in efficient energy use in practice by timely turning off the irrelevant components.

We propose a new fine Doppler frequency estimator using two fast Fourier transform (FFT) samples for pulse Doppler radar that offers highly sensitive detection and a high resolution of velocity. The procedure of fine Doppler frequency estimation is completed through coarse frequency estimation (CFE) and fine frequency estimation (FFE) steps. During the CFE step, the integer part of the Doppler frequency is obtained by processing the FFT, after which, during the FFE step, the fractional part is estimated using the relationship between the FFT peak and its nearest resultant value. Our simulation results show that the proposed estimator has better accuracy than Candan's estimator in terms of bias. The root mean square error (RMSE) of the proposed estimator has more than 1.4 time better accuracy than Candan's estimator under a 1,024-point FFT and a signal-to-noise ratio (SNR) of 10 dB. In addition, when the FFT size is increased from 512 to 2,048, the RMSE characteristics of the proposed estimator improve by more than two-fold.

Cyclic Redundancy Check (CRC) is a well known error detection scheme used to detect corruption of digital content in digital networks and storage devices. Since it is a compute-intensive process which adversely affects performance, hardware acceleration using FPGAs has been tried and satisfactory performance has been achieved. However, recent extended usage of networks and storage systems require various correction capabilities for various CRC standards. Traditional hardware designs based on the LFSR (Linear Feedback Shift Register) tend to have fixed structure without such flexibility. Here, fully-adaptable CRC accelerator based on a table-based algorithm is proposed. The table-based algorithm is a flexible method commonly used in software implementations. It has been rarely implemented with the hardware, since it is believed that the operational speed is not enough. However, by using pipelined structure and efficient use of memory modules in FPGAs, it appeared that the table-based fixed CRC accelerators achieved better performance than traditional implementation. Based on the implementation, fully-adaptable CRC accelerator which eliminate the need for many non-adaptable CRC implementations is proposed. The accelerator has ability to process arbitrary number of input data and generates CRC for any known CRC standard, up to 65 bits of generator polynomial, during run-time. Further, we modify Table generation algorithm in order to decrease its space complexity from O(nm) to O(n). On Xilinx Virtex 6 LX550T board, the fully-adaptable accelerators occupy between 1 to 2% area to produce maximum of 289.8 Gbps at 283.1 MHz if BRAM is deployed, or between 1.6 - 14% of area for 418 Gbps at 408.9 MHz if tables are implemented in logic. Proposed architecture enables further expansion of throughput by increasing a number of input bits M processed at a time.

This paper presents a method of designing transmission line couplers (TLCs) and a mixer-based receiver for dicode partial response communications. The channel design method results in the optimum TLC design. The receiver with mixers and DC balancing circuits reduces the threshold control circuits and digital circuits to decode dicode partial response signals. Our techniques enable low inter-symbol interference (ISI) dicode partial response communications without three level decision circuits and complex threshold control circuits. The techniques were evaluated in a simulation with an EM solver and a transistor level simulation. The circuit was designed in the 90-nm CMOS process. The simulation results show 12-Gb/s operation and 52mW power consumption at 1.2V.

Power consumption has recently emerged as a first class design constraint in system LSI designs. Specially, leakage power has occupied a large part of the total power consumption. Therefore, reduction of leakage power is indispensable for efficient design of high-performance system LSIs. Since 2006, we have carried out a research project called “Innovative Power Control for Ultra Low-Power and High-Performance System LSIs”, supported by Japan Science and Technology Agency as a CREST research program. One of the major objectives of this project is reducing the leakage power consumption of system LSIs by innovative power control through tight cooperation and co-optimization of circuit technology, architecture, and system software designs. In this project, we focused on power gating as a circuit technique for reducing leakage power. Temporal granularity is one of the most important issue in power gating. Thus, we have developed a series of Geysers as proof-of-concept CPUs which provide several mechanisms of fine-grained run-time power gating. In this paper, we describe their concept and design, and explain why co-optimization of different design layers are important. Then, three kinds of power gating implementations and their evaluation are presented from the view point of power saving and temporal granularity.

The size and complexity of software in computer systems and even in consumer electronics is drastically and continuously increasing, thus increasing the compilation time. For example, the compilation time for building some of mobile phones' platform software takes several hours. In order to reduce the compilation time, this paper proposes a Distributed Scalable Compilation Tool, called DiSCo where full compilation passes such as preprocessing, compilation, and even linking are performed at remote machines, i.e. in parallel. To the best of our knowledge DiSCo is the first distributed compiler to support complete distributed processing in all the compilation passes. We use an extensive dependency analysis in parsing compilation commands for exploiting higher command-level parallelism, and we apply a file caching method and a network-drive protocol for reducing the remote compilation overhead and simplifying the implementation. Lastly, we minimize load imbalance and remote machine management overhead with our heuristic static scheduling method by predicting compilation time and considering the overheads invoked by the compilation process. Our evaluation using four large mobile applications and eight GNU applications shows that the performance of DiSCo is scalable and the performance is close to a profile scheduling.