Energy minimization has become one of the primary goals in the embedded real-time domains. Consequently, scratch-pad memory has been employed as partial or entire replacement for cache memory due to its better energy efficiency. However, most previous approaches were not applicable to a preemptive multi-task environment. We propose three methods of partitioning and allocation of scratch-pad memory for fixed-priority-based preemptive multi-task systems. The three methods, i.e., spatial, temporal, and hybrid methods, achieve energy reduction in the instruction memory subsystems. With the spatial method, each task occupies its exclusive space in scratch-pad memory. With the temporal method, the running task uses entire scratch-pad space. The content of scratch-pad memory is swapped out as a task executes or gets preempted. The hybrid method is based on the spatial one but a higher priority task can temporarily use the space of lower priority task. The amount of space is prioritized for higher priority tasks. We formulate each method as an integer programming problem that simultaneously determines (1) partitioning of scratch-pad memory space for the tasks, and (2) allocation of program code to scratch-pad memory space for each task. Our methods not only support the real-time task scheduling but also consider aggressively the periods and priorities of tasks for the energy minimization. Additionally, we implement an RTOS-hardware cooperative support mechanism for runtime code allocation to the scratch-pad memory space. We have made the experiments with the fully functional real-time operating system. The experimental results have demonstrated the effectiveness of our techniques. Up to 73% energy reduction compared to a conventional method was achieved.

In this paper, a rat-race hybrid coupler based on an open complementary split ring resonator (OCSRR) is presented. By embedding the OCSRR in the microstrip transmission line, slow-wave effect is introduced to achieve size reduction. The proposed rat-race coupler size is 37% smaller than the conventional rat-race coupler. Besides, the proposed coupler provides better third harmonic suppression up to 35 dB. The simulated results are compared with the measured data and good agreement is reported.

The aim of this study is to realize a simplified gait analysis system using wearable sensors. In this paper, a joint angle measurement method using Kalman filter to correct gyroscope signals from accelerometer signals was examined in measurement of hip, knee and ankle joint angles with a wireless wearable sensor system, in which the sensors were attached on the body without exact positioning. The lower limb joint angles of three healthy subjects were measured during gait with the developed sensor system and a 3D motion measurement system in order to evaluate the measurement accuracy. Then, 10 m walking measurement was performed under different walking speeds with a healthy subject in order to find the usefulness of the system as a simplified gait analysis system. The joint angles were measured with reasonable accuracy, and the system showed joint angle changes that were similar to those shown in a previous report as walking speed changed. It would be necessary to examine the influence of sensor attachment position and method for more stable measurement, and also to study other parameters for gait evaluation.

A detailed analysis of a multilayer symmetric coupler employing symmetrical broad-side coupled lines is presented. We confirm that the coupler can be designed using a well-known even-odd mode analysis of two strip lines while the coupler has four strip lines. We also confirm that the previously reported poor isolation originates from port mismatching. To verify the analysis, couplers that have different dimensions are fabricated. One example exhibits a coupling loss of 4.50.5 dB, a return loss better than 15 dB, and isolation characteristics higher than 12 dB in the 6.5 to 15.1 GHz frequency range. These results agree well with the obtained simulation results. The results show that the coupler has the potential to provide tight and ideal coupling.

Sender-based message logging (SBML) with checkpointing has its well-known beneficial feature, lowering highly failure-free overhead of synchronous logging with volatile logging at sender's memory. This feature encourages it to be applied into many distributed systems as a low-cost transparent rollback recovery technique. However, the original SBML recovery algorithm may no longer be progressing in some transient communication error cases. This paper proposes a consistent recovery algorithm to solve this problem by piggybacking small log information for unstable messages received on each acknowledgement message for returning the receive sequence number assigned to a message by its receiver. Our algorithm also enables all messages scheduled to be sent, but delayed because of some preceding unstable messages to be actually transmitted out much earlier than the existing ones.

This paper proposes ladder-logic programming model for sensor actuator networks. We also demonstrate optimized operations of them with central controller-based device management (CCDM) architecture. A wireless sensor actuator network consists of distributed wireless nodes, and implementing data streams and data processors onto these wireless nodes has been challenging. System programmers have to describe their instructions by a programming language, and data processors must be placed so that it optimizes, for example, total network traffic. The ladder-logic model enables the programming of them, and CCDM makes various types of optimizations feasible, including the optimization of network traffic, delivery latency, load-balancing and fault-tolerance even though these algorithms are not lightweight. In this paper, we focus on traffic reduction case, and propose two moderately complex algorithms. The experiment has shown that CCDM achieves optimizations even with such moderately complex algorithms.

Transmission performance of carrier superposed signals for frequency reuse are significantly degraded when transmitted through a satellite channel containing a nonlinear device. The extent to which the signals are degraded depends on the operating level (back off) of the transponder. This paper proposes a method to compensate for the effects of nonlinearity in the interference canceller by giving the same nonlinearity to a replica with the capability to automatically track the back off of the satellite transponder. Computer simulations show that the proposed technique significantly enhances system performance at all transponder operating levels even though it can be simply implemented in the canceller by digital signal processing circuits.

Manufacturing defects in the deep sub-micron VLSI process and aging resulted problems of devices during lifecycle are inevitable, and fault-tolerant routing algorithms are important to provide the required communication for NoCs in spite of failures. The proposed algorithm, referred to as scalable and reconfigurable fault-tolerant distributed routing (RFDR), partitions the system into nine regions using the concept of divide-and-conquer. It is a distributed algorithm, and each router guarantees fault-tolerance within one's own region and the system can be still sustained with multiple fault areas. The proposed RFDR has excellent scalability with hardware cost keeping constant independent of system size. Also it is completely reconfigurable when new nodes fail. Simulations under various synthetic traffic patterns show its better performance compared to Extended-XY routing algorithm. Moreover, there is almost no hardware overhead compared to Logic-Based Distributed Routing (LBDR), but the fault-tolerance capacity is enhanced in the proposed algorithm. Hardware cost is reduced 37% compared to Reconfigurable Distributed Scalable Predictable Interconnect Network (R-DSPIN) which only supports single fault region.

A planar miniaturized branch-line coupler with harmonic suppression property for UHF band applications is presented in this paper. By properly synthesizing the LC-tanks that employ artificial transmission lines, two pairs of quarter-wavelength branch-lines to respectively meet characteristic impedances of 35.4 and 50 ohms can be obtained with the coupler. For the operating band, it can achieve good 3 dB power division with a 90° phase difference in the outputs of the through and coupled arms. The coupler also has a small area of 20.5(L)18(W) mm2, corresponding to 0.11 λg0.1 λg at 922 MHz. Compared with conventional couplers, the proposed design not only offers a wide bandwidth of more than 230 MHz within 1° or 1 dB, but also works with additional harmonic suppression for achieving better performance. Therefore, the proposed branch-line coupler with a compact size is well suitable for power division application.

This paper proposed a novel platform for sensor nodes to resolve the energy and latency challenges. It consists of a processor, an adaptive compressing module and several compression accelerators. We completed the proposed chip in a 0.18µm HJTC CMOS technology. Compared to the software-based solution, the hardware-assisted compression reduces over 98% energy and 212% latency. Besides, we balanced the energy and latency metric using an adaptive module. According to the scheduling algorithm, the module tunes the state of the compression accelerator, as well as the sampling frequency of the online sensor. For example, given a 9µs constraint for a 1-byte operation, it reduces 34% latency while the energy overheads are less than 5%.

This paper proposes a method for using an accelerometer, microphone, and GPS in a mobile phone to recognize the movement of the user. Past attempts at identifying the movement associated with riding on a bicycle, train, bus or car and common human movements like standing still, walking or running have had problems with poor accuracy due to factors such as sudden changes in vibration or times when the vibrations resembled those for other types of movement. Moreover, previous methods have had problems with has the problem of high power consumption because of the sensor processing load. The proposed method aims to avoid these problems by estimating the reliability of the inference result, and by combining two inference modes to decrease the power consumption. Field trials demonstrate that our method achieves 90% or better average accuracy for the seven types of movement listed above. Shaka's power saving functionality enables us to extend the battery life of a mobile phone to over 100 hours while our estimation algorithm is running in the background. Furthermore, this paper uses experimental results to show the trade-off between accuracy and latency when estimating user activity.

In the case of Barreto-Naehrig pairing-friendly curves of embedding degree 12 of order r, recent efficient Ate pairings such as R-ate, optimal, and Xate pairings achieve Miller loop lengths of(1/4) ⌊log2 r⌋. On the other hand, the twisted Ate pairing requires (3/4) ⌊log2 r⌋ loop iterations, and thus is usually slower than the recent efficient Ate pairings. This paper proposes an improved twisted Ate pairing using Frobenius maps and a small scalar multiplication. The proposed idea splits the Miller's algorithm calculation into several independent parts, for which multi-pairing techniques apply efficiently. The maximum number of loop iterations in Miller's algorithm for the proposed twisted Ate pairing is equal to the (1/4) ⌊log2 r ⌋ attained by the most efficient Ate pairings.

A safe prime p is a prime such that (p-1)/2 is also a prime. A primality test or a safe primality test is normally a combination of trial division and a probabilistic primality test. Since the number of small odd primes used in the trial division affects the performance of the combination, researchers have studied how to obtain the optimal number of small odd primes to be used in the trial division and the expected running time of the combination for primality tests. However, in the case of safe primality tests, the analysis of the combination is more difficult, and thus no such results have been given. In this paper, we present the first probabilistic analysis on the expected running time and the optimal number of small odd primes to be used in the trial division for optimizing the tests. Experimental results show that our probabilistic analysis estimates the behavior of the safe primality tests very well.

This paper presents a simplifying method of the two previous fault attacks to pairing and the Miller algorithms based on a practical fault assumption. Our experimental result shows that the assumption is feasible and easy to implement.

An algorithm for the discrimination between human upstairs and downstairs using a tri-axial accelerometer is presented in this paper, which consists of vertical acceleration calibration, extraction of two kinds of features (Interquartile Range and Wavelet Energy), effective feature subset selection with the wrapper approach, and SVM classification. The proposed algorithm can recognize upstairs and downstairs with 95.64% average accuracy for different sensor locations, i.e. located on the subject's waist belt, in the trousers pocket, and in the shirt pocket. Even for the mixed data from all sensor locations, the average recognition accuracy can reach 94.84%. Experimental results have successfully validated the effectiveness of the proposed method.

This study demonstrates the ability of a portable X-band Doppler weather radar (XDR) to measure Doppler velocity (Vd). Existing portable X-band weather radars are housed in a container and hence have to be carried by a truck. Therefore they have limitations in their installation places. For installations at small areas where the existing X-band weather radars cannot be installed (e.g., rooftop area of small building), XDR is designed to be carried by a cart. Components of the outdoor unit (a parabolic antenna with a diameter of 1.2 m, magnetron transmitter, and radio frequency (RF) and intermediate frequency (IF) analog components) are housed in a compact body with a weight less than 300 kg. The radar operation, IF digital processing, and data storage are carried out by a desktop computer having a commercial IF digital receiver. In order to attain the required portability and reduced purchase and running costs, XDR uses a magnetron transmitter. Because XDR is the first that utilizes an IF digital receiver for the signal processing specific to magnetron transmitters (i.e., the phase correction of received signals due to the randomness of the transmitted pulse phase), Vd measured by XDR (hereafter VdXDR) was assessed. Using the dataset collected from 25 to 26 October 2009 at the Shigaraki MU Observatory (3451'N, 13606'E), the equivalent radar reflectivity factor (Ze) and VdXDR were assessed using Ze and Vd measured by a Micro Rain Radar and a L-band Doppler radar named LQ-7. The results using correlation coefficients and regression lines demonstrate that XDR measured Ze and Vd accurately. The results also show that IF digital receivers are useful for providing magnetron weather radars with the function of Vd measurement, and further suggest that a combination of IF digital receiver and magnetron transmitter contributes to future development of Doppler weather radars, because high cost performance is strongly required for a precipitation monitoring radar network.

Due to the lack of end-to-end paths between the communication source and destination, the routing of Delay Tolerant Networks (DTN) exploits the store-carry-and-forward mechanism. This mechanism requires nodes with sufficient energy to relay and forward messages in a cooperative and selfless way. However, in the real world, the energy is constrained and most of the nodes exhibit selfish behaviors. In this paper, we investigate the performance of DTN routing schemes considering both the energy constraint and selfish behaviors of nodes. First, we model the two-hop relay and epidemic routing based on a two-dimensional continuous time Markov chain. Then, we obtain the system performance of message delivery delay and delivery cost by explicit expressions. Numerical results show that both the energy constraint and node selfishness reduce the message delivery cost at the expense of increasing the message delivery delay. Furthermore, we demonstrate that the energy constraint plays a more important role in the performance of epidemic routing than that of two-hop relay.

In this paper, a soft-error-tolerant BILBO (Built-In Logic Block Observer) FF (flip-flop) is presented. The proposed FF works as a soft-error-tolerant FF in system operations and as a BILBO FF in manufacturing testing. The construction of the proposed FF is based on that of an existing soft-error-tolerant FF, namely a BISER (Built-In Soft Error Resilience) FF. The proposed FF contains a reconfigurable C-element with XNOR calculation capability, which works as a C-element for soft-error-tolerance during system operations and as an XNOR gate employed in linear feedback shift registers (LFSRs) during manufacturing testing. The evaluation results shown in this paper indicate that the area of the proposed FF is 8.5% smaller than that of a simple combination of the existing BISER and BILBO FFs. In addition, the sum of CLK-Q delay and D-CLK setup times on system operations for the proposed FF is 19.7% shorter than that for the combination.

In this paper, a 24 GHz frequency source for low phase noise is presented in a 0.18 µm CMOS process. The 24 GHz frequency source chip is composed of a 12 GHz voltage controlled oscillator (VCO) and a 24 GHz balanced frequency doubler with class B gate bias. Compared to a conventional complementary VCO, the proposed 12 GHz VCO has phase noise improvement by using resistor current sources and substituting the nMOS cross-coupled pair in the conventional complementary VCO for a gm-boosted nMOS differential Colpitts pair. The measured phase noise and fundamental frequency suppression are -107.17 dBc/Hz at a 1 MHz offset frequency and -20.95 dB at 23.19 GHz frequency, respectively. The measured frequency tuning range is from 23.19 GHz to 24.76 GHz drawing 2.72 mA at a supply voltage of 1.8 V not including an output buffer.

In this paper, we propose a memory-efficient structure for a pulse Doppler radar in order to reduce the hardware's complexity. The conventional pulse Doppler radar is computed by fast frequency transform (FFT) of all range cells in order to extract the velocity of targets. We observed that this method requires a huge amount of memory to perform the FFT processes for all of the range cells. Therefore, instead of detecting the velocity of all range cells, the proposed architecture extracts the velocity of the targets by using the cells related to the moving targets. According to our simulations and experiments, the detection performance of this proposed architecture is 93.5%, and the proposed structure can reduce the hardware's complexity by up to 66.2% compared with the conventional structure.