Lei JING Yinghui ZHOU Zixue CHENG Junbo WANG
Automatic recognition of finger gestures can be used for promotion of life quality. For example, a senior citizen can control the home appliance, call for help in emergency, or even communicate with others through simple finger gestures. Here, we focus on one-stroke finger gesture, which are intuitive to be remembered and performed. In this paper, we proposed and evaluated an accelerometer-based method for detecting the predefined one-stroke finger gestures from the data collected using a MEMS 3D accelerometer worn on the index finger. As alternative to the optoelectronic, sonic and ultrasonic approaches, the accelerometer-based method is featured as self-contained, cost-effective, and can be used in noisy or private space. A compact wireless sensing mote integrated with the accelerometer, called MagicRing, is developed to be worn on the finger for real data collection. A general definition on one-stroke gesture is given out, and 12 kinds of one-stroke finger gestures are selected from human daily activities. A set of features is extracted among the candidate feature set including both traditional features like standard deviation, energy, entropy, and frequency of acceleration and a new type of feature called relative feature. Both subject-independent and subject-dependent experiment methods were evaluated on three kinds of representative classifiers. In the subject-independent experiment among 20 subjects, the decision tree classifier shows the best performance recognizing the finger gestures with an average accuracy rate for 86.92 %. In the subject-dependent experiment, the nearest neighbor classifier got the highest accuracy rate for 97.55 %.
Yoshimitsu TAKAMATSU Ryuichi FUJIMOTO Tsuyoshi SEKINE Takaya YASUDA Mitsumasa NAKAMURA Takuya HIRAKAWA Masato ISHII Motohiko HAYASHI Hiroya ITO Yoko WADA Teruo IMAYAMA Tatsuro OOMOTO Yosuke OGASAWARA Masaki NISHIKAWA Yoshihiro YOSHIDA Kenji YOSHIOKA Shigehito SAIGUSA Hiroshi YOSHIDA Nobuyuki ITOH
This paper presents a single-chip RF tuner/OFDM demodulator for a mobile digital TV application called “1-segment broadcasting.” To achieve required performances for the single-chip receiver, a tunable technique for a low-noise amplifier (LNA) and spurious suppression techniques are proposed in this paper. Firstly, to receive all channels from 470 MHz to 770 MHz and to relax distortion characteristics of following circuit blocks such as an RF variable-gain amplifier and a mixer, a tunable technique for the LNA is proposed. Then, to improve the sensitivity, spurious signal suppression techniques are also proposed. The single-chip receiver using the proposed techniques is fabricated in 90 nm CMOS technology and total die size is 3.26 mm 3.26 mm. Using the tunable LNA and suppressing undesired spurious signals, the sensitivities of less than -98.6 dBm are achieved for all the channels.
Jiangtao SUN Qing LIU Yong-Ju SUH Takayuki SHIBATA Toshihiko YOSHIMASU
A balanced push-push frequency doubler has been demonstrated in 0.25-µm SOI (Silicon on Insulator) SiGe BiCMOS technology operating from 22 GHz to 29 GHz with high fundamental frequency suppression and high conversion gain. A series LC resonator circuit is connected in parallel with the differential outputs of the doubler core circuit. The LC resonator is effective to improve the fundamental frequency suppression. In addition, the LC resonator works as a matching circuit between the output of the doubler core and the input of the output buffer amplifier, which increases the conversion gain of the whole circuit. A measured fundamental frequency suppression of greater than 46 dBc is achieved at an input power of -10 dBm in the output frequency band of 22-29 GHz. Moreover, maximum fundamental frequency suppression of 66 dBc is achieved at an input frequency of 13 GHz and an input power of -10 dBm. The frequency doubler works at a supply voltage of 3.3 V.
Shoji KANEKO Masashi FUSHIKI Masayuki NAKANO Yoji KISHI
Multi-site MIMO (Multiple Input Multiple Output) is a key technology that will enable next generation cellular networks to achieve high throughput in cell edge areas. However, a multi-site single-user MIMO system is subject to performance degradation in terms of cell throughput due to the expense of additional assignments of radio resources to cell edge user equipment. This paper presents a BS-cooperation scheduling scheme for a multi-site single-user MIMO cellular system. The proposed BS-cooperation scheduling scheme aims to maintain cell throughput while improving cell edge user throughput. The proposed scheme employs two policies with respect to the assignment of radio resource to the user equipment with multi-site connection. One is to control the opportunities for radio resource assignment to user equipment with a multi-site connection to avoid the excessive assignment of radio resources and to maintain cell throughput. The other policy governs the decision as to whether the user equipment operates with a multi-site connection or not, making it possible for the multi-site connection to contribute to the improvement in user throughput in the cell edge areas. The simulation results show that the proposed scheme is effective from the perspective of both cell throughput and cell edge user throughput.
Binzhang FU Yinhe HAN Huawei LI Xiaowei LI
The Network-on-Chip (NoC) is limited by the reliability constraint, which impels us to exploit the fault-tolerant routing. Generally, there are two main design objectives: tolerating more faults and achieving high network performance. To this end, we propose a new multiple-round dimension-order routing (NMR-DOR). Unlike existing solutions, besides the intermediate nodes inter virtual channels (VCs), some turn-legally intermediate nodes inside each VC are also utilized. Hence, more faults are tolerated by those new introduced intermediate nodes without adding extra VCs. Furthermore, unlike the previous solutions where some VCs are prioritized, the NMR-DOR provides a more flexible manner to evenly distribute packets among different VCs. With extensive simulations, we prove that the NMR-DOR maximally saves more than 90% unreachable node pairs blocked by faults in previous solutions, and significantly reduces the packet latency compared with existing solutions.
Satoshi DENNO Ke LIU Tatsuo FURUNO Masahiro MORIKURA
It is known that a heterodyne multimode receiver implemented with a single RF (Radio Frequency) receiver suffers from image-band interference due to imbalance, i.e. the phase error and the gain imbalance of the RF Hilbert transformer. The blind image band interference canceler with deterministic imbalance estimation that has been proposed mitigates the image-band interference. This performance of the image-band interference canceler is analyzed theoretically in this paper. As a result, it is revealed that estimation accuracy of the deterministic imbalance estimation is improved slightly as the imbalance becomes greater. In addition, it is also shown that the deterministic estimation achieves better performance as the power of image-band interference increases. The performance is confirmed by computer simulation.
Xincun JI Fuqing HUANG Jianhui WU Longxing SHI
A 1.8 V, 5 GHz low power frequency synthesizer for Wireless Sensor Networks is presented in 0.18 µm CMOS technology. A low power phase-switching prescaler is designed, and the current mode phase rotator is merged into the first divide-by-2 circuit of the prescaler to reduce power and propagation delay. An improved charge pump circuit is proposed to compensate for the dynamic effects with the charge pump. By a divide-by-2 circuit, the frequency synthesizer can provide a 2.324-2.714 GHz quadrature output frequency in 1 MHz steps with a 4 MHz reference frequency. The measured output phase noise is -110 dBc/Hz at 1-MHz offset frequency. The power consumption of the PLL is 11.2 mW at 1.8 V supply voltage.
Atsunori OGAWA Satoshi TAKAHASHI Atsushi NAKAMURA
This paper proposes an efficient combination of state likelihood recycling and batch state likelihood calculation for accelerating acoustic likelihood calculation in an HMM-based speech recognizer. Recycling and batch calculation are each based on different technical approaches, i.e. the former is a purely algorithmic technique while the latter fully exploits computer architecture. To accelerate the recognition process further by combining them efficiently, we introduce conditional fast processing and acoustic backing-off. Conditional fast processing is based on two criteria. The first potential activity criterion is used to control not only the recycling of state likelihoods at the current frame but also the precalculation of state likelihoods for several succeeding frames. The second reliability criterion and acoustic backing-off are used to control the choice of recycled or batch calculated state likelihoods when they are contradictory in the combination and to prevent word accuracies from degrading. Large vocabulary spontaneous speech recognition experiments using four different CPU machines under two environmental conditions showed that, compared with the baseline recognizer, recycling and batch calculation, our combined acceleration technique further reduced both of the acoustic likelihood calculation time and the total recognition time. We also performed detailed analyses to reveal each technique's acceleration and environmental dependency mechanisms by classifying types of state likelihoods and counting each of them. The analysis results comfirmed the effectiveness of the combined acceleration technique.
Mitsuyoshi KISHIHARA Isao OHTA Kensuke OKUBO
A broadband cruciform substrate integrated waveguide coupler is designed based on the planar circuit approach. The broadband property is obtained by widening the crossed region in the same way as rectangular waveguide cruciform couplers. As a result, a 3 dB coupler with fractional bandwidth of 30% is realized at 24 GHz.
Jiangtao SUN Qing LIU Yong-Ju SUH Takayuki SHIBATA Toshihiko YOSHIMASU
A broadband balanced frequency doubler has been demonstrated in 0.25-µm SOI SiGe BiCMOS technology to operate from 22 GHz to 30 GHz. The measured fundamental frequency suppression of greater than 30 dBc is achieved by an internal low pass LC filter. In addition, a pair of matching circuits in parallel with the LO inputs results in high suppression with low input drive power. Maximum measured conversion gain of -6 dB is obtained at the input drive power as low as -1 dBm. The results presented indicate that the proposed frequency doubler can operate in broadband and achieve high fundamental frequency suppression with low input drive power.
Kazuya UEKI Masashi SUGIYAMA Yasuyuki IHARA
Over the recent years, a great deal of effort has been made to estimate age from face images. It has been reported that age can be accurately estimated under controlled environment such as frontal faces, no expression, and static lighting conditions. However, it is not straightforward to achieve the same accuracy level in a real-world environment due to considerable variations in camera settings, facial poses, and illumination conditions. In this paper, we apply a recently proposed machine learning technique called covariate shift adaptation to alleviating lighting condition change between laboratory and practical environment. Through real-world age estimation experiments, we demonstrate the usefulness of our proposed method.
Eiji ITOH Yuji HIGUCHI Daisuke FURUHATA
We investigated the photovoltaic properties of multilayered devices consisting of ITO/oxide/Tetraphenyl porphyrin (H2TPP)/Fullerene (C60)/Bathocuproine (BCP)/Al structures. The VOC markedly increases with the insertion of NiO and MoO3 hole collection layers. However, the "kink" behaviors and temperature dependent properties are observed for the devices with and without MoO3 especially for the thick H2TPP film. We demonstrated the analysis of the photovoltaic properties using the Poole-Frenkel and Schottky models based on the dielectric behaviors of porphyrin and MoO3 layers.
This paper presents a novel time-domain design procedure for fast-settling three-stage nested-Miller compensated (NMC) amplifiers. In the proposed design methodology, the amplifier is designed to settle within a definite time period with a given settling accuracy by optimizing both the power consumption and silicon die area. Detailed design equations are presented and the circuit level simulation results are provided to verify the usefulness of the proposed design procedure with respect to the previously reported design schemes.
Lihong SHANG Mi ZHOU Yu HU Erfu YANG
Field programmable gate arrays (FPGAs) are widely used in reliability-critical systems due to their reconfiguration ability. However, with the shrinking device feature size and increasing die area, nowadays FPGAs can be deeply affected by the errors induced by electromigration and radiation. To improve the reliability of FPGA-based reconfigurable systems, a permanent fault recovery approach using a domain partition model is proposed in this paper. In the proposed approach, the fault-tolerant FPGA recovery from faults is realized by reloading a proper configuration from a pool of multiple alternative configurations with overlaps. The overlaps are presented as a set of vectors in the domain partition model. To enhance the reliability, a technical procedure is also presented in which the set of vectors are heuristically filtered so that the corresponding small overlaps can be merged into big ones. Experimental results are provided to demonstrate the effectiveness of the proposed approach through applying it to several benchmark circuits. Compared with previous approaches, the proposed approach increased MTTF by up to 18.87%.
It is necessary to perform arithmetic in Fp12 to use an Ate pairing on a Barreto-Naehrig (BN) curve, where p is a prime given by p(z)=36z4+36z3+24z2+6z+1 for some integer z. In many implementations of Ate pairings, Fp12 has been regarded as a 6th degree extension of Fp2, and it has been constructed by Fp12=Fp2[v]/(v6-ξ) for an element ξ ∈ Fp2 such that v6-ξ is irreducible in Fp2[v]. Such a ξ depends on the value of p, and we may use a mathematical software package to find ξ. In this paper it is shown that when z ≡ 7,11 (mod 12), we can universally construct Fp12 as Fp12=Fp2[v]/(v6-u-1), where Fp2=Fp[u]/(u2+1).
Saiyan SAIYOD Sakchai THIPCHAKSURAT Ruttikorn VARAKULSIRIPUNTH
In wireless OFDM systems, the system performance is suffered from frequency offset and symbol timing offset due to the Doppler effect. Using the discrete Fourier transform (DFT) and inverse discrete Fourier transform (IDFT) for traditional signal transformation from the time-domain into frequency-domain, and vice versa, the system performance may be severely degraded. To make the OFDM system that can tolerate the above problems, we have considered that the harmonic transform can be applicable to the traditional signal transformation, thereby improving the system performance. In this paper, we combine the good characteristics of harmonic transform and instantaneous frequency to be a novel transformation for wireless OFDM systems. We propose a modified discrete harmonic transform (MDHT) which can be performed adaptively. Our proposed scheme called the modified discrete harmonic transform OFDM (MDHT-OFDM scheme). We derive the equations of the novel discrete harmonic transform which are suitable for wireless OFDM systems and the novel channel estimation cooperated with the novel transformation. The proposed channel estimation is performed in both time-domain and frequency-domain. The performance of a MDHT-OFDM scheme is evaluated by means of a simulation. We compare the performance of a MDHT-OFDM scheme with one of the conventional DFT-OFDM scheme in the term of symbol error rate (SER). MDHT-OFDM scheme can achieve better performance than that of the conventional DFT-OFDM scheme in mitigating the Doppler spread.
While volunteer computing (VC) systems reach the most powerful computing platforms, they still have the problem of guaranteeing computational correctness, due to the inherent unreliability of volunteer participants. Spot-checking technique, which checks each participant by allocating spotter jobs, is a promising approach to the validation of computation results. The current spot-checking is based on the implicit assumption that participants never distinguish spotter jobs from normal ones; however generating such spotter jobs is still an open problem. Hence, in the real VC environment where the implicit assumption does not always hold, spot-checking-based methods such as well-known credibility-based voting become almost impossible to guarantee the computational correctness. In this paper, we generalize spot-checking by introducing the idea of imperfect checking. This generalization allows to guarantee the computational correctness under the situation that spot-checking is not fully-reliable and participants may distinguish spotter jobs. Moreover, we develop a generalized formula of the credibility, which enables credibility-based voting to utilize check-by-voting technique. Simulation results show that check-by-voting improves the performance of credibility-based voting, while guaranteeing the same level of computational correctness.
Kazuteru NAMBA Kengo NAKASHIMA Hideo ITO
This paper presents a construction of a single-event-upset (SEU) tolerant reset-set (RS) flip-flop (FF). The proposed RS-FF consists of four identical parts which form an interlocking feedback loop just like DICE. The area and average power consumption of the proposed RS-FFs are 1.101.48 and 1.201.63 times smaller than those of the conventional SEU tolerant RS-FFs, respectively.
Min ZHU Leibo LIU Shouyi YIN Chongyong YIN Shaojun WEI
This paper introduces a cycle-accurate Simulator for a dynamically REconfigurable MUlti-media System, called SimREMUS. SimREMUS can either be used at transaction-level, which allows the modeling and simulation of higher-level hardware and embedded software, or at register transfer level, if the dynamic system behavior is desired to be observed at signal level. Trade-offs among a set of criteria that are frequently used to characterize the design of a reconfigurable computing system, such as granularity, programmability, configurability as well as architecture of processing elements and route modules etc., can be quickly evaluated. Moreover, a complete tool chain for SimREMUS, including compiler and debugger, is developed. SimREMUS could simulate 270 k cycles per second for million gates SoC (System-on-a-Chip) and produced one H.264 1080p frame in 15 minutes, which might cost days on VCS (platform: CPU: E5200@ 2.5 Ghz, RAM: 2.0 GB). Simulation showed that 1080p@30 fps of H.264 High Profile@ Level 4 can be achieved when exploiting a 200 MHz working frequency on the VLSI architecture of REMUS.
Yutaro NAKAGAWA Yukitoshi SANADA
In this letter, a new feedback equalization scheme to suppress inter-carrier interference (ICI) in an OFDM system using scattered pilot is investigated. On a fast fading channel severe ICI occurs due to a Doppler shift and it deteriorates a bit error rate (BER) seriously because of small subcarrier spacing. In an ISDB-T receiver the equalization is mainly processed in a frequency domain because the scattered pilot is transmitted over the subcarriers. However, the frequency domain equalization may not suppress severe ICI in the case of the fast fading channel with a large Doppler shift. The proposed equalization scheme uses the scattered pilot symbols transformed in a time domain as the reference signal for feedback taps. Numerical results through computer simulation show that the proposed scheme improves the BER performance especially with low carrier-to-noise ratio (CNR) conditions.