This paper presents a fault-tolerance scheme based on mobile agents for the reliable mobile computing systems. Mobility of the agent is suitable to trace the mobile hosts and the intelligence of the agent makes it efficient to support the fault tolerance services. This paper presents two approaches to implement the mobile agent based fault tolerant service and their performances are evaluated and compared with other fault-tolerant schemes.

We provide an efficient transmission scheme which embeds a pilot signal in the data signal for channel state information (CSI) based on the configuration of a multiple-input multiple-output (MIMO) system using space-time block coding (STBC) with an adaptive array (AA). A computer simulation and analysis show that the proposed scheme, which combines the advantage of an Alamouti-like STBC scheme and the pilot-based AA, can suppress the irreducible error due to random FM noise. The proposed scheme using a pilot minimizes the decoding delay, and is highly robust against fast fading. We show that the proposed scheme can significantly increase the data transmission rate by using the transmitter diversity based on STBC, and the accuracy of the proposed technique is exemplified by a computer simulation.

It is important to improve a cell-edge throughput of next generation mobile communication systems. Frequency reuse schemes such as three-cell reuse or fractional frequency reuse are suitable for achieving this goal. Another candidate is multi-link transmission; signals on different sub-carriers from adjacent base stations are received by a mobile. However, the orthogonality of these signals can collapse if a frequency offset between adjacent base stations is excessive; this loss triggers adjacent-channel interference. This paper proposes an interference canceller to solve this problem and confirms the effectiveness of the method through numerical analysis and computer simulations.

Custody transfer in delay tolerant networks (DTNs) provides reliable end-to-end data delivery by delegating the responsibility of data transfer among special nodes (custodians) in a hop-by-hop manner. However, storage congestion occurs when data increases and/or the network is partitioned into multiple sub-networks for a long time. The storage congestion can be alleviated by message ferries which move around the network and proactively collect data from the custodians. In such a scenario, data should be aggregated to some custodians so that message ferries can collect them effectively. In this paper, we propose a scheme to aggregate data into selected custodians, called aggregators, in a fully distributed and autonomous manner with the help of evolutionary game theoretic approach. Through theoretical analysis and several simulation experiments, taking account of the uncooperative behavior of nodes, we show that aggregators can be selected in a self-organized manner and the number of aggregators can be controlled to a desired value.

A proposed pseudo fractional-N clock generator with 50% duty cycle output is presented by using the pseudo fractional-N controller for SoC chips and the dynamic frequency scaling applications. The different clock frequencies can be generated with the particular phase combinations of a four-stage voltage-controlled oscillator (VCO). It has been fabricated in a 0.13 µm CMOS technology, and work with a supply voltage of 1.2 V. According to measured results, the frequency range of the proposed pseudo fractional-N clock generator is from 71.4 MHz to 1 GHz and the peak-to-peak jitter is less than 5% of the output period. Duty cycle error rates of the output clock frequencies are from 0.8% to 2% and the measured power dissipation of the pseudo fractional-N controller is 146 µW at 304 MHz.

This paper presents a proposal of an expected-credibility-based job scheduling method for volunteer computing (VC) systems with malicious participants who return erroneous results. Credibility-based voting is a promising approach to guaranteeing the computational correctness of VC systems. However, it relies on a simple round-robin job scheduling method that does not consider the jobs' order of execution, thereby resulting in numerous unnecessary job allocations and performance degradation of VC systems. To improve the performance of VC systems, the proposed job scheduling method selects a job to be executed prior to others dynamically based on two novel metrics: expected credibility and the expected number of results for each job. Simulation of VCs shows that the proposed method can improve the VC system performance up to 11%; It always outperforms the original round-robin method irrespective of the value of unknown parameters such as population and behavior of saboteurs.

In this letter, a broadband coupler is presented that makes use of a half mode substrate integrated waveguide (HMSIW) technique using a printed circuit board process. The coupler is realized by a parallel HMSIW line which couples energy by magnetic field. Compared with micro-strip coupler and conventional HMSIW coupler, it has lower loss and better Electromagnetic Compatibility owning to the closed field structure. Compared with SIW coupler, it has smaller size and lower cost owing to the half TE10 model. The coupler is simulated and measured at 8-12 GHz. Measured results show a good agreement with simulation.

Partial plasma polymerization for coexistence of hydrophobic/hydrophilic area in several ten micrometer size is the typical technique for protein patterning. A hydrophobic hexamethyldisiloxane plasma-polymerized film (HMDS PPF) was deposited on a glass substrate and this surface was partially modified by subsequent nitrogen plasma treatment (hydrophilic surface, HMDS-N PPF) with a patterned shadow mask. An antibody protein (F(ab')2 fragment of anti-human immunoglobulin G) was selectively adsorbed onto the HMDS-N area and was not adsorbed onto the HMDS area. Distinct 8080 µm2 square spots surrounded by a non-protein adsorbed 80 µm-wide grid were observed. Then, when the protein modified by fullerene was used, the reversible patterning was obtained. This indicated that the modification by fullerene changed the hydrophilic nature of F(ab')2 protein to hydrophobic one, as a result, the modified protein was selectively adsorbed onto hydrophobic area.

This paper presents a numerical approach to the time-domain analysis of N-branch-line couplers. The approach is based on the modified central difference (MCD) method combined with internal boundary treatments, which consist of the time-domain scattering matrix for the three-port junction discontinuity. The behavior of the signal propagation including multiple reflections on the N-branch-line coupler with and without line loss is analyzed and demonstrated in the time domain. Additionally, the S-parameters obtained from Gaussian pulse responses of the N-branch-line directional couplers are shown. The simulated results are in good agreement with those of the commercial simulator.

We propose a novel epidemic routing policy, named energy optimal epidemic routing, for delay tolerant networks (DTNs). By investigating the tradeoff between delay and energy, we found the optimal transmission range as well as the optimal number of infected nodes for the minimal energy consumption, given a delivery requirement, specifically delay bound and delivery probability to the destination. We derive an analytic model of the Binary Spraying routing to find the optimal values, describing the delay distributions with respect to the number of infected nodes.

Based on provided convenient design equations for slow wave transmission lines and metamaterial line, a very compact rat-race hybrid coupler is proposed using three slow wave lines and one metamaterial line. At the design frequency of 2 GHz, the size of the proposed coupler is 2.3 cm2.7 cm, which is a 74% reduction compared with the conventional one. Despite the considerable size reduction, the theoretical bandwidths based on | S11|, | S31|, ∠ S21-∠ S31, and ∠ S24-∠ S34, have been improved by 9%, 7%, 31%, and 59%, respectively. The measured performances are in reasonable agreement with the theoretical ones.

Partial forwarding is a design method to place forwarding paths on a part of processor pipeline. Hardware cost of processor can be reduced without performance loss by partial forwarding. However, compiler with the instruction scheduler which considers partial forwarding structure of the target processor is required since conventional scheduling algorithm cannot make the most of partial forwarding structure. In this paper, we propose a heuristic instruction scheduling method for processors with partial forwarding structure. The proposed algorithm uses available distance to schedule instructions which are suitable for the target partial forwarding processor. Experimental results show that the proposed method generates near-optimal solutions in practical time and some of the optimized codes for partial forwarding processor run in the shortest time among the target processors. It also shows that the proposed method is superior to hazard detection unit.

As device feature size decreases, interconnection delay becomes the dominating factor of circuit total delay. Distributed-register architectures can reduce the influence of interconnection delay. They may, however, increase circuit area because they require many local registers. Moreover original distributed-register architectures do not consider control signal delay, which may be the bottleneck in a circuit. In this paper, we propose a high-level synthesis method targeting generalized distributed-register architecture in which we introduce shared/local registers and global/local controllers. Our method is based on iterative improvement of scheduling/binding and floorplanning. First, we prepare shared-register groups with global controllers, each of which corresponds to a single functional unit. As iterations proceed, we use local registers and local controllers for functional units on a critical path. Shared-register groups physically located close to each other are merged into a single group. Accordingly, global controllers are merged. Finally, our method obtains a generalized distributed-register architecture where its scheduling/binding as well as floorplanning are simultaneously optimized. Experimental results show that the area is decreased by 4.7% while maintaining the performance of the circuit equal with that using original distributed-register architectures.

Multitude parameters in the design process of a reconfigurable instruction-set processor (RISP) may lead to a large design space and remarkable complexity. Quantitative design approach uses the data collected from applications to satisfy design constraints and optimize the design goals while considering the applications' characteristics; however it highly depends on designer observations and analyses. Exploring design space can be considered as an effective technique to find a proper balance among various design parameters. Indeed, this approach would be computationally expensive when the performance evaluation of the design points is accomplished based on the synthesis-and-simulation technique. A combined analytical and simulation-based model (CAnSO**) is proposed and validated for performance evaluation of a typical RISP. The proposed model consists of an analytical core that incorporates statistics collected from cycle-accurate simulation to make a reasonable evaluation and provide a valuable insight. CAnSO has clear speed advantages and therefore it can be used for easing a cumbersome design space exploration of a reconfigurable RISP processor and quick performance evaluation of slightly modified architectures.

This paper presents a measurement method for determining effective conductivity of copper-clad dielectric laminate substrates in the millimeter-wave region. The conductivity is indirectly evaluated from measured resonant frequencies and unloaded Q values of a number of Whispering Gallery modes excited in a circular disk sample, which consists of a copper-clad dielectric substrate with a large diameter of 20-30 wavelengths. We can, therefore, obtain easily the frequency dependence of the effective conductivity of the sample under test in a wide range of frequency at once. Almost identical conductivity is predicted for two kinds of WG resonators (the copper-clad type and the sandwich type) with different field distribution; it is self-consistent and provides the important foundation for the method if not for the alternative method at this moment. We measure three kinds of copper foils in 55-65 GHz band, where the conductivity of electrodeposited copper foil is smaller than that of rolled copper foil and shiny-both-sides copper foil. The measured conductivity for the electrodeposited copper foil decreases with an increase in the frequency. The transmission losses measured for microstrip lines which are fabricated from these substrates are accurately predicted with the conductivity evaluated by this method.

Recently, many researchers tackle accurate object recognition algorithms and many algorithms are proposed. However, these algorithms have some problems caused by variety of real environments such as a direction change of the object or its shading change. The new tracking algorithm, Cascade Particle Filter, is proposed to fill such demands in real environments by constructing the object model while tracking the objects. We have been investigating to implement accurate object recognition on embedded systems in real-time. In order to apply the Cascade Particle Filter to embedded applications such as surveillance, automotives, and robotics, a hardware accelerator is indispensable because of limitations in power consumption. In this paper we propose a hardware implementation of the Discrete AdaBoost algorithm that is the most computationally intensive part of the Cascade Particle Filter. To implement the proposed hardware, we use PICO Express, a high level synthesis tool provided by Synfora, for rapid prototyping. Implementation result shows that the synthesized hardware has 1,132,038 transistors and the die area is 2,195 µm 1,985 µm under a 0.180 µm library. The simulation result shows that total processing time is about 8.2 milliseconds at 65 MHz operation frequency.

Delay Tolerant Networks (DTNs) are able to provide communication services in challenged networks where the end-to-end path between the source and destination does not exist. In order to increase the probability of message delivery, DTN routing mechanisms require nodes in the network to store and carry messages in their local buffer and to replicate many copies. When the limited buffer is consumed, choosing appropriate messages to discard is critical to maximizing the system performance. Current approaches for this are sub-optimal or assumed unrealistic conditions. In this paper, we propose an optimal buffer management scheme for the realistic situations where the bandwidth is limited and messages vary in size. In our scheme, we design a message discard policy that maximizes the message delivery rate. Simulation results demonstrate the efficiency of our proposal.

This paper proposes an architecture of an interference canceller for satellite communications with super-posed transmission, which is applicable not only to QPSK but also to 16QAM transmission to get higher satellite capacity. We implement it as an FPGA-based prototype and verify its performance. We propose here to use a new method to measure the satellite round-trip delay using an extended matched filter (EMF), which can work in low C/N conditions such as 0 dB and under. Given this performance, our canceller can work in a network in which forward and reverse links have the same power level. The results of the laboratory tests for QPSK show that interference can be suppressed by about 30 dB and that the BER degradation due to the canceller was small enough for operation.

This paper proposes a frequency asynchronous cross-polarization interference canceller for Vertical/Horizontal (V/H) polarization multiplexing satellite communications. In satellite communications, V/H polarization signals are likely to experience different frequency fluctuations, and so the cross-polarization undergoes two different frequency fluctuations. To cancel this cross-polarization interference, a new frequency asynchronous cross-polarization interference canceller that removes interference and frequency offsets is proposed. Computer simulations are carried out to evaluate its fundamental performance. The results show that the proposed canceller can remove the cross-polarization interference created by the two different frequency offsets, simultaneously.

In this letter, Doppler spread estimation in different Doppler spectra is investigated and some efficient methods are proposed to calculate the maximum Doppler frequency from autocorrelation function easily.