We propose a learning strategy for acceleration in learning speed of genetic programming (GP), named hierarchical structure GP (HSGP). The HSGP exploits multiple learning nodes (LNs) which are connected in a hierarchical structure, e.g., a binary tree. Each LN runs conventional evolutionary process to evolve its own population, and sends the evolved population into the connected higher-level LN. The lower-level LN evolves the population with a smaller subset of training data. The higher-level LN then integrates the evolved population from the connected lower-level LNs together, and evolves the integrated population further by using a larger subset of training data. In HSGP, evolutionary processes are sequentially executed from the bottom-level LNs to the top-level LN which evolves with the entire training data. In the experiments, we adopt conventional GPs and the HSGPs to evolve image recognition programs for given training images. The results show that the use of hierarchical structure learning can significantly improve learning speed of GPs. To achieve the same performance, the HSGPs need only 30-40% of the computation cost needed by conventional GPs.

Access to information is taken for granted in urban areas covered by a robust communication infrastructure. Nevertheless most of the areas in the world, are not covered by such infrastructures. We propose a DTN publish and subscribe system called Hikari, which uses nodes' mobility in order to distribute messages without using a robust infrastructure. The area of Disruption/Delay Tolerant Networks (DTN) focuses on providing connectivity to locations separated by networks with disruptions and delays. The Hikari system does not use node identifiers for message forwarding thus eliminating the complexity of routing associated with many forwarding schemes in DTN. Hikari uses nodes paths' information, advertised by special nodes in the system or predicted by the system itself, for optimizing the message dissemination process. We have used the Paris subway system, due to it's complexity, to validate Hikari and to analyze it's performance. We have shown that Hikari achieves a superior deliver rate while keeping redundant messages in the system low, which is ideal when using devices with limited resources for message dissemination.

A novel 300 MHz embedded flash memory for dual-core microcontrollers with a shared ROM architecture is proposed. One of its features is a three-stage pipeline read operation, which enables reduced access pitch and therefore reduces performance penalty due to conflict of shared ROM accesses. Another feature is a highly sensitive sense amplifier that achieves efficient pipeline operation with two-cycle latency one-cycle pitch as a result of a shortened sense time of 0.63 ns. The combination of the pipeline architecture and proposed sense amplifiers significantly reduces access-conflict penalties with shared ROM and enhances performance of 32-bit RISC dual-core microcontrollers by 30%.

GaAs MMICs (Monolithic Microwave Integrated Circuits) reliability is a critical part of the overall reliability of the thermal solution in semiconductor devices. With MMICs reliability improved, GaAs MMICs failure rates will reach levels which are impractical to measure with conventional methods in the near future. This letter proposes a methodology to predict the GaAs MMICs reliability by combining empirical and statistical methods based on zero-failure GaAs MMICs life testing data. Besides, we investigate the effect of accelerated factors on MMICs degradation and make a comparison between the Weibull and lognormal distributions. The method has been used in the reliability evaluation of GaAs MMICs successfully.

In this Letter, a robust system identification method is proposed for the generalized sidelobe canceller using dual microphones. The conventional transfer-function generalized sidelobe canceller employs the non-stationarity characteristics of the speech signal to estimate the relative transfer function and thus is difficult to apply when the noise is also non-stationary. Under the assumption of W-disjoint orthogonality between the speech and the non-stationary noise, the proposed algorithm finds the speech-dominant time-frequency bins of the input signal by inspecting the system output and the inter-microphone time delay. Only these bins are used to estimate the relative transfer function, so reliable estimates can be obtained under non-stationary noise conditions. The experimental results show that the proposed algorithm significantly improves the performance of the transfer-function generalized sidelobe canceller, while only sustaining a modest estimation error in adverse non-stationary noise environments.

It is said that the lower bound of the number of iterations of Miller's algorithm for pairing calculation is log 2r/(k), where () is the Euler's function, r is the group order, and k is the embedding degree. Ate pairing reduced the number of the loops of Miller's algorithm of Tate pairing from ⌊log 2r⌋ to ⌊ log 2(t-1)⌋, where t is the Frobenius trace. Recently, it is known to systematically prepare a pairing-friendly elliptic curve whose parameters are given by a polynomial of integer variable "χ." For such a curve, this paper gives integer variable χ-based Ate (Xate) pairing that achieves the lower bound. In the case of the well-known Barreto-Naehrig pairing-friendly curve, it reduces the number of loops to ⌊log 2χ⌋. Then, this paper optimizes Xate pairing for Barreto-Naehrig curve and shows its efficiency based on some simulation results.

Frequent Itemsets(FI) mining is a popular and important first step in analyzing datasets across a broad range of applications. There are two main problems with the traditional approach for finding frequent itemsets. Firstly, it may often derive an undesirably huge set of frequent itemsets and association rules. Secondly, it is vulnerable to noise. There are two approaches which have been proposed to address these problems individually. The first problem is addressed by the approach Frequent Closed Itemsets(FCI), FCI removes all the redundant information from the result and makes sure there is no information loss. The second problem is addressed by the approach Approximate Frequent Itemsets(AFI), AFI could identify and fix the noises in the datasets. Each of these two concepts has its own limitations, however, the authors find that if FCI and AFI are put together, they could help each other to overcome the limitations and amplify the advantages. The new integrated approach is termed Noise-tolerant Frequent Closed Itemset(NFCI). The results of the experiments demonstrate the advantages of the new approach: (1) It is noise tolerant. (2) The number of itemsets generated would be dramatically reduced with almost no information loss except for the noise and the infrequent patterns. (3) Hence, it is both time and space efficient. (4) No redundant information is in the result.

A rotary inverted pendulum is stabilized by a single first order dynamic output feedback system. Numerical simulations and experimental results show that the proposed control law has low-pass filter property as well as it can successfully replace the velocity measurements for LQR control law.

This study utilizes a new adaptive sense current controller to get an accurate power supply. The proposed controller effectively reduces output ripple voltage of converters operated over the load current range. This reduction is realized using an adaptive sense current circuit that automatically adjusts the inductor current according to operational conditions. The proposed boost converter is designed and fabricated with a standard TSMC 3.3/5 V 0.35-µm 2P4M CMOS technology. The experimental results show that the power-conversion efficiency of the proposed boost converter is 2-5% higher than that of the conventional converter with a current-limited circuit. The proposed circuit greatly reduces (i.e. by 76%) output ripple voltage compared with the conventional circuit at a 10 mA loading current.

Electrical life is an important parameter to estimate the reliability of a relay, and it is greatly affected by load current. In order to shorten the time of life test, load current stress accelerated life tests were carried out by using a life test system designed for relay in this paper. During the life test, many parameters such as the contact resistance, the closing time and the over-travel time of relay were measured for each operation to identify the failure modes. After the life test, the failure mechanisms under each current stress, which cause the same failure mode, were analyzed by investigating the variations of parameters and observing the morphology of contact surface. In addition, for the purpose of further studying the consistency of failure mechanisms between different current stress, a Weibull statistical analysis was adopted to estimate the shape parameter of Weibull distribution because the same shape parameter means the same failure mechanism. Finally, a statistical model for estimating the lifetime under load current stress was built. The research methods and conclusions mentioned in this paper are meaningful to perform the accelerated life tests for other types of relays.

Recently, it has become important to rapidly detect human subjects buried under collapsed houses, rubble and soil due to earthquakes and avalanches to reduce the casualties in a disaster. Such detection systems have already been developed as one kind of microwave displacement sensors that are based on phase difference generated by the motion of the subject's breast. Because almost all the systems consist of single transmitter and receiver pair, it is difficult to rapidly scan a wide area. In this paper, we propose a single-frequency multistatic radar system to detect breathing human subjects which exist in the area surrounded by the transmitting and receiving array. The vibrating targets can be localized by the MUSIC algorithm with the complex amplitude in the Doppler frequency. This algorithm is validated by the simulated signals synthesized with a rigorous solution of a dielectric spherical target model. We show experimental 3D localization results using a developed multistatic Doppler radar system around 250 MHz.

In recent years, the space-time block coding (STBC) method has attracted attention to provide transmission diversity in mobile communication systems. Although the STBC method is very effective in slow fading environments, its performance in fast fading environments has yet to be clearly verified. In this paper we propose a railway radio communication system using space-time coding in cooperation with two base stations. Here, we considered the differential STBC (D-STBC) method in railway communication system to overcome difficulties caused by the fast fading environment. We have compared the performance of STBC and D-STBC method where there is frequency offset between two base stations. Moreover, we have presented the simulation result of overall performance of the system including frequency offset and transmission time delay when operating D-STBC method. The overall evaluation on this paper shows that the D-STBC method is suitable for realizing highly reliable railway communication systems.

A high-speed and ultra-low-voltage divide-by-4/5 counter with dynamic floating input D flip-flop (DFIDFF) is presented in this paper. The proposed DFIDFF and control logic gates are merged to reduce effective capacitance of internal and external nodes, and increase the operating speed of divide-by-4/5 counter. The proposed divide-by-4/5 counter is fabricated in a 0.13-µm CMOS process. The measured maximum operating frequency and power consumption of the counter are 600 MHz and 8.35 µW at a 0.5 V supply voltage. HSPICE simulations demonstrate that the proposed counter (divide-by-4) reduces power-delay product (PDP) by 37%, 71%, and 57% from those of the TGFF counter, Yang's counter [1], and the E-TSPC counter [2], respectively.

In this letter, a novel blind maximum Doppler frequency estimation algorithm for OFDM based systems is proposed. We only utilize part of the subcarriers which are modulated by constant-envelope modulation such as QPSK. The received magnitude of these subcarriers is obtained and its power spectral density (PSD) is estimated by classic periodogram method. The maximum Doppler frequency is derived by finding the edge point of PSD. Different from the conventional PSD method, our method does not need the channel estimates, the estimation precision is also increased. Simulation results show that the performance of our method is good for a wide range of Doppler spread values.

The wireless sensor network is a resource-constrained self-organizing system that consists of a large number of tiny sensor nodes. Due to the low-cost and low-power nature of sensor nodes, sensor nodes are failure-prone when sensing and processing data. Most presented fault-tolerant research for wireless sensor networks focused on crash faults or power faults and less on Byzantine faults. Hence, in this paper, we propose a power-saving data aggregation algorithm for Byzantine faults to provide power savings and high success rates even in the environment with high fault rates. The algorithm utilizes the concept of Byzantine masking quorum systems to mask the erroneous values and to finally determine the correct value. Our simulation results demonstrate that when the fault rate of sensor nodes is up to 50%, our algorithm still has 48% success rate to obtain the correct value. Under the same condition, other fault-tolerant algorithms are almost failed.

Almost all the existing secret sharing schemes are based on a single dealer. Maybe in some situations, the secret needs to be maintained by multiple dealers. In this paper, we proposed a novel secret sharing scheme based on the multi-dealer by means of Shamir's threshold scheme and T. Okamoto and S. Uchiyama's public-key cryptosystem. Multiple dealers can commonly maintain the secret and the secret can be dynamically renewed by any dealer. Meanwhile, the reusable secret shadows just needs to be distributed only once. In the secret updated phase, the dealer just needs to publish a little public information instead of redistributing the new secret shadows. Its security is based on the security of Shamir's threshold scheme and the intractability of factoring problem and discrete logarithm problem.

In this letter, we propose a simple but accurate calculation method, that is, an approximate closed-form equation of average bit error rate in DPSK/OFDM systems with post-detection diversity reception over both time- and frequency-selective Rayleigh fading channels. The validity of the proposed method is verified by the fact that BER performances given by the derived equation coincide with those by Monte Carlo simulation.

A new conditional isolation technique (CI-Domino) in domino logic is proposed for wide domino gates. This technique can not only reduce the subthreshold and gate oxide leakage currents simultaneously without sacrificing circuit performance, but also it can be utilized to speed up the evaluation time of domino gate. Simulations on high fan-in domino OR gates with 0.18 µm process technology show that the proposed technique achieves reduction on total static power by 36%, dynamic power by 49.14%, and delay time by 60.27% compared to the conventional domino gate. Meanwhile, the proposed technique also gains about 48.14% improvement on leakage tolerance.

An on-chip power supply noise canceller with higher voltage supply and switching transistor is proposed and the effectiveness of the canceller is experimentally verified. The noise canceller is effective for nano-second order noise caused by circuit wakeup or step increase of frequency in frequency hopping. The principle of the noise canceller is to reduce the current flowing through the supply line of VDD by injecting additional current from the higher voltage supply, so that the voltage drop across the VDD supply line is reduced. As additional current flow from higher supply, switching transistor has to be turned off not to increase the power consumption. With turn-off time of 2L/R, this current can be turned off without inducting another droop due to the increase of current flowing through the power supply line. The measurement shows the canceller reduces 68% of the noise with load circuit equivalent to 530 k logic gates in 90-nm CMOS with 9% wire overhead, 1.5% area overhead, and 3% power overhead at 50 k wake-ups/s. Compared to passive noise reduction, proposed noise canceller reduces power supply noise by 64% without wire overhead and to achieve same noise reduction with passive method, 77 times more C or 45 times less L is required. Too large switching transistor results in saturated noise reduction effect and higher power consumption. A rule-of-thumb is to set the on-resistance to supply 100% of load current when turned-on.

In the arsenal of resources for computer memory system performance improvement, predictors have gained an increasing role in the past years. They can suppress the latencies when accessing cache or main memory. In paper [1] it is shown how temporal parameters of cache memory access, defined as live time, dead time and access interval could be used for prediction of data prefetching. This paper examines the feasibility of applying an analog technique on controlling of opening/closing DRAM memory rows, with various improvements. The results described herein confirm the feasibility, and allow us to propose a DRAM controller with predictors that not only close the opened DRAM row, but also predict the next row to be opened.