In this paper, we develop a new iterative turbo multiuser detector for direct sequence code-division multiple access (DS-CDMA) systems over unknown frequency-selective channels by decomposing the observation signal into a number of signal components. Virtual trellis model representing the ISI channel for each separating signal user is designed to generate extrinsic probability in term of BCJR algorithm for exchange with a single channel decoder as priori information. Minimum kullback-leibler (MKL) framework is derived to calculate numerical channel estimation and extrinsic probability. In comparison with other similar receiver, simulation results demonstrate that the proposed solution achieves the desirable performance.

One of the major challenges facing the design of a routing protocol for Wireless Sensor Networks (WSNs) is to find the most reliable path between the source and sink node. Furthermore, a routing protocol for WSN should be well aware of sensor limitations. In this paper, we present an energy efficient, scalable, and distributed node disjoint multipath routing algorithm. The proposed algorithm, the Energy-aware Multipath Routing Algorithm (EMRA), adjusts traffic flows via a novel load balancing scheme. EMRA has a higher average node energy efficiency, lower control overhead, and a shorter average delay than those of well-known previous works. Moreover, since EMRA takes into consideration network reliability, it is useful for delivering data in unreliable environments.

The steady approach of advanced nations toward realization of ubiquitous computing societies has given birth to rapidly growing demands for new-generation distributed computing (DC) applications. Consequently, economic and reliable construction of new-generation DC applications is currently a major issue faced by the software technology research community. What is needed is a new-generation DC software engineering technology which is at least multiple times more effective in constructing new-generation DC applications than the currently practiced technologies are. In particular, this author believes that a new-generation building-block (BB), which is much more advanced than the current-generation DC object that is a small extension of the object model embedded in languages C++, Java, and C#, is needed. Such a BB should enable systematic and economic construction of DC applications that are capable of taking critical actions with 100-microsecond-level or even 10-microsecond-level timing accuracy, fault tolerance, and security enforcement while being easily expandable and taking advantage of all sorts of network connectivity. Some directions considered worth pursuing for finding such BBs are discussed.

In this paper, two new clustering algorithms based on fuzzy c-means for data with tolerance using kernel functions are proposed. Kernel functions which map the data from the original space into higher dimensional feature space are introduced into the proposed algorithms. Nonlinear boundary of clusters can be easily found by using the kernel functions. First, two clustering algorithms for data with tolerance are introduced. One is based on standard method and the other is on entropy-based one. Second, the tolerance in feature space is discussed taking account into soft margin algorithm in Support Vector Machine. Third, two objective functions in feature space are shown corresponding to two methods, respectively. Fourth, Karush-Kuhn-Tucker conditions of two objective functions are considered, respectively, and these conditions are re-expressed with kernel functions as the representation of an inner product for mapping from the original pattern space into a higher dimensional feature space. Fifth, two iterative algorithms are proposed for the objective functions, respectively. Through some numerical experiments, the proposed algorithms are discussed.

A Lyapunov-based recurrent neural networks unified power flow controller (UPFC) is developed for improving transient stability of power systems. First, a simple UPFC dynamical model, composed of a controllable shunt susceptance on the shunt side and an ideal complex transformer on the series side, is utilized to analyze UPFC dynamical characteristics. Secondly, we study the control configuration of the UPFC with two major blocks: the primary control, and the supplementary control. The primary control is implemented by standard PI techniques when the power system is operated in a normal condition. The supplementary control will be effective only when the power system is subjected by large disturbances. We propose a new Lyapunov-based UPFC controller of the classical single-machine-infinite-bus system for damping enhancement. In order to consider more complicated detailed generator models, we also propose a Lyapunov-based adaptive recurrent neural network controller to deal with such model uncertainties. This controller can be treated as neural network approximations of Lyapunov control actions. In addition, this controller also provides online learning ability to adjust the corresponding weights with the back propagation algorithm built in the hidden layer. The proposed control scheme has been tested on two simple power systems. Simulation results demonstrate that the proposed control strategy is very effective for suppressing power swing even under severe system conditions.

This paper is about an efficient implementation of adaptive filtering for echo cancelers. The first objective of this paper is to propose a simplified method of the flexible block Multi-Delay Filter (MDF) algorithm in the time-domain. Then, we will derive a new method for the step-size adaptation coefficient. The second objective is about the realization of a Block Proportionate Normalized Least Mean Squares (BPNLMS++) with the simplified MDF (SMDF) implementation. Using the new step-size method and the smaller block dimension proposed by SMDF, we achieve a faster convergence of the adaptive process with a limited computational cost. Then, an efficient implementation of the new procedure (SMDF-BPNLMS++) block filtering is proposed using Fermat Number Transform, which can significantly reduce the computation complexity of filter implantation on Digital Signal Processor.

In this paper, we present a reconfigurable processor infrastructure to accelerate Java applications, called Jaguar. The Jaguar infrastructure consists of a compiler framework and a runtime environment support. The compiler framework selects a group of Java methods to be translated into hardware for delivering the best performance under limited resources, and translates the selected Java methods into Verilog synthesizable code modules. The runtime environment support includes the Java virtual machine (JVM) running on a host processor to provide Java execution environment to the generated Java accelerator through communication interface units while preserving Java semantics. Our compiler infrastructure is a tightly integrated and solid compiler-aided solution for Java reconfigurable computing. There is no limitation in generating synthesizable Verilog modules from any Java application while preserving Java semantics. In terms of performance, our infrastructure achieves the speedup by 5.4 times on average and by up to 9.4 times in measured benchmarks with respect to JVM-only execution. Furthermore, two optimization schemes such as an instruction folding and a live buffer removal can reduce 24% on average and up to 39% of the resource consumption.

In multiple-input multiple-output (MIMO) wireless systems, the receiver must extract each transmitted signal from received signals. Iterative signal detection with belief propagation (BP) can improve the error rate performance, by increasing the number of detection and decoding iterations in MIMO systems. This number of iterations is, however, limited in actual systems because each additional iteration increases latency, receiver size, and so on. This paper proposes a convergence acceleration technique that can achieve better error rate performance with fewer iterations than the conventional iterative signal detection. Since the Log-Likelihood Ratio (LLR) of one bit propagates to all other bits with BP, improving some LLRs improves overall decoder performance. In our proposal, all the coded bits are divided into groups and only one group is detected in each iterative signal detection whereas in the conventional approach, each iterative signal detection run processes all coded bits, simultaneously. Our proposal increases the frequency of initial LLR update by increasing the number of iterative signal detections and decreasing the number of coded bits that the receiver detects in one iterative signal detection. Computer simulations show that our proposal achieves better error rate performance with fewer detection and decoding iterations than the conventional approach.

We propose an implementation of the tapped delay line adaptive array (TDLAA) at the base station for improving the BER performance of asynchronous multi-user mobile communication over fast fading channels using multiple antennas. The data of each user at the mobile station, which applies two transmit antennas, are encoded by Space Time Block Code (STBC). The proposed scheme transmits the pilot signal and information data in alternate time slots. We derive performance criteria for designing such a scheme under the assumption that the fading is classified as fast fading. We show that the proposed scheme can suppress co-channel interference (CCI) and defeat Doppler spread effectively.

This paper proposes the Multimedia Pre-allocation WDMA (MP-WDMA) media access control (MAC) protocol to provide an efficient packet transfer service for metro-wavelength division multiple access (WDMA) networks. MP-WDMA considers three traffic types: constant bit rate (CBR), variable bit rate 1 (VBR1), and VBR2 traffic for a multimedia service as categorized in Multimedia WDMA (M-WDMA) MAC protocol. MP-WDMA is based on pre-allocation WDMA (P-WDMA), but the three traffic types are simultaneously allocated at one time slot, and one of them is selected through low bandwidth control signaling. Namely, a station assigns appropriate priority to input traffic, based on proposed traffic priority rules in MP-WDMA in order to determine the type of traffic. Accordingly, MP-WDMA can reduce station complexity as well as the possibility of idle time slot occurrences, compared with M-WDMA. Additionally, we analytically investigate the channel utilization and channel access delay of MP-WDMA and compare them with those of M-WDMA to find a proper MAC protocol for the networks. As a result, MP-WDMA supports maximally 30% higher channel utilization than M-WDMA regardless of channel and traffic conditions. Furthermore, MP-WDMA reduces the channel access delay of the delay-sensitive VBR2 traffic at the cost of increasing the channel access delay of the delay-insensitive VBR1 traffic. In this regard, MP-WDMA is suitable for the networks in terms of station complexity, channel utilization, and the channel access delay for VBR2 traffic.

For the construction of photonic crystal fiber (PCF) systems using their unique properties, a PCF coupler (PCFC) is one of the key components of the systems. The characteristics of the PCFC depend on the state of air holes in the tapered region of the PCFC because the state of air holes in the tapered region affects light propagation in the PCFC taper. In this paper, coupling characteristics of PCFCs were theoretically investigated. In PCFCs with air hole remaining tapers, we found that a smaller elongation ratio i.e. a stronger elongation is required to obtain optical coupling as an air hole pitch or a ratio of air hole diameter to pitch is larger. In PCFCs with air hole collapsed tapers, it was clarified that a dependence of extinction ratio on air hole collapsed elongation ratio is higher for smaller elongation ratio. It was also clarified that an air hole remaining PCFC has slow wavelength characteristics in extinction ratio compared to an air hole collapsed PCFC. Air hole remaining PCFCs and air hole collapsed PCFCs were fabricated using a CO2 laser irradiation technique. We could successfully control whether air holes in the PCFC taper were remaining or collapsed by adjusting the irradiated laser power in the elongation process of the PCFC fabrication. It was experimentally clarified that the air hole remaining PCFC has slow wavelength characteristics in extinction ratio compared to the air hole collapsed PCFC. The tendencies of the measured wavelength characteristics of PCFCs agree with those of numerical results.

This paper presents a watermarking method for the copyright protection and the prevention of illegal copying of mobile 3D contents. The proposed method embeds the copyright information and user's phone number into the spatial and encryption domains of the mobile animation data using the Buyer-Seller watermarking protocol. In addition, a user operation key is also inserted, so only the authorized user can play the 3D animation game on the mobile device. The proposed method was implemented using a mobile animation tool, and experimental results verified that the proposed method was capable of copyright protection and preventing illegal copying, as the watermarks were also accurately extracted in the case of geometrical attacks, such as noise addition, data accuracy variation, and data up/down scaling.

This paper presents a triple-band WCDMA direct conversion receiver (DCR) IC that needs a small number of off-chip components and control signals from digital baseband (DBB) IC. The DCR IC consists of 3 quadrature demodulators (QDEMs) with on-chip impedance matching circuit and an analog baseband block (ABB) that contains a low-pass filter (LPF) with fc automatic tuning circuit using no off-chip components and a linear-in-dB variable-gain amplifier (VGA) with on-chip analog high-pass filter (HPF). In order to make use of DBB control-free DC offset canceler, the DCR is designed to avoid large gain change under large interference that causes long transient response. In order to realize that characteristic without increasing quiescent current, the QDEM is used that employs class AB input stage and low-noise common mode feedback (CMFB) output stage. The DCR IC was fabricated in a SiGe BiCMOS process and occupies about 2.9 mm3.0 mm. The DCR needs SAW filters only for off-chip components and a gain control signal from DBB IC for AGC loop. The IIP3 of over -4.4 dBm for small signal input level and that of over +1.9 dBm for large signal input level are achieved. The gain compression of the desired signal is less than 0.3 dB for ACS Case-II condition.

We propose a new robust frequency domain acoustic echo cancellation filter that employs a normalized residual echo enhancement. By interpreting the conventional robust step-size control approaches as a statistical-model-based residual echo enhancement problem, the optimal step-size introduced in the most of conventional approaches is regarded as optimal only on the assumption that both the residual echo and the outlier in the error output signal are described by Gaussian distributions. However, the Gaussian-Gaussian mixture assumption does not always hold well, especially when both the residual echo and the outlier are speech signals (known as a double-talk situation). The proposed filtering scheme is based on the Gaussian-Laplacian mixture assumption for the signals normalized by the reference input signal amplitude. By comparing the performances of the proposed and conventional approaches through the simulations, we show that the Gaussian-Laplacian mixture assumption for the normalized signals can provide a better control scheme for the acoustic echo cancellation.

This paper presents a new quarter-wavelength microstrip coupler compensated with a periodic sequence of floating metallic strips in the slots on the inner edges. After describing the characteristics of the coupled-line, as an example, a 15-dB coupler is designed and a high directivity of 30 dB or more in theory is obtained over a full band of a single-section coupler. Next, couplers with various coupling factors are designed, and the usefulness for very loose coupling is demonstrated. Furthermore, a three-section coupler is designed to show the effectiveness in a wide frequency range. The validity of the design concept and procedure is confirmed by electromagnetic simulations and experiments.

A power-aware compiler controllable chip multiprocessor (CMP) is presented and its performance and power consumption are evaluated with the optimally scheduled advanced multiprocessor (OSCAR) parallelizing compiler. The CMP is equipped with power control registers that change clock frequency and power supply voltage to functional units including processor cores, memories, and an interconnection network. The OSCAR compiler carries out coarse-grain task parallelization of programs and reduces power consumption using architectural power control support and the compiler's power saving scheme. The performance evaluation shows that MPEG-2 encoding on the proposed CMP with four CPUs results in 82.6% power reduction in real-time execution mode with a deadline constraint on its sequential execution time. Furthermore, MP3 encoding on a heterogeneous CMP with four CPUs and four accelerators results in 53.9% power reduction at 21.1-fold speed-up in performance against its sequential execution in the fastest execution mode.

Bubble-sort graphs are variants of Cayley graphs. A bubble-sort graph is suitable as a topology for massively parallel systems because of its simple and regular structure. Therefore, in this study, we focus on n-bubble-sort graphs and propose an algorithm to obtain n-1 disjoint paths between two arbitrary nodes in time bounded by a polynomial in n, the degree of the graph plus one. We estimate the time complexity of the algorithm and the sum of the path lengths after proving the correctness of the algorithm. In addition, we report the results of computer experiments evaluating the average performance of the algorithm.

Two simple but useful methods, called the deep learning methods, for making multilayer neural networks tolerant to multiple link-weight and neuron-output faults, are proposed. The methods make the output errors in learning phase smaller than those in practical use. The abilities of fault-tolerance of the multilayer neural networks in practical use, are analyzed in the relationship between the output errors in learning phase and in practical use. The analytical result shows that the multilayer neural networks have complete (100%) fault-tolerance to multiple weight-and-neuron faults in practical use. The simulation results concerning the rate of successful learnings, the ability of fault-tolerance, and the learning time, are also shown.

The scheduling of real-time tasks with fault-tolerant requirements has been an important problem in multiprocessor systems. The primary-backup (PB) approach is often used as a fault-tolerant technique to guarantee the deadlines of tasks despite the presence of faults. In this paper we propose a dynamic PB-based task scheduling approach, wherein an allocation parameter is used to search the available time slots for a newly arriving task, and the previously scheduled tasks can be re-scheduled when there is no available time slot for the newly arriving task. In order to improve the schedulability we also propose an overloading strategy for PB-overloading and Backup-backup (BB) overloading. Our proposed task scheduling algorithm is compared with some existing scheduling algorithms in the literature through simulation studies. The results have shown that the task rejection ratio of our real-time task scheduling algorithm is almost 50% lower than the compared algorithms.

We propose a fast decoding algorithm for the p-ary first-order Reed-Muller code guaranteeing correction of up to errors and having complexity proportional to nlog n, where n = pm is the code length and p is an odd prime. This algorithm is an extension in the complex domain of the fast Hadamard transform decoding algorithm applicable to the binary case.