New interference cancellation technique using time division reference signal is proposed for optical synchronous code-division multiple-access (CDMA) systems with modified prime sequence codes. In the proposed system one user in each group is not allowed to access the network at each time, and this unallowable user's channel is used as a reference signal for other users in the same group at the time. The performance of the proposed system using an avalanche photodiode (APD) is analyzed where the Gaussian approximation of the APD output is employed and the effects of APD noise, thermal noise, and interference for the receiver are included. The proposed cancellation techniqus is shown to be effective to improve the bit error probability performance and to alleviate the error floor when the number of users and the received optical power are not appreciably small.

In this paper, the bit error rate (BER) considering tracking performance is evaluated, by theoretical analysis and computer simulation, for a bi-orthogonal system using a synchronizing pseudo-noise (PN) sequence and co-channel interference cancellers. A system that improves on Tachikawa's system is proposed. It is found that the optimum ratio of the information signal energy to the synchronizing signal energy varies with Eb/No, and the canceller is better for small L than for large L (L = length of the sequence). Moreover, it is found that the BER considering synchronization performance improvse as the equivalent noise bandwidth Bn decreases.

A generalized Reed-Muller expression (GRM) is obtained by negating some of the literals in a positive polarity Reed-Muller expression (PPRM). There are at most 2(n2)^(n-1) different GRMs for an n-variable function. A minimum GRM is one with the fewest products. This paper presents certain properties and an exact minimization algorithm for GRMs. The minimization algorithm uses binary decision diagrams. Up to five variables, all the representative functions of NP-equivalence classes were generated and minimized. Tables compare the number of products necessary to represent four-and five-variable functions for four classes of expressions: PPRMs, FPRMs, GRMs and SOPs. GRMs require, on the average, fewer products than sum-of-products expressions (SOPs), and have easily testable realizations.

When wireless multi-media information which includes speech, image, data and so on are transmitted, the defference in information rate, required quality as well as traffic performance should be taken into account. A wireless spread spectrum system can achieve a flexible balance of these differences because of the inherent asynchronous capability of CDMA. In this paper, we propose a wireless multi-media CDMA system based on a processing gain control in a dynamic traffic channel. According to the priority of each medium and channel measurement information i.e. traffic, the optimal processing gain can be controlled by using Nonlinear Programming. Numerical results demonstrate that the proposed method possesses higher flexible capacity than TDMA in a dynamic multi-medea traffic channel.

This paper proposes a novel Doppler frequency shift compensation technique to achieve terrestrial and low earth orbit (LEO) satellite dual mode DS/CDMA terminals robust to high Doppler shift and multipath fading. In order to satisfy the requirements of wide dynamic range and high accuracy simultaneously, the proposed scheme employs two stage compensation scheme, i.e., coarse compensation to keep dynamic range of about 100 kHz and fine compensation to satisfy its resolution of about 30 Hz, using block demodulation technique. Computer simulation results show that the proposed scheme can sufficiently compensate for the offset frequency up to the range of about 100 kHz at the terrestrial and LEO satellite combined mobile communication systems.

We develop a new class of stochastic Petri net: non-regenerative stochastic Petri net (NRSPN), which allows the firing time of its transitions with arbitrary distributions, and can automatically generate a bounded reachability graph that is equivalent to a generalization of the Markov renewal process in which some of the states may not constitute regeneration points. Thus, it can model and analyze behavior of a system whose states include some non-regeneration points. We show how to model a system by the NRSPN, and how to obtain numerical solutions for the NRSPN model. The probabilistic behavior of the modeled system can be clarified with the reliability measures such as the steady-state probability, the expected numbers of visits to each state per unit time, availability, unavailability and mean time between system failure. Finally, to demonstrate the modeling ability and analysis power of the NRSPN model, we present an example for a fault-tolerant system using the NRSPN and give numerical results for specific distributions.

A graph G is called an n-channel graph at vertex r if there are n independent spanning trees rooted at r. A graph G is called an n-channel graph if G is an n-channel graph at every vertex. Independent spanning trees of a graph play an important role in fault-tolerant broadcasting in the graph. In this paper we show that if G1 is an n1-channel graph and G2 is an n2-channel graph, then G1G2 is an (n1 + n2)-channel graph. We prove this fact by a construction of n1+n2 independent spanning trees of G1G2 from n1 independent spanning trees of G1 and n2 independent spanning trees of G2. As an application we describe a fault-tolerant broadcasting scheme along independent spanning trees.

It is well known that extracting parallel loops plays a significant role in designing parallelizing compilers. The execution efficiency of a loop is enhanced when the loop can be executed in parallel or partial parallel, like a DOALL or DOACROSS loop. This paper reports on the practical parallelism detector (PPD) that is implemented in PFPC (a portable FORTRAN parallelizing compiler running on OSF/1) at NCTU to concentrate on finding the parallelism available in loops. The PPD can extract the potential DOALL and DOACROSS loops in a program by invoking a combination of the ZIV test and the I test for verifying array subscripts. Furthermore, if DOACROSS loops are available, an optimization of synchronization statement is made. Experimental results show that PPD is more reliable and accurate than previous approaches.

Entire systems on a chip (SOCs) embodying a processor, memory, and system-specific peripheral hardware are now an everyday reality. The current generation of SOC designers are driven more than ever by the need to lower chip cost, while at the same time being faced with demands to get designs to market more quickly. It was to support this new community of designers that we developed Satsuki-an integrated processor synthesis and compiler generation system. By allowing the designer to tune the processor design to the bitwidth and performance required by the application, minimum cost designs are achieved. Using synthesis to implement the processor in the same technology as the rest of the chip, allows for global chip optimization from the perspective of the system as a whole and assures design portability. The integral compiler generator, driven by the same parameters used for processor synthesis, promotes high-level expression of application algorithms while at the same time isolating the application software from the processor implementation. Synthesis experiments incorporating a 0.8 micron CMOS gate array have produced designs ranging from a 45 MHz, 1,500 gate, 8-bit processor with a 4-word register file to a 31 MHz, 9,800 gate, 32-bit processor with a 16-word register file.

This paper describes a narrow pass-band optical filter utilizing a wavelength-sensitive power-transfer characteristic in the directional coupler composed of the K-and Ag-ion exchange waveguides which have greatly different dispersion relations caused by the large mismatch in the index profile of the waveguide cross-section. A narrow pass-band width of about 7 nm is measured in the filter fabricated in the soda-lime glass substrate. The fabrication technique with two-step ion-exchange of the K-and Ag-ions, is also presented together with a quick design method.

In this paper, scattering problem of the grating coupler is analyzed by the mode-matching method in the sense of least squares for the gaussian light beam incidence. This coupler has a periodic groove structure of finite extent, which is formed on the surface of the core layer of the symmetric thin-film waveguide. In the present method, the approximate scattered fields of each region of the grating coupler are described by the superpositions of the plane waves with band-limited spectra, respectively. These approximate wave functions are determined by the minimization of the mean-square boundary residual. This method results in the simultaneous Fredholm type integral equations of the second kind for these spectra. The first and second order approximate solutions of the integral equations are derived analytically and the coupling efficiency and scattered fields are analyzed on the basis of those solutions. A qualitative and physical consideration for the scattering problem of the grating coupler is presented with the fundamental data derived from approximate solutions in this paper.

Synthesis tools are now extensively used in the VLSI circuit design process. They allow a much higher design productivity, but the designer often does not directly control the circuit structure. Thus, when circuits are dedicated to dependable applications, designers have difficulties in implementing manually the devices needed to obtain fault detection or tolerance capabilities. The ASYL-SdF System has been developed over the last few years in order to avoid this break in the design flow, and to facilitate the designer's work when dependability is targeted. This paper gives an overview of the resulting tool, its synthesis flow for fault detection and fault tolerance in Finite State Machines, its limitations and the current developments. Actual circuit implementation results are given in terms of area overheads, expected reliability and experimental fault detection coverage.

Abstract machine modelling is a technique used frequently in developing the retargetable compilers. By translating the abstract machine operations into target machine instructions, we can construct retargetable compilers. However, such a technique will cause two problems. First, the code produced by the compilers is inefficient. Next, in order to emit the efficient code, the compilation time is too long. In view of these two disadvantages, we apply PO (peephole optimizer) in our retargetable compilers to do code optimization. Peephole optimizer searches for the adjacent instruction candidates in the intermediate code, and then replaces them with equivalent instructions of less cost. Furthermore, the peephole description table consists of simple tree-rewriting rules which are easily retargeted into different machines. At the same time, we have proposed a simple peephole pattern matching algorithm to reduce the peephole pattern matching time. The experiment indicates that the machine code generated by our compiler runs faster than that by GNU c compiler (gcc).

The importance sampling simulation technique has been exploited to obtain an accurate estimate for a very small probability which is not tractable by the ordinary Monte Carlo simulation. In this paper, we will investigate the simulation for a sample average of an output sequence from a Markov chain. The optimal simulation distribution will be characterized by the Kullback-Leibler divergence of Markov chains and geometric properties of the importance sampling simulation will be presented. As a result, an effective computation method for the optimal simulation distribution will be obtained.

A pilot symbol-assisted coherent multistage interference canceller (PSA-COMSIC) using recursive channel estimation is proposed for DS-CDMA mobile radio cellular systems. In the proposed scheme, since the channel variation due to fading is recursively estimated at each interference canceling stage, the accuracy of channel estimation is successively improved. The bit error rate (BER) performances against average Eb/N0 (signal energy per bit-to-noise power spectral density ratio) and capacity in the isolated cell are investigated by computer simulations. The simulations demonstrate that the capacity using the PSA-COMSIC with recursive channel estimation is about 1.6 times higher than that of the conventional matched filter receiver with channel coding and bit-interleaving in the interference-limited environments.

Multistage Interconnection Networks (MIN) with multiple outlets are networks which can support higher bandwidth than those of nonblocking networks by passing multiple packets to the same destination. Fault recovery mechanisms are proposed for two of such networks (TBSF/PBSF) with the best use of their inherent fault tolerant capability. With these mechanisms, on-the-fly fault recovery is possible for multiple faults on switching elements. For the link fault, the networks are reconfigured after fault diagnosis, and the network is available with some performance degradation. The bandwidth degradation under multiple faults on link/element is analyzed with both theoretical models and simulation. Through the analysis, F-PBSF shows high fault tolerance under high traffic load and low reliability by using 3 or more banyan networks.

Motivated by the design of fault-tolerant multiprocessor interconnection networks, this paper considers the following problem: Given a positive integer t and a graph H, construct a graph G from H by adding a minimum number Δ(t, H) of edges such that even after deleting any t edges from G the remaining graph contains H as a subgraph. We estimate Δ(t, H) for the hypercube and torus, which are well-known as important interconnection networks for multiprocessor systems. If we denote the hypercube and the square torus on N vertices by QN and DN respectively, we show, among others, that Δ(t, QN) = O(tN log(log N/t + log 2e)) for any t and N (t 2), and Δ(1, DN) = N/2 for N even.

In this paper, we study the following node-to-node and node-to-set routing problems in r-dimensional torus Trn with r 2 and n 4 nodes in each dimension: given at most 2r - 1 faulty nodes and non-faulty nodes s and t in Trn, find a fault-free path s t; and given at most 2r - k faulty nodes and non-faulty nodes s and t1,..., tk in Trn, find k fault-free node-disjoint paths s ti, 1 i k. We give an O(r2) time algorithm which finds a fault-free path s t of length at most d(Trn) + 1 for the node-to-node routing, where d(Trn) is the diameter of Trn. For node-to-set routing, we show an O(r3) time algorithm which finds k fault-free node-disjoint paths s ti, 1 i k, of length at most d(Trn) + 1. The upper bounds on the length of the found paths are optimal. From this, Rabin diameter of Trn is d(Trn) + 1.

This paper proposes a new duplication redundancy technology, 2 Transistors for 1.5 Gates, that is capable of automatic defect tolerance, so making large, high-resolution, color TFT-LCD panel fabrication both easy and economical. This redundancy technology with automatic defect tolerant capability has a low hardware overhead and is very capable of compensating for open circuit defects in a large active-matrix panel. This technology was confirmed by fabricating a 9.5-inch color TFT-LCD panel with 640480 pixels(960960 dots). This panel showed excellent display performance and produced pictures without defects. The yield improvement effect of this technology was also confirmed by calculation based on the Boltzmann statistics model. Consequently, this technology is clearly seen to have a yield improvement effect equal to defect density reduction of about one order, compared to non redundancy. This technology drastically reduces dot and line defects, enabling fabrication of large, high-resolution, color TFT-LCD panels at a relatively low cost.

This paper proposes a fast timing recovery method with a decision feedback equalizer for baudrate sampling. The proposed method features two special techniques. The first one is for coarse estimation of the sampling phase. Internal signals of the oversampled analog-to-digital converter at different phases are directly taken out for parallel evaluation. The second technique provides fine tuning with a phase-modification stepsize which is adaptively controlled by the residual intersymbol interference. Simulation results by a full-duplex digital transmission system with a multilevel line code show superiority of the proposed method. The coarse timing estimation and the fine tuning reduce 75% and 40% of the time required by the conventional method,respectively. The overall saving in timing recovery is almost 60% over the conventional method. The proposed method could easily be extended to other applications with a decision feedback equalizer.