Multicasting is an important feature for any switching network being intended to support broadband integrated services digital networks (B-ISDN). This paper proposes an improved multicast packet switch based on Lee's nonblocking copy network. The improved design retains the desirable features of Lee's network including its nonblocking property while adopting techniques to overcome the various limitations mentioned in various literature. The proposed network architecture utilizes d-dilated banyan networks to increase the amount of cells that can be replicated within the copy network. Cell splitting is used to optimize the utilization of the network's available bandwidth. Furthermore, the proposed architecture allows for the modular expansion in capacity to accomodate changing traffic patterns. The modular design of the proposed switch likewise offers easy handling and replacement of faulty modules.

In this paper, a dynamic constructive algorithm for fault tolerant feedforward neural network, called DCFTA, is proposed. The algorithm starts with a network with single hidden neuron, and a new hidden unit is added dynamically to the network whenever it fails to converge. Before inserting the new hidden neuron into the network, only the weights connecting the new hidden neuron to the other neurons are trained (i. e. , updated) until there is no significant reduction of the output error. To generate a fault tolerant network, the relevance of each synaptic weight is estimated in each cycle, and only the weights which have their relevance less than a specified threshold are updated in that cycle. The loss of a connections between neurons (which are equivalent to stuck-at-0 faults) are assumed. The simulation results indicate that the network constructed by DCFTA has a significant fault tolerance ability.

This paper presents two types of two-dimensional (2-D) adaptive beamforming algorithm which have high rate of convergence. One is a linearly constrained minimum variance (LCMV) beamforming algorithm which minimizes the average output power of a beamformer, and the other is a generalized sidelobe canceler (GSC) algorithm which generalizes the notion of a linear constraint by using the multiple linear constraints. In both algorithms, we apply a 2-D lattice filter to an adaptive filtering since the 2-D lattice filter provides excellent properties compared to a transversal filter. In order to evaluate the validity of the algorithm, we perform computer simulations. The experimental results show that the algorithm can reject interference signals while maintaining the direction of desired signal, and can improve convergent performance.

Considering the pattern classification/recognition tasks, the influence of the activation function on fault tolerance property of feedforward neural networks is empirically investigated. The simulation results show that the activation function largely influences the fault tolerance and the generalization property of neural networks. It is found that, neural networks with symmetric sigmoid activation function are largely fault tolerant than the networks with asymmetric sigmoid function. However the close relation between the fault tolerance and the generalization property was not observed and the networks with asymmetric activation function slightly generalize better than the networks with the symmetric activation function. First, the influence of the activation function on fault tolerance property of neural networks is investigated on the XOR problem, then the results are generalized by evaluating the fault tolerance property of different NNs implementing different benchmark problems.

This paper presents a practical fault-tolerant architecture for mesh parallel machines that has t spare processors and has 2(t+2) communication links per processor while tolerating at most t+1 processor and link faults. We also show that the architecture presented here can be laid out efficiently in a linear area with wire length at most O(t).

In supervisory control, discrete event dynamic systems (DEDSs) are modeled by finite-state automata, and their behaviors described by the associated formal languages; control is exercised by a supervisor, whose control action is to enable or disable the controllable events. In this paper we present a general stability concept for DEDSs, stability in the sense of Lyapunov with resiliency, by incorporating Lyapunov stability concepts with the concept of stability in the sense of error recovery. We also provide algorithms for verifying stability and obtaining a domain of attraction. Relations between the notion of stability and the notion of fault-tolerance are addressed.

In this paper, we study and analyze the overall acquisition performance of the combined acquisition-tracking synchronization loop for direct-sequence spread-spectrum (DS-SS) signals in the presence of Doppler shift. We consider both the change of effective search rate and the impact on the detection probability due to Doppler for the acquisition loop. We also determine the acquisition behavior of the digital delay lock loop (DDLL) in the presence of code Doppler. As a result, the influence of the DDLL's acquiring capability on the complete acquisition process is investigated and some numerical results are presented to demonstrate the acquisition performances of this combined loop which are quite different from the previous reports.

A switched-capacitor Wien bridge oscillator and its automatic gain controller are discussed for low-frequency generation. The dc voltage Vs related to the amplitude of oscillation is obtained from the voltage differences in the frequency-determining arm. Theoretical analysis of the ripples in Vs is reported.

Many digital signal processors (DSPs) employ indirect addressing using address registers (ARs) to indicate their memory addresses, which often leads to overhead. This paper presents methods to efficiently allocate addresses for variables in a given program so that overhead in AR update operations is reduced. Memory addressing model is generalized in such a way that AR can be updated at the codes without memory accesses. An efficient memory address allocation is obtained by a method based on the graph linearization algorithm, which takes account of the number of possible AR update operations for every memory access. In order to utilize multiple ARs, methods to assign variables into ARs are also investigated. The proposed methods are applied to the compiler for µPD77230 (NEC) and generated codes for several examples prove effectiveness of these methods.

This paper propeses advanced multi-stage interference canceller systems (MSICS) wihch can estimate radio channels with precision in the direct sequence code division multiple access (DS-CDMA) systems. For the accurate channel estimations, we propose a novel radio channel estimation method specified by the following two signal processing methods. One is the radio channel estimation using both pilot and information signals. The other is the correction of estimated radio channels using adaptation algorithm based on the least mean square method (LMS). The results of our computer simulation indicate that the cell capacity of the advanced MSICS in serial and parallel structure can be increased by about 1.8 and 1.3 times over that of a receiver which does not has a canceller, respectively. Moreover, the advanced MSICS in serial and parallel structure can reduce the required Eb/No by about 1.2 dB and 1.6 dB at a BER of 10-3 compared to the Eb/No of a basic MSICS, respectively.

The bit error rate (BER) performance against average Eb/No (signal energy per bit-to-noise power spectral density ratio) and the capacity of the pilot symbol-assisted coherent orthogonal filter (PSA-COF) based Rake receiver with fast transmit power control (TPC) are evaluated in DS-CDMA reverse link under multipath Rayleigh fading. Fast TPC, which controls all signals transmitted from users in the same cell or sector such that they are received with equal power at the cell site under fast Rayleigh fading, is essential for the PSA-COF based Rake receiver in the reverse link in order to improve the performance degradation experienced when the received signal level drops due to fading as the transmit power is limited in practical systems. Signal-to interference plus noise power ratio (SINR) based fast transmit power control (TPC) is assumed here. By using the fast TPC in reverse link and applying the PSA-COF based Rake receiver to base station (BS), the transmit power of each mobile station (MS) can be significantly reduced, thus increasing link capacity. It is demonstrated that the capacity of the PSA-COF based Rake receiver is about 1.5 times higher than that of the conventional matched filter (MF) receiver in interference-limited channels.

We analyze performance of direct-detection optical synchronous code-division multiple-access (CDMA) system with co-channel interference canceller using Gaussian approximation of avalanche photodiode (APD) output. Our results show that the derived probability of error floor is equal to that under the number-state light field model.

Investigated is a guided-wave device for dividing optical power into three equal parts. The device fundamentally consists of a three-waveguide tapered-velocity coupler which is designed to operate under the adiabatic condition. Field distributions of the local normal modes along the coupler explain basic principles of the device. Its performance is confirmed through numerical simulations by means of finite difference beam propagation method.

In this paper, scattering problem of the directional coupler for the slab waveguides are analyzed by the mode-matching method in the sense of least squares for the lowest order even TE mode incidence. It is considered that the analysis of this coupler for the slab waveguides presents the fundamental data to design the directional coupler for the three dimensional waveguides. This directional coupler is composed of three parallel slabs which are placed at equal space in the dielectric medium. Respective slabs are core regions of three respective waveguides. The periodic groove structure of finite extent is formed on the both surfaces of core region of the central waveguide among them. The power of incident TE mode is coupled to other two waveguides through periodic groove structure. The coupled TE mode propagates in the other waveguides to the same or opposite direction for the direction of incident mode which propagates in the waveguide having periodic structure when the Bragg condition is selected appropriately. The scattered field of each region of this directional coupler is described by the superpositions of the plane waves with bandlimited spectra, respectively. These approximate wave functions are determined by the minimization of the mean-square boundary residual. This method results in the simultaneous Fredholm type integral equations of the second kind for these spectra. The first order approximate solutions of the integral equations are derived and the coupling efficiency and scattered fields are analyzed on the basis of those solutions in this paper.

This is a review of our high-Tc superconductor (HTS) sampler development. The design and experimental demonstration of a Josephson sampler circuit based on YBa2 Cu3Ox(YBCO)/PrBa2Cu3Ox/YBCO ramp-edge junctions is described. The sampler circuit contains five edge junctions with a stacked YBCO groundplane and is based on single-flux quantum (SFQ) operations. Computer simulation results show that the time resolution of the sampler circuit depends strongly on the IcRn product of the junction and can be reduced to a few picoseconds with realistic parameter values. The edge junctions were fabricated using an in-situ process in which a barrier and a counter-electrode layer are deposited immediately after the edge etching without breaking the vacuum. The in-situ process improved the critical current uniformity of the junctions to 1σ20% in twelve 4-µm-width junctions. An YBCO groundplane was placed on the junctions in a multilayer structure we call the HUG (HTS cricuit with an upper-layer groundplane) structure. The inductance of YBCO lines was reduced to 1 pH per square without junction-quality degradation in the HUG structure. SFQ current-pulse generation, SFQ storage, and SFQ readout in the circuit have been confirmed by function tests using 3-kHz pulse currents. The successful operation of the sampler circuit has been demonstrated by measuring a signal-current waveform at 50K.

This paper describes technological and operational issues of an image-art-on-demand system, which provides visitors with high-definition images of fine art in a virtual gallery. The system is presented as a typical example of multimedia information service systems on IP over ATM network. The high-definition images of fine arts from a database are interactively selected in a virtual gallery which is generated by an advanced computer graphics (CG) workstation. The generated images of the virtual gallery are transmitted by MPEG-2 over TCP/IP on ATM at 30 frames per second. This system was opened from January 1996 to March 1997 as one project of NTT's joint utilization tests of multimedia communications. As far as we know, this system is the first real-time image-art-on-demand system using MPEG-2 on IP over ATM-WAN to be exhibited to the general public.

We present a novel replication technique for parallel applications where instances of the replicated application are active on different group of processors called replicas. The replication technique is based on the FTAG (Fault Tolerant Attribute Grammar) computation model. FTAG is a functional and attribute based model. The developed replication technique implements "active parallel replication," that is, all replicas are active and compute concurrently a different piece of the application parallel code. In our model replicas cooperate not only to detect and mask failures but also to perform parallel computation. The replication mechanisms are supported by FTAG run time system and are fully application-transparent. Different novel mechanisms for checkpointing and recovery are developed. In our model during rollback recovery only that part of the computation that was detected faulty is discarded. The replication technique takes full advantage of parallel computing to reduce overall computation time.

This work is targeted to understand the operating principle of the feedback type echo canceller for use in an FM broadcasting receiver and to study its compensating features and the effects of the practical operating environment on its performance. The effects of the tap interval and the compensation performance in the presence of an echo with excess delay 0 - 15 µs are examined. The results show that the tap interval should be selected according to the observable bandwidth of the channel transfer function and the performance of a feedback type echo canceller has a wavelike curve with respect to the excess delay of the echo. To improve the performance of the feedback type echo canceller, an adaptive echo canceller operating with CM algorithm is proposed and examined with computer simulation. The results show that the compensation performance is improved.

The construction of fault-tolerant processor arrays with interconnections of cube-connected cycles (CCCs) by using an advanced spare-connection scheme for k-out-of-n redundancies called "generalized additional bypass linking" is described. The connection scheme uses bypass links with wired OR connections to spare processing elements (PEs) without external switches, and can reconfigure complete arrays by tolerating faulty portions in these PEs and links. The spare connections are designed as a node-coloring problem of a CCC graph with a minimum distance of 3: the chromatic numbers corresponding to the number of spare PE connections were evaluated theoretically. The proposed scheme can be used for constructing various k-out-of-n configurations capable of quick broadcasting by using spare circuits, and is superior to conventional schemes in terms of extra PE connections and reconfiguration control. In particular, it allows construction of optimal r-fault-tolerant configurations that provide r spare PEs and r extra connections per PE for CCCs with 4x PEs (x: integer) in each cycle.

The authors previously proposed a reconfigurable architecture called the "XL-scheme" in order to cope with processor element (PE) faults as well as link faults. However, they described an algorithm for compensating only for link faults. They determined the potential ability to tolerate faults of the XL-scheme for simultaneous faults of links and PEs, and left a reconstruction algorithm for simultaneous PE and link faults to be studied in the future. This paper briefly explains the XL-scheme and gives a reconstruction algorithm for simultaneous PE and link faults. The algorithm first replaces faulty PEs with healthy ones and then replaces faulty links with healthy ones. We then compute the reliabilities of the mesh-arrays with simultaneous PE and link faults by simulation. We compare the reliability of the XL-scheme with that of the one-and-half track switch model. It is seen that the former is much larger than the latter. Furthermore, we show the result for processing time.