A novel K-band MMIC frequency doubler has been developed using resistive series feedback circuit. The doubler exhibits much better D/U ratio, smaller output power variation against ambient temperature and lower power consumption than those of the conventional single-ended doubler. This paper presents the simulation results on the effect of the resistive series feedback by harmonic balance methods. To obtain practical and accurate simulation results, newly developed gate charge model for Cgs and Cgd is introduced. The fabricated result of the proposed MMIC is also demonstrated.

Designing a protocol to exchange a secret key is one of the most fundamental subjects in cryptography. Using a random deal of cards, pairs of card players (agents) can share secret keys that are information-theoretically secure against an eavesdropper. A key set protocol, which uses a random deal of cards, can perform an Eulerian secret key exchange, in which the pairs of players sharing secret keys form an Eulerian circuit passing through all players. Along the Eulerian circuit any designated player can send a message to the rest of players and the message can be finally sent back to the sender. Checking the returned message with the original one, the sender can know whether the message circulation has not been influenced by a possible single transmission error or false alteration. It has been known that any Eulerian circuit formed by the protocol has length at most 3/2k, where k is the number of players. Note that the length corresponds to the time required to send the message to all players and acknowledge the secure receipt. In this paper, we show that the average length of Eulerian circuits is approximately k+ln k.

In this paper, we present a new approach for the design of partially adaptive broadband beamformers with the generalized sidelobe canceller (GSC) as an underlying structure. The approach designs the blocking matrix involved by utilizing a set of P-regular, M-band wavelet filters, whose vanishing moment property is shown to meet the requirement of a blocking matrix in the GSC structure. Furthermore, basing on the subband decomposition property of these wavelet filters, we introduce a new dynamic subband selection scheme succeeding the blocking matrix. The scheme only retains the principal subband components of the blocking matrix outputs based on a prescribed statistical hypothesis test and thus further reduces the dimension of weights in adaptive processing. As such, the overall computational complexity, which is mainly dictated by the dimension of adaptive weights, is substantially reduced. The furnished simulations show that this new approach offers comparable performance as the existing fully adaptive beamformers but with reduced computations.

Distributed computation has attracted considerable attention and large-scale distributed systems have been designed and developed. A distributed system inherently has possibility of fault tolerance because of its redundancy. Thus, a great deal of investigation has been made to design fault-tolerant distributed algorithms. This paper introduces two promising paradigms, self-stabilization and wait-freedom, for designing fault-tolerant distributed algorithms and discusses some subjects important from the point of view of algorithm engineering.

In the phase locked loop (PLL) frequency synthesizer which is used in a higher frequency region, the prescaler method is employed in order to increase the operating frequency of the programmable divider. However, since the fixed divider whose division ratio is same as the prescaler is installed at the following stage of the reference divider, the reference frequency is decreased and the performance of the PLL frequency synthesizer is degraded. The prescaler PLL frequency synthesizer using multi-programmable divider is one of the counter measures answering the request. In this paper we propose the reduction of the number of programmable dividers by using the (N+1/2) programmable divider. The effectiveness of the proposed method is confirmed by experimental results.

An epoxy-modified urethane rubber mixed with carbon particles is now chosen as the millimeter-wave absorber material in our study. The absorption characteristics of the absorber is measured under temperature changes. The weatherability of our absorber is also clarified based on absorption characteristics, thickness and hardness of the sample. As a result of the temperature characteristics of the absorber, the difference of the maximum absorption frequency under temperature changes is about 1 GHz, however the absorption of 20 dB or more is obtained between 54 and 58 GHz. The result of accelerated artificial exposure test is that 2.8% of the thickness of our sample is shrunk after 1000 hour exposure, and the hardness of rubber is hardened with increasing test time. It is also confirmed that the deterioration of the absorption ranges from 1 to 3 dB, although the absorption of about 20 dB is kept at the frequency range. As a consequence, it is confirmed that the wave absorber using the epoxy-modified urethane rubber mixed with carbon particles has good weatherability including our desired temperature characteristics, and it is suitable for outdoor use.

The rapid growth of the Internet impacts ATM networks to be furnished IP handling capability. This paper discusses networking issues for IP and ATM integration. First, it considers function allocation at the boundary of an ATM backbone network and the Internet. As the result, the paper explains the necessity of built-in IP handling capability into an ATM switching system, and summarizes functional requirements for the system architecture. According to the discussion above, the authors propose the system architecture of the IP/ATM integration in the ATM switching system. The implementation of the proposed architecture is evaluated, and the wire-speed IP handling capability in the ATM switch is confirmed.

The operation of a novel all-optical wavelength converter based on directionally-coupled semiconductor optical amplifiers is described. Merits such as extinction enhancement and digital response are expected through a simple analytical model and a sophisticated transfer matrix method developed to take into account the spatial distributions of the optical power, carrier density, refractive index, propagation constant, and coupling coefficient along device. We fabricated devices operating at 1.55 µm band using an InGaAsP/InP material system and demonstrated successfully the static characteristics of wavelength conversion with the expected advantages. Devices are as small as 1.5 mm and do not need any active/passive integration step during fabrication.

Two different examples have been respectively given by Aggarwal and Viswanathan to establish the necessity of (n + 2)/5 edge guards for spiral polygons. However, the former example is incorrect. To show why it is wrong, we give an alternate proof of sufficiency of (n + 2)/5 edge guards for spiral polygons. Our proof is simpler than the sufficiency proof given by Viswanathan.

This paper addresses output regulation for nonlinear systems driven by a time varying parameter. The derivative information of the time varying parameter is necessary for the improved regulation performance but it is not readily available in general. In this paper, we propose a velocity estimation of the time varying parameter for use in the control law without amplifying noise signals.

In this paper, we show two process allocation schemes to tolerate multiple faults when the primary-backup replication method is used. The first scheme, called multiple backup scheme, is running multiple backup processes for each process to tolerate multiple faults. The second scheme, called regenerative backup scheme, is running only one backup process for each process, but re-generates backup processes for processes that do not have a backup process after a fault occurrence to keep the primary-backup process pair available. In both schemes, we propose heuristic process allocation methods for balancing loads in spite of the occurrence of faults. Then we evaluate and compare the performance of the proposed heuristic process allocation methods using simulation. Next, we analyze the reliability of two schemes based on their fault-tolerance capability. For the analysis of fault-tolerance capability, we find the degree of fault tolerance for each scheme. Then we find the reliability of each scheme using Markov chains. The comparison results of two schemes indicate that the regenerative single backup process allocation scheme is more suitable than the multiple backup allocation scheme.

We propose a model for fault tolerant 3D processor arrays using one-and-half track switches. Spare processors are laid on the two opposite surfaces of the 3D array. The fault compensation process is performed by shifting processors on a continuous straight line (called compensation path) from a faulty processor to a spare on the surfaces. It is not allowed that compensantion paths are in the near-miss relation each other. Then, switches with only 4 states are needed to preserve the 3D mesh topology after compensating for faults. We give an algorithm in a convenient form for reconfiguring by hardware the 3D mesh arrays with faults. The algorithm can reconfigure the 3D mesh arrays in polynomial time. By computer simulation, we show the survival rates and the reliabilities of arrays which express the efficiencies of reconfiguration according to the algorithm. The reliabilities are compared with those of the model using double tracks for which the near-miss relation among compensation paths is allowed, but whose hardware overhead is almost double of that of the proposed model using one-and-half track. Finally, we design a logical circuit for hardware realization of the algorithm. Using the circuit, we can construct such a built-in self-reconfigurable 3D mesh array that the reconfiguration is done very quickly without an aid of a host computer.

This paper introduces an acoustic echo canceller system materialized with a 16-bit fixed point processing type DSP (Analog Devices, ADSP-2181). This experimental system uses the tri-quantized-x individually normalized least mean square (INLMS) algorithm little degrading the convergence property under the fixed point processing. The experimental system also applies a small step gain to the algorithm to prevent the double-talk from increasing the estimation error. Such a small step gain naturally reduces the convergence speed. The experimental system compensates the reduction by applying the block length adjustment technique to the algorithm. This technique enables to ceaselessly update the coefficients of the adaptive filter even when the reference signal power is low. The experimental system thus keeps the echo return loss enhancement (ERLE) high against the double-talk.

As VLSI technology has developed, the interest in implementing an entire or significant part of a parallel computer system using wafer scale integration is growing. The major problem for the case is the possibility of drastically low yield and/or reliability of the system if there is no strategy for coping with such situations. Various strategies to restructure the faulty physical system into the fault-free target logical system are described in the literature [1]-[5]. In this paper, we propose an efficient approximate method which can reconstruct the 1 1/2 track-switch mesh arrays with faulty PEs using hardware as well as software. A logical circuit added to each PE and a network connecting the circuits are used to decide spare PEs which compensate for faulty PEs. The hardware compexity of each circuit is much less than that of a PE where the size of each additional circuit is independent of array sizes and constant. By using the exclusive hardware scheme, a built-in self-reconfigurable system without using a host computer is realizable and the time for reconfiguring arrays becomes very short. The simulation result of the performance of the method shows that the reconstructing efficiency of our algorithm is a little less than those of the exaustive and Shigei's ones [6] and [7], but much better than that of the neural one [3]. We also compare the time complexities of reconstructions by hardware as well as software, and the hardware complexity in terms of the number of gates in the logical circuit added to each PE among the other methods.

In this paper, system capacity of the reverse link of a wireless multimedia CDMA system with transmission power control is analysed for receivers with and without CCI cancellers. For N classes of users, system capacity is represented by a point in an N-dimensional space. It is shown that system capacity is improved considerably with CCI cancellers, that system capacity region is non-convex in general, and that its boundary is well approximated with a unique hyper plane when CCI cancellers are fully employed.

In the hardware synthesis methods with high level languages such as C language, optimization quality of the compilers has a great influence on the area and speed of the synthesized circuits. Among hardware-oriented optimization methods required in such compilers, minimization of the bit length of the data-paths is one of the most important issues. In this paper, we propose an estimation algorithm of the necessary bit length of variables for this aim. The algorithm analyzes the control/data-flow graph translated from C programs and decides the bit length of each variable. On several experiments, the bit length of variables can be reduced by half with respect to the declared length. This method is effective not only for reducing the circuit area but also for reducing the delay of the operation units such as adders.

A 32-bit motor-drive-specific microcontroller chip was newly designed, implemented using a 0.8 µm double-metal CMOS process, and its feasibility was successfully tested by applying the fabricated microcontroller chip to a real AC induction motor drive system. The microcontroller chip includes a single-precision floating-point unit, peripheral devices for motor drive, and a memory controller as well as the SPARC V7 CPU. The pipeline scheme and the two-step multiplication method were used in the multiplier of floating-point unit for the best area and speed trade-off, using the standard cell library available for the design. The chip size is 12.7 12.8 mm2, the number of transistors is around 562,000, and the power consumption is 1.69 W at the supply voltage of 5 V and the clock frequency of 30 MHz. Both a standard cell library and a full-custom layout were used in the implementation.

Using Hopfield-type neural network model, we present an algorithm for reconstructing 3D mesh processor arrays using single-track switches where spare processors are laid on the six surfaces of a 3D array and show its effectiveness in terms of reconstruction rate and computing time by computer simulation. Next, we show how the algorithm can be realized by a digital neural circuit. It consists of subcircuits for finding candidate compensation paths, deciding whether the neural system reaches a stable state and at the time the system energy is minimum, and subcircuits for neurons. The subcircuit for each neuron including the other subcircuits can only be made with 16 gates and two flip-flops. Since the state transitions are done in parallel, the circuit will be able to find a set of compensation paths for a fault pattern very quickly within a time less than 1 µs. Furthermore, the hardware implementation of the algorithm leads to making a self-reconfigurable system without the aid of a host computer.

In this paper, we consider the ring embedding problem in faulty star graphs. Our embedding is based on the path transition scheme and node borrow technique in the ring of 4-dimensional substars with evenly distributed faults. Let Sn be the n-dimensional star graph having n! nodes. We will show that a ring of length n! - 2f can be found in Sn when the number of faulty nodes f is at most n-3. In the worst case, the loss of 2f nodes in the size of fault-free ring is inevitable because the star graph is bipartite. In addition, this result is superior to the best previous result that constructs the ring of length n! - 4f under the same fault condition. Moreover, by extending this result into the star graph with both node and edge faults simultaneously, we can find the fault-free ring of length n! - 2 fn in Sn when it contains fn faulty nodes and fe faulty edges such that fn + fe n-3.

This paper proposes an adaptive noise canceller with low signal-distortion in the presence of crosstalk. The proposed noise canceller has two pairs of cross-coupled adaptive filters, each of which consists of the main filter and a sub filter. The signal-to-noise ratios (SNRs) of the primary and the reference signals are estimated by the sub filters. To reduce signal distortion at the output of the adaptive noise canceller, the step sizes for coefficient adaptation in the main filters are controlled according to the estimated SNRs. Computer simulation results show that the proposed noise canceller reduces signal distortion in the output signal by up to 15 dB compared to the conventional noise canceller.