We propose a compact magnetic tunnel junction (MTJ) model for circuit simulation by de-facto standard SPICE in this paper. It is implemented by Verilog-A language which makes it easy to simulate MTJs with other standard devices. Based on the switching probability, we smoothly connect the adiabatic precessional model and the thermal activation model by using an interpolation technique based on the cubic spline method. We can predict the switching time after a current is applied. Meanwhile, we use appropriate physical models to describe other MTJ characteristics. Simulation results validate that the model is consistent with experimental data and effective for MTJ/CMOS hybrid circuit simulation.

Reference current used in sense amplifiers is a crucial factor in a single-end read manner for emerging memories. Dummy cell average read scheme uses multiple pairs of dummy cells inside the array to generate an accurate reference current for data sensing. The previous research adopts current mirror sense amplifier (CMSA) which is compatible with the dummy cell average read scheme. However, clamped bit-line sense amplifier (CBLSA) has higher sensing speed and lower power consumption compared with CMSA. Therefore, applying CBLSA to dummy cell average read scheme is expected to enhance the performance. This paper reveals that direct combination of CBLSA and dummy cell average read scheme leads to sense margin degradation. In order to solve this problem, a new array design is proposed to make CBLSA compatible with dummy cell average read scheme. Current mirror structure is employed to prevent CBLSA from being short-circuited directly. The simulation result shows that the minimum sensible tunnel magnetoresistance ratio (TMRR) can be extended from 14.3% down to 1%. The access speed of the proposed sensing scheme is less than 2 ns when TMRR is 70% or larger, which is about twice higher than the previous research. And this circuit design just consumes half of the energy in one read cycle compared with the previous research. In the proposed array architecture, all the dummy cells can be always short-circuited in totally isolated area by low-resistance metal wiring instead of using controlling transistors. This structure is able to contribute to increasing the dummy cell averaging effect. Besides, the array-level simulation validates that the array design is accessible to every data cell. This design is generally applicable to any kinds of resistance-variable emerging memories including STT-MRAM.

We performed a time dependent percolation analysis of the degradation phenomena in ultra-thin CoFeB/MgO/CoFeB magnetic tunneling junctions. The objective was to understand the microscopic degradation physics of coherent tunneling and the thickness limitation of the MgO barrier. We propose two models: a trap assisted tunneling (TAL) model and a filamentary defect assisted leakage (FAL) model. The correlation between resistance drift behavior and barrier lifetime was then calculated and compared with real data based on these models. The relationship between the resistance drift behavior and barrier lifetime was found to be well explained by the TAL model, the random trap formation in the barrier and the percolation path formation which lead to barrier breakdown. Based on the TAL model, the measured TDDB Weibull slope (β) was smaller than the value estimated by the model. By removing the effect of some initial defects in the barrier, an ultra-thin MgO tunneling barrier in MTJ has the potential for a much better lifetime with a better Weibull slope even at 3ML thickness. This method is rather simple but useful to deeply understand the microscopic degradation physics in dielectric films under TDDB stress.

Several new memories are being studied as candidates of future DRAM that seems difficult to be scaled. However, the read signal in these new memories needs to be amplified in a single-end manner with reference signal supplied if they are aimed for being applied to the high-density main memory. This scheme, which is fortunately not necessary in DRAM's 1/2Vdd pre-charge sense amp, can become a serious bottleneck in the new memory development, because the device electrical parameters in these new memory cells are prone to large cell-to-cell variations without exception. Furthermore, the extent to which the parameter fluctuates in data “1” is generally not the same as in data “0”. In these situations, a new sensing scheme is proposed that can minimize the sensing error rate for high-density single-end emerging memories like STT-MRAM, ReRAM and PCRAM. The scheme is based on averaging multiple dummy cell pairs that are written “1” and “0” in a weighted manner according to the fluctuation unbalance between “1” and “0”. A detailed analysis shows that this scheme is effective in designing 128Mb 1T1MTJ STT-MRAM with the results that the required TMR ratio of an MTJ can be relaxed from 130% to 90% for the fluctuation of 6% sigma-to-average ratio of MTJ resistance in a 16 pair-dummy cell averaging case by using this technology when compared with the arithmetic averaging method.

This paper reports a 65nm 8Mb spin transfer torque magnetoresistance random access memory (STT-MRAM) operating at a single supply voltage with a process-variation-tolerant sense amplifier. The proposed sense amplifier comprises a boosted-gate nMOS and negative-resistance pMOSs as loads, which maximizes the readout margin at any process corner. The STT-MRAM achieves a cycle time of 1.9µs (=0.526MHz) at 0.38V. The operating power is 1.70µW at this voltage. The minimum energy per access is 1.12 pJ/bit when the supply voltage is 0.44V. The proposed STT-MRAM operates at a lower energy than an SRAM when the utilization of the memory bandwidth is 14% or less.

Spin-torque transfer magnetic random access memory (STT-MRAM) is a promising technology for next generation nonvolatile universal memory because it reduces the high write current required by conventional MRAM and enables write current scaling as technology becomes smaller in size. However, the sensing margin is not improved in STT-MRAM and tends to decrease with technology scaling due to the lowered supply voltage and increased process variation. Moreover, read disturbance, which is an unwanted write in a read operation, can occur in STT-MRAM because its read and write operations use the same path. To overcome these problems, we present a load-line analysis method, which is useful for systematically analyzing the impacts of transistor size and gate voltage of MOSFETs on the sensing margin, and also propose an optimization procedure for the commonly applicable MRAM sensing circuits. This methodology constitutes an effective means to optimize the transistor size and gate voltage of MOSFETs and thus maximizes the sensing margin without causing read disturbance.

In this paper, we have succeeded in the fabrication of high performance Magnetic Tunnel Junction (MTJ) which is integrated in CMOS circuit with 4-Metal/ 1-poly Gate 0.14 µm CMOS process. We have measured the DC characteristics of the MTJ that is fabricated on via metal of 3rd layer metal line. This MTJ of 60180 nm2 achieves a large change in resistance of 3.52 kΩ (anti-parallel) with TMR ratio of 151% at room temperature, which is large enough for sensing scheme of standard CMOS logic. Furthermore, the write current is 320 µA that can be driven by a standard MOS transistor. As the results, it is shown that the DC performance of our fabricated MTJ integrated in CMOS circuits is very good for our novel spin logic (MTJ-based logic) device.

We propose an MRAM macro architecture for SoCs to reduce their area size. The shared write-selection transistor (SWST) architecture is based on 2T1MTJ MRAM cell technology, which enables the same fast access time with a smaller cell area than that of 6T SRAMs. We designed a 4-Mb macro using the SWST architecture with a 0.15-µm CMOS process and a 0.24-µm MRAM process. The macro cell array consists of 81T64MTJ cell array elements, each storing 64 bits of data. The area size is reduced by more than 30%. By introducing a leakage-replication (LR) read scheme, a wide read margin on a test chip is accomplished and 50-ns access time is achieved with SPICE simulation. The 2T1MTJ macro and 81T64MTJ macro can be integrated into a single SoC.

Apart from magnetic random access memories (MRAM), nonvolatile memories cannot be used without causing fatigue. As the use of MRAMs can solve fatigue problems, MRAMs have a large potential to open up large new markets. The manufacturing cost of LSIs cannot be reduced while they have not been produced massively. To increase the size of the MRAM market, new applications, in which MRAMs create added value, are needed. A demo system that models a drive recorder was developed to introduce the novel features of MRAMs, and a 4-Mb MRAM was developed to be used in the demo system.

We propose a writing circuit scheme to screen intermittent failure cells for toggle MRAM. The scheme, comprising a current waveform circuitry that controls rise/fall time of writing current, drastically decreases the probability of intermittent failure. To apply the scheme to large-capacity MRAMs, a current booster containing discharging capacitors has also been developed. It adjusts the waveform of writing current to that designed by the current waveform circuitry even in presence of parasitic capacitors and resistors along the writing current path. Such a technique is essential for achieving stability in large-capacity MRAMs.

A tunneling magnetoresistive(TMR)-based logic-in- memory circuit, where storage functions are distributed over a logic-circuit plane, is proposed for a low-power VLSI system. Since the TMR device is regarded as a variable resistor with a non-volatile storage capability, any logic functions with external inputs and stored inputs can be performed by using the TMR-based resistor/transistor network. The combination of dynamic current-mode circuitry and a TMR-based logic network makes it possible to perform any switching operations without steady current, which results in power saving. A design example of an SAD unit for MPEG encoding is discussed, and its advantages are demonstrated.

MRAM-writing circuitry to compensate for the thermal variation of the magnetization-reversal current is proposed. The writing current of the proposed circuitry is designed to decrease in proportion to an increase in temperature. This technique prevents multiple-write failures from degrading 1 Gb MRAM yield where the standard deviation of magnetization-reversal current variation from other origins is less than 5%.