In recent years, the growing density and complexity of VLSIs have led to an increase in the numbers of test patterns and fault models. Test patterns used in VLSI testing are required to provide high quality and low cost. Don't care (X) identification techniques and X-filling techniques are methods to satisfy these requirements. However, conventional X-identification techniques are less effective for application-specific fields such as test compaction because the X-bits concentrate on particular primary inputs and pseudo primary inputs. In this paper, we propose a don't care identification method for test compaction. The experimental results for ITC'99 and ISCAS'89 benchmark circuits show that a given test set can be efficiently compacted by the proposed method.

In this paper, we propose the Perceptual Shape Decomposition (PSD) to detect fingers for a Kinect-based hand gesture recognition system. The PSD is formulated as a discrete optimization problem by removing all negative minima with minimum cost. Experiments show that our PSD is perceptually relevant and robust against distortion and hand variations, and thus improves the recognition system performance.

This paper reports an advanced millimeter-wave radar system to enable detection of vehicles and pedestrians in wide areas around the radar site such as an intersection. We focus on a pulse coding scheme using complementary codes to reduce range sidelobe for discriminating vehicles from pedestrians with high accuracy. In order to suppress sidelobe increase created by RF circuit imperfections, a π/2 shift pulse modulation method with a complementary code pair cycle is presented. Moreover, in order to improve the angular resolution, a high-resolution direction of arrival estimation involving Tx beam scanning is presented. Experiments on a prototype confirm its range sidelobe suppression exceeds 40dB and its angular resolution is 5° for two human's separation at the distance of about 10m in an anechoic chamber. In a trial intersection experiment, a pedestrian detection rate of 95% was achieved at the false alarm rate of 10% in the range from 5m to 40m. The results prove the system's feasibility for future automotive safety application.

This paper presents a novel data compression method for testing integrated circuits within the framework of pattern run-length coding. The test set is firstly divided into 2n-length patterns where n is a natural number. Then the compatibility of each pattern, which can be an external type, or an internal type, is analyzed. At last, the codeword of each pattern is generated according to its analysis result. Experimental results for large ISCAS89 benchmarks show that the proposed method can obtain a higher compression ratio than existing ones.

Regular on-site testing is an elementary means to obtain real-time data and state of Electromagnetic Compatibility (EMC) of electronics systems. Nowadays, there is a lot of measured EMC data while the application of the data is insufficient. So we put forward the concept of EMC model synthesis. To carry out EMC data mining with measured electromagnetic data, we can build or modify models and synthesize variation rules of electromagnetic parameters of equipment and EMC performance of systems and platforms, then realize the information synthesis and state prediction. The concept of EMC reliability is brought forward together with the definition and description of parameters such as invalidation rate and EMC lifetime. We studied the application of statistical algorithms and Artificial Neural Network (ANN) in model synthesis. Operating flows and simulation results as well as measured data are presented. Relative research can support special measurement, active management and predictive maintenance and replenishment in the area of EMC.

We propose an asynchronous datapath for the low-density parity-check decoder to decrease power consumption. Glitches and redundant computations are decreased by the asynchronous design. Taking advantage of the statistical characteristics of the input data, we develop novel key arithmetic elements in the datapath to reduce redundant computations. Two other types of datapaths, including normal synchronous design and clock-gating design, are implemented for comparisons with the proposed design. The three designs use similar architectures and realize the same function by using the 0.18µm process of the Semiconductor Manufacturing International Corporation. Post-layout result shows that the proposed asynchronous design exhibits the lowest power consumption. The proposed asynchronous design saves 48.7% and 21.9% more power than the normal synchronous and clock-gating designs, respectively. The performance of the proposed datapath is slightly worse than the clock-gating design but is better than the synchronous design. The proposed design is approximately 7% larger than the other two designs.

Nowadays, fault tolerance has been playing a progressively important role in covering increasing soft/hard error rates in electronic devices that accompany the advances of process technologies. Research shows that wear-out faults have a gradual onset, starting with a timing fault and then eventually leading to a permanent fault. Error detection is thus a required function to maintain execution correctness. Currently, however, many highly dependable methods to cover permanent faults are commonly over-designed by using very frequent checking, due to lack of awareness of the fault possibility in circuits used for the pending executions. In this research, to address the over-checking problem, we introduce a metric for permanent defects, as operation defective probability (ODP), to quantitatively instruct the check operations being placed only at critical positions. By using this selective checking approach, we can achieve a near-100% dependability by having about 53% less check operations, as compared to the ideal reliable method, which performs exhaustive checks to guarantee a zero-error propagation. By this means, we are able to reduce 21.7% power consumption by avoiding the non-critical checking inside the over-designed approach.

Clustering methods are divided into hierarchical clustering, partitioning clustering, and more. K-Means is a method of partitioning clustering. We improve the performance of a K-Means, selecting the initial centers of a cluster through a calculation rather than using random selecting. This method maximizes the distance among the initial centers of clusters. Subsequently, the centers are distributed evenly and the results are more accurate than for initial cluster centers selected at random. This is time-consuming, but it can reduce the total clustering time by minimizing allocation and recalculation. Compared with the standard algorithm, F-Measure is more accurate by 5.1%.

The purpose of this study is to develop an automated scheme of carotid artery calcification (CAC) detection on dental panoramic radiographs (DPRs). The CAC is one of the indices for predicting the risk of arteriosclerosis. First, regions of interest (ROIs) that include carotid arteries are determined on the basis of inflection points of the mandibular contour. Initial CAC candidates are detected by using a grayscale top-hat filter and a simple grayscale thresholding technique. Finally, a rule-based approach and a support vector machine to reduce the number of false positive (FP) findings are applied using features such as area, location, and circularity. A hundred DPRs were used to evaluate the proposed scheme. The sensitivity for the detection of CACs was 90% with 4.3 FPs (80% with 1.9 FPs) per image. Experiments show that our computer-aided detection scheme may be useful to detect CACs.

Many High-Dynamic-Range (HDR) rendering techniques have been developed. Of these, the image color appearance model, iCAM, is a typical HDR image rendering algorithm. HDR rendering methods normally require a tone compression process and include many color space transformations from the RGB signal of an input image to the RGB signal of output devices for the realistic depiction of a captured image. The iCAM06, which is a refined iCAM, also contains a tone compression step and several color space conversions for HDR image reproduction. On the other hand, the tone compression and frequent color space changes in the iCAM06 cause color distortion, such as a hue shift and saturation reduction of the output image. To solve these problems, this paper proposes a separate color correction method that has no effect on the output luminance values by controlling only the saturation and hue of the color attributes. The color saturation of the output image was compensated for using the compensation gain and the hue shift was corrected using the rotation matrix. The separate color correction method reduces the existing color changes in iCAM06. The compensation gain and rotation matrix for the color correction were formulated based on the relationship between the input and output tristimulus values through the tone compression. The experimental results show that the revised iCAM06 with the proposed method has better performance than the default iCAM06.

Comparable Corpora are valuable resources for many NLP applications, and extensive research has been done on information mining based on comparable corpora in recent years. While there are not enough large-scale available public comparable corpora at present, this paper presents a bi-directional CLIR-based method for creating comparable corpora from two independent news collections in different languages. The original Chinese document collections and English documents collections are crawled from XinHuaNet respectively and formatted in a consistent manner. For each document from the two collections, the best query keywords are extracted to represent the essential content of the document, and then the keywords are translated into the language of the other collection. The translated queries are run against the collection in the same language to pick up the candidate documents in the other language and candidates are aligned based on their publication dates and the similarity scores. Results show that our approach significantly outperforms previous approaches to the construction of Chinese-English comparable corpora.

Anomaly-based worm detection is a complement to existing signature-based worm detectors. It detects unknown worms and fills the gap between when a worm is propagated and when a signature is generated and downloaded to a signature-based worm detector. A major obstacle for its deployment to personal computers (PCs) is its high false positive alarms since a typical PC user lacks the skill to handle exceptions flagged by a detector without much knowledge of computers. In this paper, we exploit the feature of personal computers in which the user interacts with many running programs and the features combining various network characteristics. The model of a program's network behaviors is conditioned on the human interactions with the program. Our scheme automates detection of unknown worms with dramatically reduced false positive alarms while not compromising low false negatives, as proved by our experimental results from an implementation on Windows-based PCs to detect real world worms.

A coarse-grained reconfigurable architecture (CGRA) is typically hybrid architecture, which is composed of a reconfigurable processing unit (RPU) and a host microprocessor. Many computation-intensive kernels (e.g., loop nests) are often mapped onto RPUs to speed up the execution of programs. Thus, mapping optimization of loop nests is very important to improve the performance of CGRA. Processing element (PE) utilization rate, communication volume and reconfiguration cost are three crucial factors for the performance of RPUs. Loop transformations can affect these three performance influencing factors greatly, and would be of much significance when mapping loops onto RPUs. In this paper, a joint loop transformation approach for RPUs is proposed, where the PE utilization rate, communication cost and reconfiguration cost are under a joint consideration. Our approach could be integrated into compilers for CGRAs to improve the operating performance. Compared with the communication-minimal approach, experimental results show that our scheme can improve 5.8% and 13.6% of execution time on motion estimation (ME) and partial differential equation (PDE) solvers kernels, respectively. Also, run-time complexity is acceptable for the practical cases.

We propose a composite DCT basis line test signal to evaluate the video quality of a DTV encoder. The proposed composite test signal contains a frame index, a calibration square wave, and 7-field basis signals. The results show that the proposed method may be useful for an in-service video quality verifier, using an ordinary oscilloscope instead of special equipment.

Scaling up the system size has been the common approach to achieving high performance in parallel computing. However, designing and implementing a large-scale parallel system can be very costly in terms of money and time. When building a target system, it is desirable to initially build a smaller version by using the processing nodes with the same architecture as those in the target system. This allows us to achieve efficient and scalable prediction by using the smaller system to predict the performance of the target system. Such scalability prediction is critical because it enables system designers to evaluate different design alternatives so that a certain performance goal can be successfully achieved. As the de facto standard for writing parallel applications, MPI is widely used in large-scale parallel computing. By categorizing the discrete event simulation methods for MPI programs and analyzing the characteristics of scalability prediction, we propose a novel simulation method, called virtual-actual combined execution-driven (VACED) simulation, to achieve scalable prediction for MPI programs. The basic idea behind is to predict the execution time of an MPI program on a target machine by running it on a smaller system so that we can predict its communication time by virtual simulation and obtain its sequential computation time by actual execution. We introduce a model for the VACED simulation as well as the design and implementation of VACED-SIM, a lightweight simulator based on fine-grained activity and event definitions. We have validated our approach on a sub-system of Tianhe-1A. Our experimental results show that VACED-SIM exhibits higher accuracy and efficiency than MPI-SIM. In particular, for a target system with 1024 cores, the relative errors of VACED-SIM are less than 10% and the slowdowns are close to 1.

This paper introduces the concept of order complexity, which represents the minimum number of partial ordering operations to make a string of perfectly ordered symbols. A novel variable-length code expressing such order complexity using binary digits is proposed herein. The proposed code is general, uniquely decipherable, and useful for coding a string of random permuted symbols having unknown statistics or which are preferred to have a uniform distribution.

Binary sequences with good autocorrelation and large linear complexity have found many applications in communication systems. A construction of almost difference sets was given by Cai and Ding in 2009. Many classes of binary sequences with three-level autocorrelation could be obtained by this construction and the linear complexity of two classes of binary sequences from the construction have been determined by Wang in 2010. Inspired by the analysis of Wang, we deternime the linear complexity and the minimal polynomials of another class of binary sequences, i.e., the class based on the WG difference set, from the construction by Cai and Ding. Furthermore, a generalized version of the construction by Cai and Ding is also presented.

Bandwidth expansion in Long Term Evolution (LTE)-Advanced is supported via carrier aggregation (CA), which aggregates multiple component carriers (CCs) to accomplish very high data rate communications. Heterogeneous networks (HetNets), which set pico-base stations in macrocells are also a key feature of LTE-Advanced to achieve substantial gains in coverage and capacity compared to macro-only cells. When CA is applied in HetNets, transmission on all CCs may not always be the best solution due to the extremely high levels of inter-cell interference experienced by HetNets. Activated CCs that are used for transmission should be selected depending on inter-cell interference conditions and the traffic offered in the cells. This paper presents a scheme to select CCs through centralized control assuming a centralized baseband unit (C-BBU) configuration. A C-BBU involves pooling tens or hundreds of baseband resources where one baseband resource can be connected to any CC installed in remote radio heads (RRHs) via optical fibers. Fewer baseband resources can be prepared in a C-BBU than those of CCs in RRHs to reduce the cost of equipment. Our proposed scheme selects the activated CCs by considering the user equipment (UE) assigned to CCs under the criterion of maximizing the proportional fairness (PF) utility function. Convex optimization using the Karush-Kuhn-Tucker (KKT) conditions is applied to solve the resource allocation ratio that enables user throughput to be estimated. We present results from system level simulations of the downlink to demonstrate that the proposed algorithm to select CCs can outperform the conventional one that selects activated CCs based on the received signal strength. We also demonstrate that our proposed algorithm to select CCs can provide a good balance in traffic load between CCs and achieve better user throughput with fewer baseband resources.

A vertex cover of a given graph G = (V,E) is a subset N of V such that N contains either u or v for any edge (u,v) of E. The minimum weight vertex cover problem (MWVC for short) is the problem of finding a vertex cover N of any given graph G = (V,E), with weight w(v) for each vertex v of V, such that the sum w(N) of w(v) over all v of N is minimum. In this paper, we consider MWVC with w(v) of any v of V being a positive integer. We propose simple procedures as postprocessing of algorithms for MWVC. Furthremore, five existing approximation algorithms with/without the proposed procedures incorporated are implemented, and they are evaluated through computing experiment.

This paper presents a digitally error-corrected pipeline analog-to-digital converter (ADC) using linearization of incomplete settling errors. A pre-charging technique is used for residue amplifiers in order to reduce the incomplete settling error itself and linearize the input signal dependency of the incomplete settling error. A technique with charge redistribution of divided capacitors is proposed for pre-charging capacitors without any additional reference sources. This linearized settling error is corrected by a first-order error approximation in digital domain with feasible complexity and cost. Simulation results show that the ADC achieves SNDR of 70 dB, SFDR of 79 dB at nyquist input frequency in a 65 nm CMOS process under 1.2 V power supply voltage for 1.2 Vp-p input signal swing. The estimated power consumption of the 12b 200 MS/s pipeline ADC using the proposed digital error correction of incomplete settling errors is 7.6 mW with a small FOM of 22 fJ/conv-step.