Recently, two new efficient server-aided RSA secret computation protocols were proposed. They are efficient and can guard against some active attacks. In this letter, we propose two multi-round active attacks which can effectively reduce their security level even break them.

This paper describes a mobile information access system based on a multi-agent architecture. With the rapid progress of wireless data communications, mobile Internet access will be more and more popular. In mobile environments, user location plays an important role for information filtering and flexible communication service. In this paper, we propose a mobile information service system where a user with a handy terminal accesses Internet in an open air to look up map information and related town information. Each user information is managed by an independent agent process. And the agent provides each user with a personal service collaborating with other applications. A map-based information service example based on this architecture is also described.

This paper describes technological and operational issues of an image-art-on-demand system, which provides visitors with high-definition images of fine art in a virtual gallery. The system is presented as a typical example of multimedia information service systems on IP over ATM network. The high-definition images of fine arts from a database are interactively selected in a virtual gallery which is generated by an advanced computer graphics (CG) workstation. The generated images of the virtual gallery are transmitted by MPEG-2 over TCP/IP on ATM at 30 frames per second. This system was opened from January 1996 to March 1997 as one project of NTT's joint utilization tests of multimedia communications. As far as we know, this system is the first real-time image-art-on-demand system using MPEG-2 on IP over ATM-WAN to be exhibited to the general public.

This paper proposes a new approach that makes it possible for every undergraduate student to perform experiments of developing a Ipipelined RISC processor within limited time available for the course. The approach consists of 4 steps. At the first step, every student implements by himself/herself a pipelined RISC processor which is based on a given, very simple model; it has separate buses for instruction and data memory ("Harvard architecture") to avoid structural hazard, while it completely ignores data control hazards to make implementation easy. Although it is such a "defective" processor, we can test its functionality by giving object code containing sufficient amount of NOP instructions to avoid hazards. At the second step, NOP instructions are deleted and behavior of the developed processor is observed carefully to understand data and control hazards. At the third step, benchmark problems are provided, and every student challenges to improve its performance. Finally every student is requested to present how he/she improved the processor. This paper also describes a new educational FPGA board ASAver.1 which is useful for experiments from introductory class to computer architecture/system class. As a feasibility study, a 16-bit pipelined RISC processor "ASAP-O" has been developed which has eight 16-bit general purpose registers, a 16-bit program counter, and a zero flag, with 10 essential instructions.

Entire systems embedded in a chip and consisting of a processor, memory, and system-specific peripheral hardware are now commonly contained in commodity electronic devices. Cost minimization of these systems is of paramount economic importance to manufactures of these devices. By employing a variable configuration processor in conjunction with a multi-precision compiler generator, we show that there are situations in which considerable system cost reduction can be obtained by synthesizing a CPU that is narrower than the largest variable in the application program.

We present a novel replication technique for parallel applications where instances of the replicated application are active on different group of processors called replicas. The replication technique is based on the FTAG (Fault Tolerant Attribute Grammar) computation model. FTAG is a functional and attribute based model. The developed replication technique implements "active parallel replication," that is, all replicas are active and compute concurrently a different piece of the application parallel code. In our model replicas cooperate not only to detect and mask failures but also to perform parallel computation. The replication mechanisms are supported by FTAG run time system and are fully application-transparent. Different novel mechanisms for checkpointing and recovery are developed. In our model during rollback recovery only that part of the computation that was detected faulty is discarded. The replication technique takes full advantage of parallel computing to reduce overall computation time.

Advanced scientific and engineering problems require massively parallel computing. Critical to the designand ultimately the performanceof such computing systems is the interconnection network binding the computing elements, just as is the cardiovascular network to the human body. This paper develops a new interconnection network, "Tori connected mESHes (TESH)," consisting of k-ary n-cube connection of supernodes that comprise meshes of lower level nodes. Its key features are the following: it is hierarchical, thus allowing exploitation of computation locality as well as easy expansion (up to a million processors), and it appears to be well suited for 3-D VLSI implementation, for it requires far fewer number of vertical wires than almost all known multi-computer networks. Presented in the paper are the architecture of the new network, node addressing and message routing, 3-D VLSI/ULSI considerations, and application of the network to massively parallel computing. Specifically, we discuss the mapping on to the network of stack filtering, a hardware oriented technique for order statistic image filtering.

We propose an instruction-based variable priority scheme (IBVPS) which achieves high sustained memory throughput on a TCMP type vector supercomputer. Generally, there are two approaches to arbitrating interprocessor memory access conflict: request level priority control and fixed priority control. Each approach, however, affects performance in its own way: In the case of request level priority control, mutual obstruction causes a performance degradation, and in the case of fixed priority control, memory bank monopoly causes a performance degradation. Mutual obstruction refers to the interference among access requests coming from different instructions; memory bank monopoly refers to the un-interrupted accessing of the same memory bank by a series of higher priority instructions. The strategy of the instruction-based variable priority scheme consists in: (a) generally changing the priority assignment of all load/store pipelines at the end of any instruction running in the system, and (b) changing the priority assignment of all load/store pipelines more than once in the middle of an access instruction with a stride greater than 1 or an indirect access instruction which may monopolize some memory banks for an extended period of time. This strategy reduces mutual obstruction because the priority assignment is reshuffled for the entire group of load/store pipelines at a time. it also reduces memory bank monopoly because the opportunity for memory access is made equal among different instructions by changing the priority assignment at the end of an instruction. Moreover, it prevents the memory bank monopoly by a memory access instruction with a stride greater than 1 or an indirect access instruction, by changing the priority assignment more frequently. Consequently, high sustained memory throughput is achieved on TCMP type vector supercomputers.

The performance of a noncoherent parallel matched-filter (MF) acquisition scheme with a reference filter (RF) is evaluated for a direct-sequence/spread-spectrum multiple access (DS/SSMA) packet radio system in a mobile cellular environment. This acquisition scheme employs a RF to estimate the variance of interference at the output of detecting MF. Acquisition-based packet throughput of the parallel NM-RF scheme is derived for an AWGN and a Rayleigh fading channels. Packet throughput of a parallel MF-RF acquisition scheme is compared with those of a serial MF scheme, a serial MF-RF scheme, and a parallel MF. From the numerical results, it is shown that the packet throughput decreases with the number of users in the system, and increases with the preamble length. Imperfect power control causes packet throughput to decrease especially when the power control error is large. The considerations in this paper can be applied to the reverse link (mobile-to-base station) design of a DS/SSMA system for packet-type services.

This paper presents a new multi-clustering network for the purpose of intelligent data classification. In this network, the first layer is a self-organized clustering layer and the second layer is a restricted clustering layer with a neighborhood mechanism. A new clustering algorithm is developed in this system for the efficiently use of parallel processors. This parallel algorithm enables the nodes of this network to be independently processed in order to minimize data communication load among processors. Using the parallel processors, the quite low calculation cost can be realized among the conventional networks. For example, a 4-processor parallel computing system has shown its ability to reduce the time taken for data classification to 26.75% of a single processor system without declining its performance.

A fully differential folded cascode CMOS OP amp is combined with an adaptive bias OTA to increase the slew rate, and a continuous-time CMFB circuit with a push-pull type combination of a NMOS input and a PMOS input differential amplifiers is used to maximize the output voltage swing. The fabricated OP amp using a 0.8 µm digital CMOS process gives more than three times improvement in slew rate with a 15% increase in DC power consumption and a 7.5% increase in chip area compared to the conventional OP amp fabricated on the same die. The output voltage swing was measured to be -0.75 V -0.7 V at the supply voltage of +/-1.2 V.

Recently, many types of high-density recording technologies for future MO (Magneto-Optical) storage have been reported. MSR (Magnetically Induced Super Resolution) technology is one of the most promising candidates, and over ten types of MSR technologies have been already proposed. However, they are not well-discussed from the viewpoint of total recording technology which would include the recording and readout methods, the pick-up technology and the signal processing technology. Key technologies for realizing MO storage of over 7 GBytes in a CD-sized disk using a red laser are proposed, and the experimental results pertaining to each key technology are described. The write/read characteristics were examined for the CAD (Center Aperture Detection)-MSR disk. From the characteristics of the CAD-MSR disk combined with laser pumped magnetic field modulation recording, it was shown that land/groove (0.7 µm width) recording with the linear density of 0.27 µm/bit and track pitch below 0.7 µm can be realized. It was also shown that CAD-MSR disk is well combined with an OSR (Optical Super Resolution) pick up, laser pumped read-out and PRML (Partial Response Maximum Likelihood) technologies which are very useful to achieve a high density MO disk. Using CAD-MSR disk combined with above technologies together, high density write/read with a bit length of 0.2 µm and a track pitch of 0.6 µm should be realized with using the laser of 635 nm wavelength. Applying the CAD-MSR disks to a CD sized MO disk, the capacity becomes over 7 GBytes (Format efficiency: 80%), which is 20 times higher than 5.25 inches MO disk and 1.5 times than DVD-ROM.

A punctured convolutional coded PR4ML system for digital magnetic recording, which applies a punctured coding method to the convolutional code and records the punctured code sequences on two tracks, is proposed. In this study, the bit error rate performance of the proposed system is obtained by computer simulation taking account of partial erasure, which is one of the nonlinear distortions at high densities, and it is compared with those of a conventional 8/9 coded PR4ML system and an I-NRZI coded PR4ML system. The results show that the proposed system is hardly affected by partial erasure and exhibits good performance in high-density recording. A bit error rate of 10-4 can be achieved with SNR's of approximately 13.2 dB and 9.1 dB less than those of the conventional 8/9 coded and I-NRZI coded PR4ML systems, respectively, at a normalized linear density of 3.

Time decay of magnetic properties in perpendicular magnetic recording media was studied. It was suggested that magnetization in media with a low energy ratio, KV/kT, of 50 is thermally stable in the absence of a demagnetizing field while coercivity exhibits a large time dependence. Magnetization in perpendicular recording media exhibited an appreciable time decay even for films with a large energy ratio of 300. The decay is attributed to the small perpendicular squareness due to a large perpendicular demagnetizing field acting in the media. The recording density dependence of the time decay in the output was explained in terms of the change in the demagnetizing field with the density. It is concluded that the use of media with large squareness as well as large energy ratio effectively reduces time decay in the output.

In this paper, we propose a new switching network architecture with output queueing, The proposed switch, FBSF (FAB Banyan Switching Fabrics) can deliver up to 2r packets simultaneously destined for the same outlet in a single time slot. The switch fabrics consist of Batcher sorter, a radix-r double shuffle network r-packet distributors, two FAB networks, and output buffer modules. The performance of the switch fabric is evaluated by measures of throughput, average queue length, average waiting time, and packet loss rate. Numerical and simulation results indicate that the switch exhibits very good delay-throughput performance over a wide range of input traffic.

Linear programming techniques are useful in many diverse applications such as: production planning, energy distribution etc. To find an optimal solution of the linear programming problem, we have to repeat computations and it takes a lot of processing time. For high speed computation of linear programming, special purpose hardware has been sought. This paper proposes a systolic array for solving linear programming problems using the revised simplex method which is a typical algorithm of linear programming. This paper also proposes a modified systolic array that can solve linear programming problems whose sizes are very large.

For the solutions of linear systems of equations with unsymmetric coefficient matrices, we propose an improved version of the quasi-minimal residual (IQMR) method by using the Lanczos process as a major component combining elements of numerical stability and parallel algorithm design. For Lanczos process, stability is obtained by a coupled two-term procedure that generates Lanczos vectors scaled to unit length. The algorithm is derived such that all inner products and matrixvector multiplications of a single iteration step are independent and communication time required for inner product can be overlapped efficiently with computation time. Therefore, the cost of global communication on parallel distributed memory computers can be significantly reduced. The resulting IQMR algorithm maintains the favorable properties of the Lanczos process while not increasing computational costs. The efficiency of this method is demonstrated by numerical experimental results carried out on a massively parallel distributed memory computer, the Parsytec GC/PowerPlus.

We present a scalable parallel memory architecture with a skew scheme by which permanent-concentration-free strides, if any, do not depend on the number of ways in parallel memory interleaving. The permanent-concentration is a kind of memory access conflict. With conventional skew schemes, permanent-concentration-free strides depended on the number of banks (or bank groups) in parallel memory (=number of ways in parallel memory interleaving). We analyze two kinds of cause of conflicts: permanent-concentration occurs when memory access requests concentrate in limited number of banks (or bank groups) in parallel memory, and transient-concentration, when memory access requests transiently concentrate in some banks (or bank groups) in parallel memory. We have identified permanent-concentration-free strides, which are independent of the number of banks (or bank groups) in parallel memory, by solving two concentrations separately. The strategy is to increase the size of address block of shifting address assignment to the parallel memory in order to reduce permanent-concentrations, and make the size of the buffer for each banks (or bank groups) in the parallel memory match the size of address block of shifting in order to absorb transient-concentrations. The skew scheme uses the same size of address block of shifting address assignment for memory systems for different numbers of banks (or bank groups) in parallel memory. As a result, scalability for permanent-concentration-free strides is achieved independent of the number of banks (or bank groups) in parallel memory.

Obradovic and Parberry showed that any n-input k-ary function can be computed by a depth 4 unit-weight k-ary threshold circuit of size O(nkn). They also showed that any n-input k-ary symmetric function can be computed by a depth 6 unit-weight k-ary threshold circuit of size O(nk+1). In this paper, we improve upon and expand their results. The k-ary threshold circuits of nonunit weight and unit weight are considered. We show that any n-input k-ary function can be computed by a depth 2 k-ary threshold circuit of size O(kn-1). This means that depth 2 is optimal for computing some k-ary functions (e.g., a PARITY function). We also show that any n-input k-ary function can be computed by a depth 3 unit-weight k-ary threshold circuit of size O(kn). Next, we show that any n-input k-ary symmetric function can be computed by a depth 3 k-ary threshold circuit of size O(nk-1), and can be computed by a depth 3 unit-weight k-ary threshold circuit of size O(knk-1). Finally, we show that if the weights of the circuit are polynomially bounded, some k-ary symmetric functions cannot be computed by any depth 2 k-ary threshold circuit of polynomial-size.

Many network protocols for routing messages have been proposed for mobile computing environments. In this paper, we consider the query processing strategy which operates over these network protocols. To begin with, we introduce five fundamental location update methods based on ideas extracted from the representative network protocols. They are the single broadcast notification (SBN), the double broadcast notification (WBN), the single default notification (SDN), the double default notification (WDN), and the no notification (NN). As a network protocol, each method is strong in performance in some system enrivonment, but weak in others. In practical situations, where various kinds of applications are used for various purposes, however, it is required to use a single method. We therefore propose an adaptive query processing strategy where these five location update methods can be dynamically selected. Moreover, we analyze the performance of this adaptive query processing strategy via the Markov chain. We also use the statistical approach to estimate the traffic of individual hosts. Finally, we show the efficiency of our proposed strategy over a wide area of system environments.