In this paper, an artificial sub-threshold oscillating spiking neuron is presented and its response phenomena to an input spike-train are analyzed. In addition, a dynamic parameter update rule of the neuron for achieving synchronizations to the input spike-train having various spike frequencies is presented. Using an analytical two-dimensional return map, local stability of the parameter update rule is analyzed. Furthermore, a pulse-coupled network of the neurons is presented and its basic self-organizing function is analyzed. Fundamental comparisons are also presented.

This paper presents two circuits to measure pulse width distribution of single event transients (SETs). We first review requirements for SET measurement in accelerated neutron radiation test and point out problems of previous works, in terms of time resolution, time/area efficiency for obtaining large samples and certainty in absolute values of pulse width. We then devise two measurement circuits and a pulse generator circuit that satisfy all the requirements and attain sub-FO1-inverter-delay resolution, and propose a measurement procedure for assuring the absolute width values. Operation of one of the proposed circuits was confirmed by a radiation experiment of alpha particles with a fabricated test chip.

This paper presents a systemic analysis for phase noise performances of differential cross-coupled LC oscillators by using Hajimiri and Lee's model. The effective impulse sensitivity functions (ISF) for each noise source in the oscillator is mathematically derived. According to these effective ISFs, the phase noise contribution from each device is figured out, and phase noise contributions from the device noise in the vicinity of the integer multiples of the resonant frequency, weighted by the Fourier coefficients of the effective ISF, are also calculated. The explicit closed-form expression for phase noise of the oscillator is definitely determined. The validity of the phase noise analysis is verified by good simulation agreement.

A dual-mode pulse-triggered flip-flop design supporting functional versatility is presented. A low-complexity unified logic module, consisting of only five transistors, for dual-mode pulse generation is devised using pass transistor logic (PTL). Potential threshold voltage loss problem is successfully resolved to ensure the signal integrity. Despite the extra logic for dual-mode operations, the circuit complexity of the proposed design is comparable to those of the single mode designs. Simulations in different process corners and switching activities prove the competitive performance of proposed design against various single mode designs.

A K-exponential filter is derived and utilized for pulse shaping to reduce peak to average power ratio (PAPR) without intersymbol interference (ISI). While keeping the same bandwidth, the frequency responses of the filters vary with different values of the parameter k. The minimum PAPR is associated with a value of the parameter k when the roll-off factor α is specified. Simulations show that the PAPR can be reduced compared with the raised cosine (RC) filter in various systems. The derived pulse shaping filters also provide better performance in PAPR reduction compared with the existing filters.

This paper describes a nonlinear filter that can extract the image feature from noise corrupted image labeled self-quotient ε-filter (SQEF). SQEF is an improved self-quotient filter (SQF) to extract the image feature from noise corrupted image. Although SQF is a simple approach for feature extraction from the images, it is difficult to extract the feature when the image includes noise. On the other hand, SQEF can extract the image feature not only from clear images but also from noise corrupted images with uniform noise, Gaussian noise and impulse noise. We show the algorithm of SQEF and describe its feature when it is applied to uniform noise corrupted image, Gaussian noise corrupted image and impulse noise corrupted image. Experimental results are also shown to confirm the effectiveness of the proposed method.

A new type of digital filter for removing impulsive noise in color images is proposed using interactive evolutionary computing. This filter is realized as a rule-based system containing switching median filters. This filter detects impulsive noise in color images with rules and applies switching median filters only at the noisy pixel. Interactive evolutionary computing (IEC) is adopted to optimize the filter parameters, considering the subjective assessment by human vision. In order to detect impulsive noise precisely, complicated rules with multiple parameters are required. Here, the relationship between color components and the degree of peculiarity of the pixel value are utilized in the rules. Usually, optimization of such a complicated rule-based system is difficult, but IEC enables such optimization easily. Moreover, human taste and subjective sense are highly considered in the filter performance. Computer simulations are shown for noisy images to verify its high performance.

A waveform of an ultra wideband impulse radio (UWB-IR) system can be extremely distorted through a channel even for free-space transmission because of antenna dispersion. This highly degrades the link budget performance. Therefore, the understand of antenna characteristics, which effects on waveform distortion, is necessary. This paper studies the waveform distortion due to antenna in free space transmission in UWB-IR system. The link budget is usually evaluated by using the Friis' transmission formula. However, it is not directly applicable to the UWB-IR transmission system. The link budget evaluation formula attended from conventional Friis' transmission formula that takes into account the transmitted waveform, its distortion due to the antennas, the channel and the correlation receiver is proposed. Since the antenna is significant pulse-shaping filters in UWB-IR system, the example kind of the log-periodic dipole antenna (LPDA) is experimentally examined, especially focused on the effect of the template waveforms.

An empirical dispersion formula is proposed and experimentally verified considering higher order modes of the conductor-backed coplanar waveguide with via holes. For this purpose, an effective dielectric constant is extracted up to 100 GHz from measured S-parameters. By fitting the extracted data, an empirical equation is extracted. The simulation of the Gaussian pulse transmission and the comparison results with the modeling data validate the reported expression.

In order to quickly discharge the electrostatic discharge (ESD) energy, an unassisted low-voltage-trigger ESD protection structure is proposed in this work. Under transmission line pulsing (TLP) stress, the trigger voltage, turn-on speed and second breakdown current can be obviously improved, as compared with the traditional protection structure. Moreover there is no need to add any extra mask or do any process modification for the new structure. The proposed structure has been verified in foundry's 0.18-µm CMOS process.

A digital spiking neuron is a wired system of shift registers that can generate spike-trains having various spike patterns by adjusting the wiring pattern between the registers. Inspired by the ultra-wideband impulse radio, a novel theoretical synthesis method of the neuron for application to spike-pattern division multiplex communications in an artificial pulse-coupled neural network is presented. Also, a novel heuristic learning algorithm of the neuron for realization of better communication performances is presented. In addition, fundamental comparisons to existing impulse radio sequence design methods are given.

TR-UWB (Transmitted Reference-Ultra Wide Band) systems have low system complexity since they transmit data with the corresponding reference signals and demodulate the data through correlation using these received signals. However, the BER (Bit Error Rate) performance in the conventional TR-UWB systems is sensitive to the SNR (Signal-to-Noise Ratio) of the reference templates used in the correlator. We propose an improved recursive transceiver structure that effectively minimizes the BER for TR-UWB systems by increasing the SNR of reference templates.

This paper presents a novel spur suppression technique using a three-phase holding pulse for a direct digital synthesizer (DDS) with a two-phase holding digital-to-analog converter (2PH-DAC). A 2PH-DAC, which uses a reverse-sign step-function as a sampling pulse waveform instead of a commonly-used gate function of zeroth-order hold, enhances the first image of aliasing, which is of higher frequency than the fundamental. Therefore, the first image can be treated as a desired signal, while the fundamental and the second image are spurs for a DDS with a 2PH-DAC (2PH-DDS). The main problem of the 2PH-DDS is close spurs in the case that signal frequency is near Nyquist frequency or sampling frequency. This paper proposes a novel spur suppression technique for a 2PH-DDS. A configuration of a 2PH-DDS is first explained, and spectral properties are analyzed. Based on the analysis, a technique using a three-phase holding pulse to cancel spurs is proposed. Evaluated spur levels of the proposed synthesizer are from -51 to -34 dBc, and are improved by 25 dB or more by the proposed technique.

A low power pulse generator design using hybrid logic realization of a 3-input NAND gate is presented. The hybrid logic approach successfully shortens the critical path along the discharging transistor stack and thus reduces the short circuit power consumption during the pulse generation. The combination of pass transistor and full CMOS logic styles in one NAND gate design also helps minimize the required transistor size, which alleviates the loading capacitance of clock tree as well. Simulation results reveal that, compared with prior work, our design can achieve 20.5% and 23% savings respectively in power and circuit area.

A low power impulse radio ultra-wideband (IR-UWB) receiver for DC-960 MHz band is proposed in this paper. The proposed receiver employs multiple DC power-free charge-domain sampling correlators to eliminate the need for phase synchronization. To alleviate BER degradation due to an increased charge injection in a subtraction operation in the sampling correlator than that of an addition operation, a comparator with variable threshold (=offset) voltage is used, which enables an addition-only operation. The developed receiver fabricated in 1.2 V 65 nm CMOS achieves the lowest energy consumption of 17.6 pJ/bit at 100 Mbps in state-of-the-art correlation-based UWB receivers.

In this paper, an ultra low power analog front-end for EPCglobal Class 1 Generation 2 RFID tag is presented. The proposed RFID tag removes the need for high frequency clock and counters used in conventional tags, which are the most power hungry blocks. The proposed clock-free decoder employs an analog integrator with an adaptive current source that provides a uniform decoding margin regardless of the data rate and a link frequency extractor based on a relaxation oscillator that generates frequency used for backscattering. A dual supply voltage scheme is also employed to increase the power efficiency of the tag. In order to improve the tolerance of the proposed circuit to environmental variations, a self-calibration circuit is proposed. The proposed RFID analog front-end circuit is designed and simulated in 0.25 µm CMOS, which shows that the power consumption is reduced by an order magnitude compared to the conventional RFID tags, without losing immunity to environmental variations.

A novel turbo coded modulation scheme, called the turbo-APPM, for deep space optical communications is proposed. The proposed turbo-APPM is a serial concatenation of turbo codes, an accumulator and a pulse position modulation (PPM), where turbo codes act as an outer code while the accumulator and the PPM act together as an inner code. The generator polynomial and the puncturing rule for generating turbo codes are chosen to lower the bit error rate. At the receiver, the joint iterative decoding is performed between the inner decoder and the outer turbo decoder. In the outer decoder, local iterative decoding for turbo codes is conducted. Simulation results are presented showing that the proposed turbo-APPM outperforms all previously proposed schemes such as LDPC-APPM, RS-PPM and SCPPM reported in the literature.

An on-chip Charged Device Model (CDM) ESD protection method for RF ICs is proposed in a 0.13 µm RF process and evaluated by using very fast Transmission Line Pulse (vf-TLP) system. Key design parameters such as triggering voltage (Vt1) and the oxide breakdown voltage from the vf-TLP measurement are used to design input ESD protection circuits for a RF test chip. The characterization and the behavior of a Low Voltage Triggered Silicon Controlled Rectifier (SCR) which used for ESD protection clamp under vf-TLP measurements are also reported. The results measured by vf-TLP system showed that the triggering voltage decreased and the second breakdown current increased in comparison with the results measured by a standard 100 ns TLP system. From the HBM/ CDM testing, the RF test chip successfully met the requested RF ESD withstand level, HBM 1 kV, MM 100 V and CDM 500 V.

The proportionate normalized least mean square algorithm (PNLMS) greatly improves the convergence of the sparse impulse response. It exploits the shape of the impulse response to decide the proportionate step gain for each coefficient. This is not always suitable. Actually, the proportionate step gain should be determined according to the difference between the current estimate of the coefficient and its optimal value. Based on this idea, an approach is proposed to determine the proportionate step gain. The proposed approach can improve the convergence of proportionate adaptive algorithms after a fast initial period. It even behaves well for the non-sparse impulse response. Simulations verify the effectiveness of the proposed approach.

A novel signal transition detector design using as few as 8 transistors is presented. The proposed design cleverly exploits the property of a specific internal state transition to mitigate the voltage degradation problem by employing only one extra transistor. It is thus capable of supporting level intact output signals and eliminating DC power consumption in the trailing buffer. The proposed design, featuring low circuit complexity and low power consumption, is considered useful for applications in self-timed circuits. Simulation results show that, when compared with other pass transistor logic based counterpart designs, as much as 46% savings in power and 28% in area can be achieved by the proposed design.