In this paper, a new narrowband beamformer with derivative constraint is developed for wideband and coherent jammers suppression. The so-called IQML algorithm with linear constraint, which is used to estimate the unknown directions of the jammers in signal-free environment, is shown to be an inappropriate constraint estimator. In this paper, a new IQML algorithm with a norm constraint is considered, which is a consistent estimator and can be used to achieve desired performance. It can be also employed in the CDMA system for MAI suppression. We show that it outperforms the approach with the linear constraint used in the narrowband beamformer, in terms of directional pattern, output SINR and nulling capability for wideband and coherent jammers suppression.

To increase the discriminating ability of the speech feature based on linear predictive coding (LPC) and increase its noise robustness, an SNR-dependent arcsin transform is applied to the autocorrelation sequence (ACS) of each analysis frame in a speech signal. Moreover, each component in the ACS is also weighted by the normalized reciprocal of the average magnitude difference function (AMDF) for emphasizing its peak structure. Experimental results for the task of Mandarin digit recognition indicate that the LPC speech feature employing the proposed scheme is more robust than some widely used LPC-based approaches over a wide range of SNR values.

The square-law characteristics of MOSFET in the saturation region have a parameter of threshold voltage VT. However, it introduces some complexities to the circuit design since it depends on kinds of MOS technology and cannot be controlled easily. In this paper, we show an equivalent MOSFET cell which has VT-programming capability and some application instances based on it. The simulation is carried out using CMOS 0.8 µm n-well technology and the results have shown the feasibility of the proposed structure.

A scalable MOSFET parasitic model has been studied using 0.13 µm standard CMOS process. The model consisted of a core BSIM3v3 transistor model and parasitic resistor, capacitor, inductor, and diode. All parasitic components' values were automatically calculated by transistor geometrical parameters, only gate length (Lg), gate width (Wg), and gate multiple numbers (Mg), and some fixed process parameters such as sheet resistance of each part of diffusion layer. This model was confirmed for 0.25 µm to 0.5 µm gate length, 10 to 40 gate multiples with 5 µm gate finger width (Wf), 0.8 V to 1.5 V gate-source voltage (|Vgs|) with 0.6 V threshold voltage (|Vth|), and 1.0 V to 2.5 V drain-source voltage (|Vds|) from the viewpoint of small signal. The measured s-parameter and simulated one are in fairly good agreement in 200 MHz to 20 GHz frequencies range. This model is very simple, scalable, and convenient for RF circuit designers without difficult parameter setting.

In the past, enhancement techniques for the end-to-end quality of a networked application were studied by looking at each individual layer. Examples of such techniques include the error resilience/concealment methods in the application layer, the FEC/ARQ in the transport layer, and the Quality of Service (QoS) techniques in the network layers. However, an integrated approach that would look across all related layers had yet to be investigated. This paper proposes an approach that combines priority-aware video packetization, adaptively used layered FEC, and QoS controlled networks such as IntServ and DiffServ in order to provide an efficient end-to-end quality in layered streaming video. The combination is more efficient in terms of a simple network price mechanism, that is, in getting the best end-to-end quality under a given total cost constraint. Our proposed approach in DiffServ with video packet (VP) data-splitting and layered FEC guarantees minimal service quality in a scalable and cost effective manner without introducing resource reservation. For video, we also propose performance metrics such as corrupted/frozen frame ratio (CFR, FFR). These provide objective metrics like PSNR as well as a measurement for subjective perceptions. Our approach, which combines related layers such as video coding, transport, and network, has yielded results that have proven to be more cost-effective and practical than the supporting network QoS.

A three inputs and single output voltage-mode universal biquadratic filter using only two operational transconductance amplifiers (OTAs) and two capacitors is presented. The new circuits offer several advantages, such as employing the minimum number of active and passive components (two OTAs and two capacitors), the versatility to synthesize highpass, bandpass, lowpass, notch and allpass responses without component matching conditions, high input impedance for bandpass and lowpass filter realizations and good sensitivities performance.

Directional couplers with flat coupling are designed by using an asymmetrical coupled-HNRD-guide consisting of two HNRD guides of different cross sections arranged closely. First, propagation characteristics of the asymmetrical coupled-HNRD-guide are analyzed by the transverse resonance technique. Next, the whole directional couplers including tapered sections are designed from the S-parameters of the coupled HNRD guides derived from a superposition of the even-like and odd-like modes. Finally, the validity of the design procedure is confirmed by an em-simulator (HFSS).

A high temperature superconductor (HTS) 5 GHz 10-pole bandpass filter (BPF) is designed by using coplanar waveguide (CPW) quarter-wavelength resonators. The 10-pole Chebyshev BPF has a center frequency 5.0 GHz and a fractional bandwidth 3.2%. Based on an equivalent circuit with J- and K-inverters, the filter is first designed by using an EM simulator. Next an optimization algorithm is employed to diagnose the discrepancy between the filter responses calculated by the EM simulator and the equivalent circuit. Adjustment of the dimensions of the filter is made thereby. The frequency response of the adjusted filter satisfies well the design specifications.

This paper describes a highly-portable multilingual question answering system on multiple relational databases. We apply techniques which were verified on open-domain text-based question answering, such as semantic category and pattern-based grammars, into natural language interfaces to relational databases. Lexico-semantic pattern (LSP) and multi-level grammars achieve portability of languages, domains, and DB management systems. The LSP-based linguistic processing does not require deep analysis that sacrifices robustness and flexibility, but can handle delicate natural language questions. To maximize portability, we drive three dependency factors into the following two parts: language-dependent part into front linguistic analysis, and domain-dependent and database-dependent parts into backend SQL query generation. We also support session-based dialog by preserving SQL queries created from previous user's question, and then re-generating new SQL query for the successive questions. Experiments with 779 queries generate only constraint-missing errors, which can be easily corrected by adding new terms, of 2.25% for English and 5.67% for Korean.

In this paper, parallelization methods for quantum circuits are studied, where parallelization of quantum circuits means to reconstruct a given quantum circuit to one which realizes the same quantum computation with a smaller depth, and it is based on using additional bits, called ancillae, each of which is initialized to be in a certain state. We propose parallelization methods in terms of the number of available ancillae, for three types of quantum circuits. The proposed parallelization methods are more general than previous one in the sense that the methods are applicable when the number of available ancillae is fixed arbitrarily. As consequences, for the three types of n-bit quantum circuits, we show new upper bounds of the number of ancillae for parallelizing to logarithmic depth, which are 1/log n of previous upper bounds.

In the FDTD simulation of microwave circuits, a device in very small size compared with the wavelength is often handled as a lumped element, but it may still occupy more than one cell instead of a wire structure without volume routinely employed in classical extended FDTD algorithms. In this paper, two modified extended FDTD algorithms incorporating a lumped element occupying more than one cell are developed directly from the integral form of Maxwell's equations based on the assumption whether displacement current exists inside the region where a device is present. If the displacement current exists, the modified extended FDTD algorithm can be represented as a Norton equivalent current-source circuit, or otherwise as a Thevenin equivalent voltage-source circuit. These algorithms are applied in the microwave line loaded by a lumped resistor and an active antenna to illustrated the efficiency and difference of the two algorithms.

This paper presents a miniaturized reverse-phase hybrid ring by the use of shunt capacitors, and successfully designs a very miniature hybrid ring of a 0.28-wavelength circumference with a wide bandwidth comparable to the regular reverse-phase hybrid ring based on the equivalent admittance approach. Moreover, a method of broadening the bandwidth with adding a matching network consisting of a very short transmission line and two shunt capacitors at each port is also described. The validity of the proposed design is demonstrated by electromagnetic simulator (Sonnet em) for a uniplanar hybrid ring.

Existing research related to RSVP with mobility support has mainly focused on maintaining reservation state along the routing path, which changes continuously with the movements of mobile host (MH), without much overhead and delay. However, problems such as deepening RSVP's inherent scalability problem and requiring significant changes in the existing network infrastructure have not been adequately addressed. In this paper, we propose a new approach, known as Concatenation and Optimization for Reservation Path (CORP), which addresses these issues. In CORP, each BS pre-establishes pseudo reservations to its neighboring BSs in anticipation of the MH's movement. When the MH moves into another wireless cell, the associated pseudo reservation is activated and concatenated to the existing RSVP session to guarantee continuous QoS support. Because a pseudo reservation is recognized as a normal RSVP session by intermediate routers, little change is required in the current Internet environment to support both movements within a single routing domain and between two different routing domains. CORP also dynamically optimizes the extended reservation path to avoid the infinite path extension problem. Multicast addressing is used to further reduce resource consumption in the optimization process. The experimental results of the CORP implementation demonstrate that it significantly reduces the delay and overhead caused by handoffs compared to the case of establishing a new RSVP session. The improvement increases as the distance between the MH and its correspondent host (CH) grows.

Class-based delay differentiation model has been recently proposed as a part of relative differentiated services frameworks, and it is shown that the model can provide delay differentiation without admission control and end-to-end resource reservation. In this paper, however, we observe that there can be inconsistent delay differentiation caused by different size of packets. We propose packet size-based delay differentiation model and show that packet size-based queueing is effective to achieve equal delay within a class and provide consistent delay differentiation between classes through simulations. Simulation results also show that the proposed model improves jitter characteristics of CBR flows.

As multimedia and high-speed traffic become more popular on the Internet, the various traffic requiring different qualities of service (QoS) must co-exist. In addition, classified services based on Diff-Serv (Differentiated Service), MPLS (Multi-Protocol Label Switching), etc., have come into wide use. Today's Internet environment requires routers to perform control mechanisms in order to guarantee various QoSs. In this paper, we propose a smart buffer management scheme for the Internet router that uses hierarchical priority control with port class and flow level. Furthermore, since the proposed scheme must operate at very high speed, we first propose several design policy for high speed operation and the hardware implementation is performed in VHDL code. Implementation results show that the proposed scheme can scale with high-speed link, achieving the maximum rate of 4.0 Gbps by using the 3.5 µm CMOS technology.

This study investigates the anisotropy substrate and dielectric cover effects of the rectangular microstrip patch antenna on anisotropy substrates with air gap, based on rigorous full-wave analysis and Galerkin's moment method. Results show that the resonant frequencies in the variation of air gap, patch length, and permittivity of superstrate can be determined and analyzed with varying dielectric cover thickness.

We propose a new phase interpolator that provides precise fractional phase pulses without the need to adjust circuit constants. The variable phases are produced by detecting the coincidence of two voltages, the ramp wave and the threshold voltage. The new phase interpolator can keep the same ramp wave slope and the same threshold voltage for different output phases. This significantly reduces the power dissipation of the voltage comparator. This phase interpolator can be applied to various timing circuits and clock generators, such as frequency multipliers and direct digital synthesizers. We present a novel frequency doubler, a novel frequency tripler, a direct digital synthesizer (DDS), and a novel wideband DDS (WDDS) as applications of our new phase interpolator, which uses 0.35-mm CMOS process technology. Experimental results confirm the functionarity of the new phase interpolator. An 8-bit complete DDS IC dissipates only 2.1 mA at a 50-MHz clock rate and a supply voltage of 2.8 V.

As an enhancement mechanism for the end-to-end congestion control, AQM (Active Queue Management) can keep smaller queuing delay and higher throughput by purposefully dropping the packets at the intermediate nodes. Comparing with RED algorithm, although the PI (Proportional-Integral) controller for AQM designed by C. Hollot improves the stability, it seems unscientific to tune the controller parameters through trial-error, moreover the transient performance of the PI controller is not perfect, such as the regulating time is too long. In order to overcome this drawback, in this paper, the PID (Proportional-Integral-Differential) controller is proposed to speed up the responsiveness of AQM system. The controller parameters are tuned based on the determined gain and phase margins. The simulation results show that the integrated performance of the PID controller is obviously superior to that of the PI controller.

A CMOS current-mode continuous-time band-pass filter using the positive feedback Q (quality factor) - enhancement technique is presented in this paper. Q of the proposed filter can be mainly determined by the ratio of the two MOSFETs' transconductances in a Q-setting part, not by the ratio of two capacitance values similar to most of conventional band-pass filters. This filter can realize high Q value in spite of small chip area. Therefore, when higher value of Q is needed, the proposed filter does not need large capacitor which occupies large area on an IC chip. The proposed filter spends smaller chip area than the conventional one under the condition of Q>2. The proposed circuit is simulated by Spectre to confirm its characteristics.

A new analog equalizer supporting 10Base-T central office and remote terminal (Category-3) LAN applications is developed. It provides robust 10 Mbps data transmission (10Base-T) at loop length up to 400 meters. The equalizer with high frequency gain boost capability is controlled automatically by the proposed AZC (Adaptive Zero Control) loop according to cable length. It is implemented using AMS 0.8 µm CMOS technology.