Some electromechanical devices and systems produced using MEMS fabrication processes are detailed. Two precision measurement metrologies for inspecting electromechanical products are also described. As the trend of electromechanical devices has been towards smaller and smaller sizes possessing robust mechanisms and powerful functions, micro-electric-mechanical system (MEMS) devices are becoming more the choice for meeting such requirements. Three MEMS examples are discussed in detail in this paper: CMOS compatible sensors, RF/microwave components, and packaged and integrated passive devices. The design thinking of a new free-fall sensor, which is an accelerometer and possesses a surprisingly low frequency response and broad bandwidth, is mentioned. In addition, an AVID (dvanced ibrometer/nterferometer evice) system for measuring tiny displacement as well as a Morphinscope system that has the advantage of a confocal microscope combined with a photon tunneling microscope and both developed by NTU's MEMS/NEMS group, are discussed. The excellent sensing ability of the free-fall sensor and the accuracy resolution of the two measurement systems are proved by experimental verification.

In this paper, we propose an algorithm that automatically generates the intermediate scenes using the bidirectional disparity morphing (BDM) from the parallel stereo images. The two-step search strategy is used for speeding up the computation of the bidirectional disparity map and three occluding patterns are used for smoothing the computed disparities more elaborately. Using the bidirectional disparity map, we interpolate the left and the right image to their intermediate scenes. Then we dissolve two interpolated images into the desired intermediate scene which the holes are removed and the effect of the disparity estimation errors is minimized. We implemented the proposed algorithm on TM1300 supported by TriMedia using pSOSytem which enables to do multiprocessing. As a result, we can interpolate the high-quality intermediate scenes with real-time process.

We investigate the design of an interpolation filter of a multi-frequency time division multiple access (MF-TDMA) demodulator which is applied to digital video broadcasting-return channel system via satellite (DVB-RCS). We propose two interpolation filters for symbol timing recovery in a digital receiver where the input analog to digital conversion sampling clock is not synchronized to the transmitter symbol clock. The two proposed interpolation filters are designed by the least mean-square-error at the output of the receiver. Simulation results show that a performance improvement is achieved by employing the proposed interpolation filter.

Sliding contact behavior is important in the mechanism of collecting current. In this study, the effect of ambient gas including an inert gas on surface film formation and on the contact voltage drop was examined, changing the atmosphere from low pressure to atmospheric pressure. Furthermore, the sliding surface state was observed using SEM, EDX and XPS analyzers after the test operation. As a result, at the sliding contact in an inert gaseous environment (nitrogen and argon), it was confirmed that the contact voltage drop tends to increase. However, it was clarified that any chemically generated surface film is difficult to detect in the inert gas environment by qualitative analysis. On the basis of these results, we suggest the existence of physically adsorbed surface film. The relationship between inert gases and sliding contact phenomena is discussed.

The c-Secure CRT code is a collusion-secure fingerprinting code whose code length is reduced by using the Chinese Remainder Theorem. The tracing algorithm for the c-secure CRT code drops its performance of traitor tracing when random errors are added to the codewords. In this paper, we show two approaches to enhance random-error-resilience to the tracing algorithm of the c-secure CRT code. The first approach is introducing thresholds for the distinction of the detected part of the embedded data called detected blocks. We propose a method to derive appropriate values of the thresholds on an assumption that the tracer can estimate the random error rate. This modification extends the capability of traitor tracing to the attacks in which the alteration rate of the detected blocks is not fixed to 0.5. The second approach is extending the scope of the search for the detected blocks. With numerical results by computer simulations, we confirmed an impressive improvement of random-error-resilience of a c-secure CRT code.

Fingerprinting is one of the digital watermarking techniques, and is becoming more important as a copyright protection technique. Fingerprinting must resist collusion attacks. As a security index, "c-secureness" has been proposed, but it has been known that there is indeed no c-secure code. In this paper, we introduce a new index to measure the resilience of fingerprinting for collusion attacks and obtain some upper bounds and a lower bound on the index.

Reconfigurable architectures have been focused for its potential on achieving high performance by reconfiguring special purpose circuits for a target application and its flexibility due to its ability of reconfiguring. We have set our sights on use of a reconfigurable architecture as a general-purpose computer by extending the advantageous properties of the architecture. To achieve the goal, a generalized execution model for reconfigurable architecture is required, so we have proposed an Ideal PARallel Structure (I-PARS) execution model. In the I-PARS execution model, any programs based on its model has no restriction depending on hardware structures based on a specific reconfigurable processor, which makes it easier to develop software. Further, we have proposed a PARS architecture which executes programs based on the I-PARS execution model effectively. The PARS architecture has a large reconfigurable part for highly parallel execution, which utilizes parallelism described on the I-PARS execution model. For effective utilization of the reconfigurable part in the PARS architecture, it has an ability to reconfigure and execute operations simultaneously in one cycle. Further, the PARS architecture supports branch operations to introduce control flow in an execution on the architecture, which makes it possible to skip an execution which does not produce a valid result. In this paper, we introduce the detailed structure of an implemented prototype processor based on the PARS architecture. In the implementation, 420,377 CMOS transistors were used, which was only 3.8% of the number of transistors used in the UltraSPARC-III in logic circuits. Additionally, we evaluated the performance of the prototype processor by using some benchmark programs. From the evaluation results, we found that the prototype processor could achieve nearly the same performance and be implemented with extremely the less number of transistors compared with UltraSPARC-III 750MHz.

The OFDM technique has recently received considerable attention in the fields of wireless LAN communication systems. It is accompanied with many practical issues and one major issue is synchronization. In this letter, we propose a frequency offset estimation technique for OFDM system. The proposed frequency offset estimator employing interpolation technique in the frequency domain has a simple structure and good performance.

An 8-bit 200 MS/s CMOS 2-stage cascaded folding/interpolating ADC chip was implemented by applying a resistor averaging/interpolating scheme at the preamplifier outputs and the differential circuits for the encoder logic block, with a 0.35-µm double-poly CMOS process. The number of preamplifiers was reduced to half by using an averaging technique with a resistor array at the preamplifier outputs. The delay time of digital encoder block was reduced from 2.2 ns to 1.3 ns by replacing the standard CMOS logic with DCVSPG and CPL differential circuits. The measured SFDR was 42.5 dB at the sampling rate of 200 MS/s for the 10.072 MHz sinusoidal input signal.

A wavelet-based vector quantization scheme for image compression is introduced here. The proposed scheme obtains a better compression efficiency by the following three methods. (1) Utilizing the correlation among wavelet coefficients. (2) Placing different emphasis on wavelet coefficients at different levels. (3) Preserving the most important information of the image. In our experiments, simulation results show that this technique outperforms the recent SMVQ-ABC [1] and WTC-NIVQ [2] techniques.

In this paper, we propose a corpus-based lip-sync algorithm for natural face animation. For this purpose, we constructed a Korean audio-visual (AV) corpus. Based on this AV corpus, we propose a concatenation method of AV units, which is similar to a corpus-based text-to-speech system. For our AV corpus, lip-related parameters were extracted from every video-recorded facial shot which of speaker reads the given texts selected from newspapers. The spoken utterances were labeled with HTK and such prosodic information as duration, pitch and intensity was extracted as lip-sync parameters. Based on the constructed AV corpus, basic synthetic units are set by CVC-syllable units. For the best concatenation performance, based on the phonetic environment distance and the prosodic distance, the best path is estimated by a general Viterbi search algorithm. From the computer simulation results, we found that the information concerned with not only duration but also pitch and intensity is useful to enhance the lip-sync performance. And the reconstructed lip parameters have almost equal values to those of the original parameters.

A 3D display using super high-density multi-view images should enable reproduction of natural stereoscopic views. In the super multi-view display system, viewpoints are sampled at an interval narrower than the diameter of the pupil of a person's eye. With the parallax produced by a single eye, this system can pull out the accommodation of an eye to an object image. We are now working on a real-time view-interpolation system for the super multi-view 3D display. A multi-view camera using convergence capturing to prevent resolution degradation captures multi-view images of an object. Most of the data processing is used for view interpolation and rectification. View interpolation is done using a high-speed image-processing board with digital-signal-processor (DSP) chips or single instruction stream and multiple data streams (SIMD) parallel processor chips. Adaptive filtering of the epipolar plane images (EPIs) is used for the view-interpolation algorithm. The multi-view images are adaptively interpolated using the most suitable filters for the EPIs. Rectification, a preprocess, converts the multi-view images in convergence capturing into the ones in parallel capturing. The use of rectified multi-view images improves the processing speed by limiting the interpolation processing in EPI.

A numerical model of thin-film transistors for circuit simulation has been developed. This model utilizes three schemes. First, the spline interpolation with transformation by y=x+log(x) achieves excellent preciseness for both on-current and off-current simultaneously. Second, the square polynomial supplement solves an anomaly near the points where drain voltage equal to zero. Third, the linear extrapolation achieves continuities of the current and its derivatives as a function of voltages out of the area where the spline interpolation is performed, and improves convergence during circuit simulation.

Due to saturable nature of gain or absorption of Er doped fiber, a dynamic grating is formed by standing wave produced by interference between two laser beams traveling in opposite directions in the fiber. In this letter, we propose a variable optical filter using the dynamic grating in Er doped fiber controlled by synthesis of optical coherence function. Simulations and experimental verifications are also shown.

This paper provides a M+1-st price auction scheme using homomorphic encryption and the mix and match technique; it offers secrecy of bidding price and public verifiability. Our scheme has low round communication complexity: 1 round from each bidder to auctioneer in bidding and log p rounds from auctioneer to trusted authority in opening when prices are selected from p prefixed choices.

In this paper, we propose a floorplanning method for VLSI building block layout. The proposed method produces a floorplan under the timing constraint for a given netlist. To evaluate the wiring delay, the proposed method estimates the global routing cost for each net with buffer insertion and wire sizing. The slicing structure is adopted to represent a floorplan, and the Elmore delay model is used to estimate the wiring delay. The proposed method is based on simulated annealing. To shorten the computation time, a table look-up method is adopted to calculate the wiring delay. Experimental results show that the proposed algorithm performs well for producing satisfactory floorplans for industrial data.

The sequence-pair was proposed as a representation method of block placement to determine the densest possible placement of rectangular modules in VLSI layout design. A method of achieving bottom left corner packing in O(n2) time based on a given sequence-pair of n rectangles was proposed using horizontal/vertical constraint graphs. Also, a method of determining packing from a sequence-pair in O(n log n) time was proposed. Another method of obtaining packing in O(n log log n) time was recently proposed, but further improvement was still required. In this paper, we propose a method of obtaining packing via the Q-sequence (representation of rectangular dissection) in O(n+k) time from a given sequence-pair of n rectangles with k subsequences called adjacent crosses, given the position of adjacent crosses and the insertion order of dummy modules into adjacent crosses. The position of adjacent crosses and insertion order of dummy modules can be obtained from a sequence-pair in O(n+k) time using the conventional method. Here, we prove that arbitrary packing can be represented by a sequence-pair, keeping the value of k not more than n-3. Therefore, we can determine packing from a sequence-pair with k of O(n) in linear time using the proposed method and the conventional method.

As a design flow for low-power FPGA implementation, Datapath-Layout-Driven Design (DLDD) has been proposed. This letter reports the effect of DLDD for standard-cell-based ASIC implementation, and proposes necessary improvements. Experimental results shows that about 8.3% reduction of power dissipation is achieved in the best case.

This paper describes special-purpose hardware for large-scale logic simulation, called SP2, which executes an event driven algorithm and can simulate up to sixteen million gates. SP2 was developed, in 1992, for system verification of large-scale computer designs as a successor to SP1, which was developed in 1987. SP2 provides enhanced performance, throughput, and delay accuracy over SP1. Since 1992, SP2 has been widely used for system-level simulation of mainframes, super computers, UNIX servers and microprocessors. It is used as a powerful simulator, in all stages of design verification, or in early stages, before regression testing, by using emulators.

A method to characterise the wall voltage distribution in a three-electrode AC PDP cell is discussed. The method makes use of a firing voltage loop in a two-dimensional voltage plane. From this "fingerprint," data on the relative wall voltages as well as on the non-uniformity of the wall voltages can be inferred. The properties of the loop are explained using a simple numerical model based on field line tracing. The fingerprint method is applied to analyse ramp waveforms on the scan and data electrode of a surface discharge PDP. Many features of the measurements can be understood in terms of uniform wall voltage distributions on the dielectrics covering the electrodes. A more detailed analysis, however, shows that considerable wall voltage non-uniformities can exist, which play an important role in the firing behaviour of the cell.