We have developed a novel downlink packet scheduling scheme for a multiuser OFDMA system in which a subchannel can be time-multiplexed among multiple users. This scheme which is called Matrixed-based Proportional Fairness can provide a high system throughput while ensuring fairness. The scheme is based on a Proportional Fairness (PF) utility function and can be applied to any of the PF-based schedulers. Our scheduler explores multichannel multiuser diversity by using a two-dimensional matrix combining user selection, subchannel assignment, and time slot allocation. Furthermore, unlike other PF-based schemes, our scheme considers finitely backlogged queues during the time slot allocation. By doing so, it can exploit multichannel multiuser diversity to utilize bandwidth efficiently and with throughput fairness. Additionally, fairness in the time domain is enhanced by limiting the number of allocated time slots. Intensive simulations considering finitely backlogged queues and user mobility prove the scheme's effectiveness.

This paper discusses the discourse understanding process in spoken dialogue systems. This process enables a system to understand user utterances from the context of a dialogue. Ambiguity in user utterances caused by multiple speech recognition hypotheses and parsing results sometimes makes it difficult for a system to decide on a single interpretation of a user intention. As a solution, the idea of retaining possible interpretations as multiple dialogue states and resolving the ambiguity using succeeding user utterances has been proposed. Although this approach has proven to improve discourse understanding accuracy, carefully created hand-crafted rules are necessary in order to accurately rank the dialogue states. This paper proposes automatically ranking multiple dialogue states using statistical information obtained from dialogue corpora. The experimental results in the train ticket reservation and weather information service domains show that the statistical information can significantly improve the ranking accuracy of dialogue states as well as the slot accuracy and the concept error rate of the top-ranked dialogue states.

In order to incorporate the reader/writers (RWs) into mobile electronic devices, miniaturization and flexibility are required. To meet these requirements, we fabricate an ultra-small RW with multiple contactless interfaces by mounting main unit circuits inside the antenna coil and using flexible multi-layer circuit board.

Modular multiplication is the most dominant arithmetic operation in elliptic curve cryptography (ECC), that is a type of public-key cryptography. Montgomery multiplier is commonly used to compute the modular multiplications and requires scalability because the bit length of operands varies depending on its security level. In addition, ECC is performed in GF(P) or GF(2n), and unified architecture for multipliers in GF(P) and GF(2n) is required. However, in previous works, changing frequency is necessary to deal with delay-time difference between GF(P) and GF(2n) multipliers because the critical path of the GF(P) multiplier is longer. This paper proposes unified dual-radix architecture for scalable Montgomery multiplications in GF(P) and GF(2n). This proposed architecture unifies four parallel radix-216 multipliers in GF(P) and a radix-264 multiplier in GF(2n) into a single unit. Applying lower radix to GF(P) multiplier shortens its critical path and makes it possible to compute the operands in the two fields using the same multiplier at the same frequency so that clock dividers to deal with the delay-time difference are not required. Moreover, parallel architecture in GF(P) reduces the clock cycles increased by dual-radix approach. Consequently, the proposed architecture achieves to compute a GF(P) 256-bit Montgomery multiplication in 0.28 µs. The implementation result shows that the area of the proposal is almost the same as that of previous works: 39 kgates.

In this paper, we propose a novel image projection technique for face recognition applications based on Fisher Linear Discriminant Analysis (LDA). The projection is performed through a couple subspace analysis for overcoming the "small sample size" problem. Also, weighted pairwise discriminant hyperplanes are used in order to provide a more accurate discriminant decision than that produced by the conventional LDA. The proposed technique has been successfully tested on three face databases. Experimental results indicate that the proposed algorithm outperforms the conventional algorithms.

Recently, SCTP is attracting attention to support mobility in the Internet because it does not require additional equipment such as the Home Agent of Mobile IP. This paper focuses on an SCTP fast handover mechanism using a single interface because it is assumed that small mobile devices have a single interface per communication medium such as IEEE802.11b due to hardware limitations. The proposed mechanism called SCTPmx employs a cross layer control information exchange system called LIES to predict handover. LIES was originally designed to achieve network layer fast handover and then it was extended by adding the network layer primitives for efficient interaction among the link layer, the network layer, and the transport layer. Prior to handover, SCTPmx can generate a new address that will be used after handover and can execute duplicate address detection of IPv6. SCTPmx can suppress the delay caused by channel scanning at the link layer by employing selective background scanning mechanism which allows to continue data communication during channel scanning. In addition, SCTPmx can notify the correspondent node of the new address before handover. SCTPmx was implemented on FreeBSD. SCTPmx achieved better than 25 times lower handover latency (100 msec) and 2 times higher throughput than previous proposals.

The novel SCR-based (silicon controlled rectifier) device for ESD power clamp is presented in this paper. The proposed device has a high holding voltage and a high triggering current characteristic. These characteristics enable latch-up immune normal operation as well as superior full chip ESD protection. The device has a small area in requirement robustness in comparison to ggNMOS (gate grounded NMOS). The proposed ESD protection device is designed in 0.25 µm and 0.5 µm CMOS Technology. In the experimental result, the proposed ESD clamp has a double trigger characteristic, a high holding voltage of 4 V and a high trigger current of above 350 mA. The robustness has measured to HBM 8 kV (HBM: Human Body Model) and MM 400 V (MM: Machine Model). The proposed device has a high level It2 of 52 mA/ µm approximately.

This letter presents a new quadrature voltage-controlled oscillator (QVCO) consisting of two n-core Colpitts voltage-controlled oscillators (VCOs) with a tail inductor. The VCOs are used as a single-ended injected injection-locked frequency divider (ILFD). The output of the tail inductor in one ILFD is injected into the injection node in the other ILFD and vice versa. The proposed QVCO has been implemented in the 0.18 µm CMOS technology. At the supply voltage of 1.0 V, the power consumption is 1.8 mW. The free-running frequency is tunable from 4.68 GHz to 5.03 GHz as the tuning voltage is varied from 0.0 V to 1.8 V. The measured phase noise is -113.58 dBc/Hz at the 1 MHz frequency offset from the oscillation frequency of 5.03 GHz and the figure of merit (FOM) of the QVCO is -185.06 dBc/Hz.

In this paper, we focus on resource allocation schemes for minimizing the energy consumption of subscriber stations (SSs) in uplink flows of the IEEE 802.16 OFDMA systems. The resource allocation schemes assign subcarriers, powers, and data rates to each SS based on the measured signal to noise ratio (SNR) of the uplink channel and predefined modulation and coding scheme as system parameters. Previous research efforts to optimize resource allocation focus on the rate and throughput maximizations, and develop suboptimal heuristic algorithms. However, this paper intends to reduce the energy consumption of SSs by considering the relationship between energy efficiency and resource allocation. In order to clearly formulate the relationship, we use the Multiple Choice Knapsack (MCK) problem, which is proved to be an NP-hard problem. We propose two heuristic schemes to solve the NP-hard problem, which adaptively use the modulation and coding scheme, defined in the IEEE 802.16 OFDMA systems to minimize the required transmission power of each SS. Our simulation results show that the proposed schemes can reduce the energy consumption by up to 53% compared to the channel state information (CSI) scheme, which determines the modulation and coding level only considering the channel state information.

This work describes a 12-bit 100 MS/s 0.13 µm CMOS ADC for 3G wireless communication systems such as two-carrier W-CDMA applications. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient gate-bootstrapped sampling switches of the input SHA maintain high signal linearity over the Nyquist rate even at a 1.0 V supply. The cascode compensation using a low-impedance feedback path in two-stage amplifiers of the SHA and MDACs achieves the required conversion speed and phase margin with less power consumption and area compared to the Miller compensation. A low-glitch dynamic latch in the sub-ranging flash ADCs reduces kickback noise referred to the input of comparator by isolating the pre-amplifier from the regeneration latch output. The proposed on-chip current and voltage references are based on triple negative TC circuits. The prototype ADC in a 0.13 µm 1P8M CMOS technology demonstrates the measured DNL and INL within 0.38LSB and 0.96LSB at 12-bit, respectively. The ADC shows a maximum SNDR and SFDR of 64.5 dB and 78.0 dB at 100 MS/s, respectively. The ADC with an active die area of 1.22 mm2 consumes 42.0 mW at 100 MS/s and a 1.2 V supply, corresponding to a figure-of-merit of 0.31 pJ/conversion-step.

Silent data corruptions, which are induced by latent sector errors, phantom writes, DMA parity errors and so on, can be detected by explicitly issuing a read command to a disk controller and comparing the corresponding data with their checksums. Because some of the data stored in a storage system may not be accessed for a long time, there is a high chance of silent data corruption occurring undetected, resulting in data loss. Therefore, periodic checking of the entire data in a storage system, known as data scrubbing, is essential to detect such silent data corruptions in time. The errors detected by data scrubbing will be recovered by the replica or the redundant information maintained to protect against permanent data loss. The longer the period between data scrubbings, the higher the probability of a permanent data loss. This paper proposes a Markov failure and repair model to conservatively analyze the effect of data scrubbing on the reliability of a storage system. We show the relationship between the period of a data scrubbing operation and the number of data replicas to manage the reliability of a storage system by using the proposed model.

In this paper, we propose a new approach to rotation invariant texture analysis. This method uses the Radon transform with some considerations in direction estimation of textural images. Furthermore, it utilizes the information obtained from the number of peaks in the variance array of the Radon transform as a realty feature. The textural features are then generated after rotation of texture along principle direction. Also, to eliminating the introduced error due to rotation of texture, a simple technique is presented. Experimental results on a set of images from the Brodatz album show a good performance achieved by the proposed method in comparison with some recent texture analysis methods.

PCA-SIFT is an extension to SIFT which aims to reduce SIFT's high dimensionality (128 dimensions) by applying PCA to the gradient image patches. However PCA is not a discriminative representation for recognition due to its global feature nature and unsupervised algorithm. In addition, linear methods such as PCA and ICA can fail in the case of non-linearity. In this paper, we propose a new discriminative method called Supervised Kernel ICA (SKICA) that uses a non-linear kernel approach combined with Supervised ICA-based local image descriptors. Our approach blends the advantages of supervised learning with nonlinear properties of kernels. Using five different test data sets we show that the SKICA descriptors produce better object recognition performance than other related approaches with the same dimensionality. The SKICA-based representation has local sensitivity, non-linear independence and high class separability providing an effective method for local image descriptors.

In this paper, we study an opportunistic scheduling and adaptive modulation scheme for a wireless network with an XOR network coding scheme, which results in a cross-layer problem for MAC and physical layers. A similar problem was studied in [2] which considered an idealized system with the Shannon capacity. They showed that it may not be optimal for a relay node to encode all possible native packets and there exists the optimal subset of native packets that depends on the channel condition at the receiver node of each native packet. In this paper, we consider a more realistic model than that of [2] with a practical modulation scheme such as M-PSK. We show that the optimal policy is to encode native as many native packets as possible in the network coding group into a coded packet regardless of the channel condition at the receiver node for each native packet, which is a different conclusion from that of [2]. However, we show that adaptive modulation, in which the constellation size of a coded packet is adjusted based on the channel condition of each receiver node, provides a higher throughput than fixed modulation, in which its constellation size is always fixed regardless of the channel condition at each receiver node.

In this study we introduce AdjScales, a method for scaling similar adjectives by their strength. It combines existing Web-based computational linguistic techniques in order to automatically differentiate between similar adjectives that describe the same property by strength. Though this kind of information is rarely present in most of the lexical resources and dictionaries, it may be useful for language learners that try to distinguish between similar words. Additionally, learners might gain from a simple visualization of these differences using unidimensional scales. The method is evaluated by comparison with annotation on a subset of adjectives from WordNet by four native English speakers. It is also compared against two non-native speakers of English. The collected annotation is an interesting resource in its own right. This work is a first step toward automatic differentiation of meaning between similar words for language learners. AdjScales can be useful for lexical resource enhancement.

IEEE 802.11 MAC protocol for medium access control in wireless Local Area Networks (LANs) is the de facto standard for wireless ad hoc networks. However, it does not perform well in terms of fairness, delay and throughput specially, in multihop networks. The problem is due to both the MAC and link layer contentions. Many research papers have been published in these fields. Among them, a modification of IEEE 802.11 MAC protocol was proposed to achieve per-node fairness, but modifications to the original MAC layer requires a change of hardware, therefore, it is difficult to implement. Moreover, it fails to solve the per-flow unfairness problem. In this paper, we propose a new scheduling method, Probabilistic Control on Round robin Queue (PCRQ) scheduling, aiming to achieve per-flow fairness in multihop ad hoc networks. PCRQ scheduling in the link layer is proposed without modifying IEEE 802.11 MAC protocol. Our proposed method achieves good performance results in both UDP and TCP traffic.

In this paper, we consider a problem of assigning n independent tasks onto m identical processors in such a way that the overall execution time of the tasks will be minimized. Unlike conventional task assignment problem, we assume that the execution time of each task is not fixed in advance, and merely upper and lower bounds of the execution time are given at the compile time. In the following, we first provide a theoretical analysis of several conventional scheduling policies in terms of the worst case slowdown compared with the outcome of an optimal off-line scheduling policy. It is shown that the best known algorithm in the literature achieves a worst case performance ratio of 1 + 1/f(n) where f(n) = O(n2/3) for any fixed m, which approaches to one by increasing n to the infinity. We then propose a new scheme that achieves better worst case ratio of 1 + 1/g(n) where g(n) = Θ (n/log n) for any fixed m, which approaches to one more quickly than previous schemes.

We first consider a variant of the Schmidt-Samoa-Takagi encryption scheme without losing additively homomorphic properties. We show that this variant is secure in the sense of IND-CPA under the decisional composite residuosity assumption, and of OW-CPA under the assumption on the hardness of factoring n=p2q. Second, we introduce new algebraic properties "affine" and "pre-image restriction," which are closely related to homomorphicity. Intuitively, "affine" is a tuple of functions which have a special homomorphic property, and "pre-image restriction" is a function which can restrict the receiver to having information on the encrypted message. Then, we propose an encryption scheme with primitive power roots of unity in (Z/ns+1). We show that our scheme has, in addition to the additively homomorphic property, the above algebraic properties. In addition to the properties, we also show that the encryption scheme is secure in the sense of OW-CPA and IND-CPA under new number theoretic assumptions.

The line-based method has been one of the most commonly-used methods of hardware implementation of two-dimensional (2D) discrete wavelet transform (DWT). However, data buffer is required between the row DWT processor and the column DWT processor to solve the data flow mismatch, which increases the on-chip memory size and the output latency. Since the incompatible data flow is induced from the intrinsic property of adopted lifting-based algorithm, a decomposed lifting algorithm (DLA) is presented by rearranging the data path of lifting steps to ensure that image data is processed in raster scan manner in row processor and column processor. Theoretical analysis indicates that the precision issue of DLA outperforms other lifting-based algorithms in terms of round-off noise and internal word-length. A memory-efficient and high-performance line-based architecture is proposed based on DLA without the implementation of data buffer. For an N M image, only 2N internal memory is required for 5/3 filter and 4N of that is required for 9/7 filter to perform 2D DWT, where N and M indicate the width and height of an image. Compared with related 2D DWT architectures, the size of on-chip memory is reduced significantly under the same arithmetic cost, memory bandwidth and timing constraint. This design was implemented in SMIC 0.18 µm CMOS logic fabrication with 32 kbits dual-port RAM and 20 K equivalent 2-input NAND gates in a 1.00 mm 1.00 mm die, which can process 512 512 image under 100 MHz.

Shamir's (k,n)-threshold secret sharing scheme (threshold scheme) has two problems: a heavy computational cost is required to make shares and recover the secret, and a large storage capacity is needed to retain all the shares. As a solution to the heavy computational cost problem, several fast threshold schemes have been proposed. On the other hand, threshold ramp secret sharing schemes (ramp scheme) have been proposed in order to reduce each bit-size of shares in Shamir's scheme. However, there is no fast ramp scheme which has both low computational cost and low storage requirements. This paper proposes a new (k,L,n)-threshold ramp secret sharing scheme which uses just EXCLUSIVE-OR(XOR) operations to make shares and recover the secret at a low computational cost. Moreover, by proving that the fast (k,n)-threshold scheme in conjunction with a method to reduce the number of random numbers is an ideal secret sharing scheme, we show that our fast ramp scheme is able to reduce each bit-size of shares by allowing some degradation of security similar to the existing ramp schemes based on Shamir's threshold scheme.