Due to the advancement of software radio and RF technology, cognitive radio(CR) has become an enabling technology to realize dynamic spectrum access through its spectrum sensing and reconfiguration capability. Robust and reliable spectrum sensing is a key factor to discover spectrum opportunity. Single cognitive radios often fail to provide such reliable information because of their inherent sensitivity limitation. Primary signals that are subject to detection by cognitive radios may become weak due to several factors such as fading and shadowing. One approach to overcome this problem is to perform spectrum sensing by using multiple CRs or multiple spectrum sensors. This approach is known as distributed sensing because sensing is carried out through cooperation of spatially distributed sensors. In distributed sensing, sensors should perform spectrum sensing and forward the result to a destination where data fusion is carried out. Depending on the channel conditions between sensors (sensor-to-sensor channel) and between the sensor and the radio (user-channel), we explore different spectrum sensing algorithms where sensors provide the sensing information either cooperatively or independently. Moreover we investigate sensing schemes based on soft information combining (SC), hard information combining (HC). Finally we propose a two-stage detection scheme that uses both SC and HC. The newly proposed detection scheme is shown to provide improved performance compared to sensing based on either HC or SC alone. Computer simulation results are provided to illustrate the performances of the different sensing algorithms.

A voltage-controlled oscillator (VCO) tolerant to process variations at lower supply voltage was proposed. The circuit consists of an on-chip threshold-voltage-monitoring circuit, a current-source circuit, a body- biasing control circuit, and the delay cells of the VCO. Because variations in low-voltage VCO frequency are mainly determined by that of the current in delay cells, a current-compensation technique was adopted by using an on-chip threshold-voltage-monitoring circuit and body-biasing circuit techniques. Monte Carlo SPICE simulations demonstrated that variations in the oscillation frequency by using the proposed techniques were able to be suppressed about 65% at a 1-V supply voltage, compared to frequencies with and without the techniques.

Partial forwarding is a design method to place forwarding paths on a part of processor pipeline. Hardware cost of processor can be reduced without performance loss by partial forwarding. However, compiler with the instruction scheduler which considers partial forwarding structure of the target processor is required since conventional scheduling algorithm cannot make the most of partial forwarding structure. In this paper, we propose a heuristic instruction scheduling method for processors with partial forwarding structure. The proposed algorithm uses available distance to schedule instructions which are suitable for the target partial forwarding processor. Experimental results show that the proposed method generates near-optimal solutions in practical time and some of the optimized codes for partial forwarding processor run in the shortest time among the target processors. It also shows that the proposed method is superior to hazard detection unit.

Scalable video coding (SVC) was standardized as an extension of H.264/AVC by the JVT (Joint Video Team) in Nov. 2007. The biggest feature of SVC is multi-layered coding where two or more video sequences are compressed into a single bit-stream. This letter proposes a fast block mode decision algorithm in spatial enhancement layer of SVC. The proposed algorithm achieves early decision by limiting the number of candidate modes for block with certain characteristic called same motion vector block (SMVB). Our proposed method reduces the complexity, in terms of encoding time by up to 66.17%. Nevertheless, it shows negligible PSNR degradation by only up to 0.16 dB and increases the bit-rate by only up to 0.64%, respectively.

In deep-submicron technology, several state-of-the-art architectural synthesis flows have already adopted the distributed register architecture to cope with the increasing wire delay by allowing multicycle communication. In this article, we regard communication synthesis targeting a refined regular distributed register architecture, named RDR-GRS, as a problem of simultaneous data transfer routing and scheduling for global interconnect resource minimization. We also present an innovative algorithm with regard of both spatial and temporal perspectives. It features both a concentration-oriented path router gathering wire-sharable data transfers and a channel-based time scheduler resolving contentions for wires in a channel, which are in spatial and temporal domain, respectively. The experimental results show that the proposed algorithm can significantly outperform existing related works.

The researches on predicting and removing of lithographic hot-spots have been prevalent in recent semiconductor industries, and known to be one of the most difficult challenges to achieve high quality detection coverage. To provide physical design implementation with designer's favors on fixing hot-spots, in this paper, we present a noble and accurate hot-spot detection method, so-called "leveling and scoring" algorithm based on weighted combination of image quality parameters (i.e., normalized image log-slope (NILS), mask error enhancement factor (MEEF), and depth of focus (DOF)) from lithography simulation. In our algorithm, firstly, hot-spot scoring function considering severity level is calibrated with process window qualification, and then least-square regression method is used to calibrate weighting coefficients for each image quality parameter. In this way, after we obtain the scoring function with wafer results, our method can be applied to future designs of using the same process. Using this calibrated scoring function, we can successfully generate fixing guidance and rule to detect hot-spot area by locating edge bias value which leads to a hot-spot-free score level. Finally, we integrate the hot-spot fixing guidance information into layout editor to facilitate the user-favorable design environment. Applying our method to memory devices of 60 nm node and below, we could successfully attain sufficient process window margin to yield high mass production.

Adjustment of a certain parameter in the course of performing a trajectory task such as drawing or gesturing is a common manipulation in pen-based interaction. Since pen tip information is confined to x-y coordinate data, such concurrent parameter adjustment is not easily accomplished in devices using only a pen tip. This paper comparatively investigates the performance of inherent pen input modalities (Pressure, Tilt, Azimuth, and Rolling) and Key Pressing with the non-preferred hand used for precision parameter manipulation during pen sliding actions. We elaborate our experimental design framework here and conduct experimentation to evaluate the effect of the five techniques. Results show that Pressure enabled the fastest performance along with the lowest error rate, while Azimuth exhibited the worst performance. Tilt showed slightly faster performance and achieved a lower error rate than Rolling. However, Rolling achieved the most significant learning effect on Selection Time and was favored over Tilt in subjective evaluations. Our experimental results afford a general understanding of the performance of inherent pen input modalities in the course of a trajectory task in HCI (human computer interaction).

In this paper, we propose a bandwidth-scalable stereo audio coding method based on a layered structure. The proposed stereo coding method encodes super-wideband (SWB) stereo signals and is able to decode either wideband (WB) stereo signals or SWB stereo signals, depending on the network congestion. The performance of the proposed stereo coding method is then compared with that of a conventional stereo coding method that separately decodes WB or SWB stereo signals, in terms of subjective quality, algorithmic delay, and computational complexity. Experimental results show that when stereo audio signals sampled at a rate of 32 kHz are compressed to 64 kbit/s, the proposed method provides significantly better audio quality with a 64-sample shorter algorithmic delay, and comparable computational complexity.

A scan chain is one of the most important testing techniques, but it can be used as side-channel attacks against a cryptography LSI. We focus on scan-based attacks, in which scan chains are targeted for side-channel attacks. The conventional scan-based attacks only consider the scan chain composed of only the registers in a cryptography circuit. However, a cryptography LSI usually uses many circuits such as memories, micro processors and other circuits. This means that the conventional attacks cannot be applied to the practical scan chain composed of various types of registers. In this paper, a scan-based attack which enables to decipher the secret key in an AES cryptography LSI composed of an AES circuit and other circuits is proposed. By focusing on bit pattern of the specific register and monitoring its change, our scan-based attack eliminates the influence of registers included in other circuits than AES. Our attack does not depend on scan chain architecture, and it can decipher practical AES cryptography LSIs.

An improved nonlinear circuit model for a GaAs Gunn diode in an oscillator is proposed based on the physical mechanism of the diode. This model interprets the nonlinear harmonic character on the Gunn diode. Its equivalent nonlinear circuit of which can assist in the design of the Gunn oscillator and help in the analysis of the fundamental and harmonic characteristics of the GaAs Gunn diode. The simulation prediction and the experiment of the Gunn oscillator show the feasibility of the nonlinear circuit model for the GaAs Gunn oscillator.

We report Ultraviolet (UV)-induced visible light luminescence in artificial-lattice thin films of ion-doped silica glass (silica superstructure thin films). The film was composed of periodic nanometer layers of germanium-doped silica (Ge:SiO2), titanium-doped silica (Ti:SiO2), and tin-doped silica (Sn:SiO2). The thickness of each layer was between 10 and 30 nm. Despite the small thickness of the film (few microns), a relatively bright luminescence of white light was observed, along with cathode-ray luminescence in the superstructure film. In addition, irradiation of the superstructure film with UV light led to light amplification by stimulated emission at 405 nm. The experimental results suggest the potential application of silica superstructure thin films as optical amplifiers.

This paper presents a wide tuning range VCO with an automatic frequency, gain, and two-step amplitude calibration loop for Digital TV (DTV) tuner applications. To cover the wide tuning range, the fully digital automatic frequency calibration (AFC) loop is used. In addition to the AFC loop, a two-step negative-Gm tuning loop is proposed to provide the optimum negative-Gm to the LC tank in a wide frequency range with a fine resolution. In the coarse negative-Gm tuning loop, the number of active negative-Gm cells is selected digitally based on the target frequency. In the fine negative-Gm tuning loop, the negative-Gm is tuned finely with the bias voltage of the VCO. Also, the digital VCO gain calibration scheme is proposed to compensate for the gain variation in a wide tuning range. The VCO tuning range is 2.6 GHz, from 1.7 GHz to 4.3 GHz, and the power consumption is 2 mA to 4 mA from a 1.8 V supply. The measured VCO phase noise is -120 dBc/Hz at 1 MHz offset.

Electrical characteristics of P3HT/Aluminum organic/ inorganic heterojunction diodes were investigated V-I and capacitance-voltage (C-V) measurements. The V-I measurement exhibited current rectification inherent in the Schottky diode, suggesting their availabilities as rectification diodes in organic flexible circuits. C-V analysis indicated the fact that the depletion layer was generated in the P3HT film in the reversed bias condition. The flat band voltage analysis suggested that the interfacial charge affected the built-in potential of the diodes. Al/P3HT heterojunction is possible to be used as not only the rectification diodes but also gate junctions for junction type field effect or static induction transistors.

This paper presents a novel X-handling technique, which removes the effect of unknowns on compacted test response with maximal compaction ratio. The proposed method combines with the current X-tolerant compactors and inserts masking cells on scan paths to selectively mask X's. By doing this, the number of unknown responses in each scan-out cycle could be reduced to a reasonable level such that the target X-tolerant compactor would tolerate with guaranteed possible error detection. It guarantees no test loss due to the effect of X's, and achieves the maximal compaction that the target response compactor could provide as well. Moreover, because the masking cells are only inserted on the scan paths, it has no performance degradation of the designs. Experimental results demonstrate the effectiveness of the proposed method.

Recently, many researchers tackle accurate object recognition algorithms and many algorithms are proposed. However, these algorithms have some problems caused by variety of real environments such as a direction change of the object or its shading change. The new tracking algorithm, Cascade Particle Filter, is proposed to fill such demands in real environments by constructing the object model while tracking the objects. We have been investigating to implement accurate object recognition on embedded systems in real-time. In order to apply the Cascade Particle Filter to embedded applications such as surveillance, automotives, and robotics, a hardware accelerator is indispensable because of limitations in power consumption. In this paper we propose a hardware implementation of the Discrete AdaBoost algorithm that is the most computationally intensive part of the Cascade Particle Filter. To implement the proposed hardware, we use PICO Express, a high level synthesis tool provided by Synfora, for rapid prototyping. Implementation result shows that the synthesized hardware has 1,132,038 transistors and the die area is 2,195 µm 1,985 µm under a 0.180 µm library. The simulation result shows that total processing time is about 8.2 milliseconds at 65 MHz operation frequency.

Delay Tolerant Networks (DTNs) are able to provide communication services in challenged networks where the end-to-end path between the source and destination does not exist. In order to increase the probability of message delivery, DTN routing mechanisms require nodes in the network to store and carry messages in their local buffer and to replicate many copies. When the limited buffer is consumed, choosing appropriate messages to discard is critical to maximizing the system performance. Current approaches for this are sub-optimal or assumed unrealistic conditions. In this paper, we propose an optimal buffer management scheme for the realistic situations where the bandwidth is limited and messages vary in size. In our scheme, we design a message discard policy that maximizes the message delivery rate. Simulation results demonstrate the efficiency of our proposal.

We carried out degradation analysis of a blue phosphorescent organic light emitting diode by both impedance spectroscopy and transient electroluminescence (EL) spectroscopy. The number of semicircles observed in the Cole-Cole plot of the modulus became three to two after the device was operated for 567 hours. Considering the effective layer thickness of the initial and degraded devices did not change by degradation and combining the analysis of the Bode-plot of the imaginary part of the modulus, the relaxation times of emission layer and hole-blocking with electron transport layers changed to nearly the same value by the increase of the resistance of emission layer. Decay time of transient EL of the initial device was coincident with that of the degraded one. These phenomena suggest that no phosphorescence quenching sites are generated in the degraded device, but the number of the emission sites decrease by degradation.

Secure operating systems (secure OSes) are widely used to limit the damage caused by unauthorized access to Internet servers. However, writing a security policy based on the principle of least privilege for a secure OS is a challenge for an administrator. Considering that remote attackers can never attack a server before they establish connections to it, we propose a novel scheme that exploits phases to simplify security policy descriptions for Internet servers. In our scheme, the entire system has two execution phases: an initialization phase and a protocol processing phase. The initialization phase is defined as the phase before the server establishes connections to its clients, and the protocol processing phase is defined as the phase after it establishes connections. The key observation is that access control should be enforced by the secure OS only in the protocol processing phase to defend against remote attacks. Since remote attacks cannot be launched in the initialization phase, a secure OS is not required to enforce access control in this phase. Thus, we can omit the access-control policy in the initialization phase, which effectively reduces the number of policy rules. To prove the effectiveness of our scheme, we wrote security policies for three kinds of Internet servers (HTTP, SMTP, and POP servers). Our experimental results demonstrate that our scheme effectively reduces the number of descriptions; it eliminates 47.2%, 27.5%, and 24.0% of policy rules for HTTP, SMTP, and POP servers, respectively, compared with an existing SELinux policy that includes the initialization of the server.

In this paper, we propose a scheme of frequency sub-band allocation to obtain maximum throughput in an orthogonal frequency division multiple access (OFDMA) system where each user has a finite number of packets to transmit, which are generated from packet calls with arbitrary size and arbitrary arrival rate. The proposed scheme is evaluated in terms of throughput and user fairness in comparison with the proportional fairness (PF) scheme and the Greedy scheme under the finite queue length condition. Numerical results show that the proposed scheme is superior to the Greedy scheme in terms of both throughput and fairness for finite queue length.

Using frictional force microscopy (FFM), the friction surface characteristics were compared between twisted nematic (TN) mode and vertical alignment (VA) mode alignment films (AFs). The friction asymmetry was detected depending on temperature conditions on TN mode AF, but not on VA mode AF. The difference between two modes was explained by leaning intermolecular repulsion caused by the pre-tilt angle uniformity and the density of side chain. No level difference according to temperature conditions appeared when the pre-tilt angle were measured after liquid crystal (LC) injection.