Dynamic Framed Slotted ALOHA (DFSA) is one of the most popular protocols to resolve tag collisions in RFID systems. In DFSA, it is widely known that the optimal performance is achieved when the frame size is equal to the number of tags. So, a reader dynamically adjusts the next frame size according to the current number of tags. Thus it is important to estimate the number of tags exactly. In this paper, we propose a novel tag estimation and identification method using litmus (test) slots for DFSA. We compare the performance of the proposed method with those of existing methods by analysis. We conduct simulations and show that our scheme improves the speed of tag identification.

This paper presents a novel method for improving the readability of automatic speech recognition (ASR) results for classroom lectures. Because speech in a classroom is spontaneous and contains many ill-formed utterances with various disfluencies, the ASR result should be edited to improve the readability before presenting it to users, by applying some operations such as removing disfluencies, determining sentence boundaries, inserting punctuation marks and repairing dropped words. Owing to the presence of many kinds of domain-dependent words and casual styles, even state-of-the-art recognizers can only achieve a 30-50% word error rate for speech in classroom lectures. Therefore, a method for improving the readability of ASR results is needed to make it robust to recognition errors. We can use multiple hypotheses instead of the single-best hypothesis as a method to achieve a robust response to recognition errors. However, if the multiple hypotheses are represented by a lattice (or a confusion network), it is difficult to utilize sentence-level knowledge, such as chunking and dependency parsing, which are imperative for determining the discourse structure and therefore imperative for improving readability. In this paper, we propose a novel algorithm that infers clean, readable transcripts from spontaneous multiple hypotheses represented by a confusion network while integrating sentence-level knowledge. Automatic and manual evaluations showed that using multiple hypotheses and sentence-level knowledge is effective to improve the readability of ASR results, while preserving the understandability.

Hypercomplex polar Fourier analysis treats a signal as a vector field and generalizes the conventional polar Fourier analysis. It can handle signals represented by hypercomplex numbers such as color images. Hypercomplex polar Fourier analysis is reversible that means it can reconstruct image. Its coefficient has rotation invariance property that can be used for feature extraction. However in order to increase the computation speed, fast algorithm is needed especially for image processing applications like realtime systems and limited resource platforms. This paper presents fast hypercomplex polar Fourier analysis based on symmetric properties and mathematical properties of trigonometric functions. Proposed fast hypercomplex polar Fourier analysis computes symmetric points simultaneously, which significantly reduce the computation time.

This work studies the benefits of heterogeneous cellular networks with overlapping picocells in a large macrocell. We consider three different strategies for resource allocation and cell association. The first model employs a spectrum overlapping strategy with an SINR-based cell association. The second model avoids the interference between macrocell and picocell through a spectrum splitting strategy. Furthermore, picocell range expansion is also considered in this strategy to enable a load balancing between the macrocell and picocells. The last model is a hybrid one, called as fractional spectrum splitting strategy, where spectrum splitting strategy is only applied at the picocell-edge, while the picocell-inner reuses the spectrum of the macrocell. We constructs resource allocation optimization problem for these strategies to maximize the system rate. Our results show that in terms of system rate, all the three strategies outperform the performance of macrocell-only case, which shows the benefit of heterogeneous networks. Moreover, fractional spectrum splitting strategy provides highest system rate at the expense of outage user rate degradation due to inter-macro-pico interference. Spectrum overlapping model provides the second highest system rate gain and also improves outage user rate owing to full spectrum reuse and the benefit of macro diversity, while spectrum splitting model achieves a moderate system rate gain.

Keith Salvin presented a key exchange protocol using matrices in the general linear group, GL(r,Zn), where n is the product of two distinct large primes. The system is fully specified in the US patent number 7346162 issued in 2008. In the patent claims, it is argued that the best way to break this system is to factor n. Furthermore, for efficiency reasons, it is suggested to use r=2. In this letter, we show that this cryptosystem can be easily broken by solving a set of consistent homogeneous r2 linear equations in 2r unknowns over Zn.

of late, many researchers have been interested in sparse representation of signals and its applications such as Compressive Sensing in Cognitive Radio (CR) networks as a way of overcoming the issue of limited bandwidth. Compressive sensing based wideband spectrum sensing is a novel approach in cognitive radio systems. Also in these systems, using spatial-frequency opportunistic reuse is emerged interestingly by constructing and deploying spatial-frequency Power Spectral Density (PSD) maps. Since the CR sensors are distributed in the region of support, the sensed PSD by each sensor should be transmitted to a master node (base-station) in order to construct the PSD maps in space and frequency domains. When the number of sensors is large, this data transmission which is required for construction of PSD map can be challenging. In this paper, in order to transmit the CR sensors' data to the master node, the compressive sensing based scheme is used. Therefore, the measurements are sampled in a lower sampling rate than of the Nyquist rate. By using the proposed method, an acceptable PSD map for cognitive radio purposes can be achieved by only 30% of full data transmission. Also, simulation results show the robustness of the proposed method against the channel variations in comparison with classical methods. Different solution schemes such as Basis Pursuit, Lasso, Lars and Orthogonal Matching Pursuit are used and the quality performance of them is evaluated by several simulation results over a Rician channel with respect to several different compression and Signal to Noise Ratios. It is also illustrated that the performance of Basis Pursuit and Lasso methods outperform the other compression methods particularly in higher compression rates.

A small-sized leakage-controlled gated sense amplifier (SA) and relevant circuits are proposed for 0.5-V multi-gigabit DRAM arrays. The proposed SA consists of a high-VT PMOS amplifier and a low-VT NMOS amplifier which is composed of high-VT NMOSs and a low-VT cross-coupled NMOS, and achieves 46% area reduction compared to a conventional SA with a low-VT CMOS preamplifier. Separation of the proposed SA and a data-line pair achieves a sensing time of 6 ns and a writing time of 0.6 ns. Momentarily overdriving the PMOS amplifier achieves a restoring time of 13 ns. The gate level control of the high-VT NMOSs and the gate level compensation circuit for PVT variations reduce the leakage current of the proposed SA to 2% of that without the control, and its effectiveness was confirmed using a 50-nm test chip.

No nontrivial optimal sets of frequency-hopping sequences (FHSs) of period 2(2n-1) for a positive integer n ≥ 2 have been found so far, when their frequency set sizes are less than their periods. In this paper, systematic doubling methods to construct new FHS sets are presented under the constraint that the set of frequencies has size less than or equal to 2n. First, optimal FHS sets with respect to the Peng-Fan bound are constructed when frequency set size is either 2n-1 or 2n. And then, near-optimal FHS sets with frequency set size 2n-1 are designed by applying the Chinese Remainder Theorem to Sidel'nikov sequences, whose FHSs are optimal with respect to the Lempel-Greenberger bound. Finally, a general construction is given for near-optimal FHS sets whose frequency set size is less than 2n-1. Our constructions give new parameters not covered in the literature, which are summarized in Table1.

Fidelity Range Extension (FRExt) (i.e. High Profile) was added to the H.264/AVC recommendation in the second version. One of the features included in FRExt is the Adaptive Block-size Transform (ABT). In order to conform to the FRExt, a Fractional Motion Estimation (FME) architecture is proposed to support the 88/44 adaptive Hadamard Transform (88/44 AHT). The 88/44 AHT circuit contributes to higher throughput and encoding performance. In order to increase the utilization of SATD (Sum of Absolute Transformed Difference) Generator (SG) in unit time, the proposed architecture employs two 8-pel interpolators (IP) to time-share one SG. These two IPs can work in turn to provide the available data continuously to the SG, which increases the data throughput and significantly reduces the cycles that are needed to process one Macroblock. Furthermore, this architecture also exploits the linear feature of Hadamard Transform to generate the quarter-pel SATD. This method could help to shorten the long datapath in the second-step of two-iteration FME algorithm. Finally, experimental results show that this architecture could be used in the applications requiring different performances by adjusting the supported modes and operation frequency. It can support the real-time encoding of the seven-mode 4 K2 K@24 fps or six-mode 4 K2 K@30 fps video sequences.

Three types of electron injection scheme: both side injection scheme and self-repair one side injection scheme Type A (injection for once) and Type B (injection for twice) are proposed and analyzed comprehensively for 65 nm technology node 6T- and 8T-SRAM cells to find the optimum injection scheme and cell architecture. It is found that the read speed degrades by as much as 6.3 times in the 6T-SRAM with the local injected electrons. However, the read speed of the 8T-SRAM cell does not degrade because the read port is separated from the write pass gate transistors. Furthermore, the self-repair one side injection scheme is most suitable to solve the conflict of the half select disturb and write characteristics. The worst cell characteristics of Type A and Type B self-repair one side injection schemes were found to be the same. In the self-repair one side injection 8T-SRAM, the disturb margin increases by 141% without write margin or read speed degradation. The proposed schemes have no process or area penalty compared with the standard CMOS-process.

Hybrid wired/wireless on-chip network is a promising communication architecture for multi-/many-core SoC. For application-specific SoC design, it is important to design a dedicated on-chip network architecture according to the application-specific nature. In this paper, we propose a heuristic wireless link allocation algorithm for creating hybrid on-chip network architecture. The algorithm can eliminate the performance bottleneck by replacing multi-hop wired paths by high-bandwidth single-hop long-range wireless links. The simulation results show that the hybrid on-chip network designed by our algorithm improves the performance in terms of both communication delay and energy consumption significantly.

In this paper, we propose a synthesis method for asynchronous circuits with bundled-data implementation. The proposed method iteratively applies behavioral synthesis and floorplanning to obtain a near optimum circuit in the term of latency under given design constraints. To improve latency, behavioral synthesis and floorplanning are carried out so that the delay of the control circuit is minimized and the addition of delay elements to satisfy timing constraints is minimized. We evaluate the effectiveness of the proposed method in terms of latency, area, and the number of timing violations while synthesizing several benchmarks. Experimental results show that the proposed method synthesizes faster circuits compared to the circuit synthesized without the proposed method. Also, the proposed method is effective to reduce the number of timing violations.

Feature selection (FS) plays an important role in pattern recognition and machine learning. FS is applied to dimensionality reduction and its purpose is to select a subset of the original features of a data set which is rich in the most useful information. Most existing FS methods based on rough set theory focus on dependency function, which is based on lower approximation as for evaluating the goodness of a feature subset. However, by determining only information from a positive region but neglecting a boundary region, most relevant information could be invisible. This paper, the maximal lower approximation (Max-Certainty) – minimal boundary region (Min-Uncertainty) criterion, focuses on feature selection methods based on rough set and mutual information which use different values among the lower approximation information and the information contained in the boundary region. The use of this idea can result in higher predictive accuracy than those obtained using the measure based on the positive region (certainty region) alone. This demonstrates that much valuable information can be extracted by using this idea. Experimental results are illustrated for discrete, continuous, and microarray data and compared with other FS methods in terms of subset size and classification accuracy.

Based on our previous work, this work presents a complete method for time-domain processing of frequency-domain data with evenly-spaced frequency indices, together with its application. The proposed method can be used to calculate the cross spectral and power spectral densities for the frequency indices of interest. A promising application for the time-domain processing of frequency-domain data, particularly for calculating the summation of frequency-domain cross- and auto-correlations in orthogonal frequency-division multiplexing (OFDM) systems, is studied. The advantages of the time-domain processing of frequency-domain data are 1) the ability to rapidly acquire the properties that are readily available in the frequency domain and 2) the reduced complexity. The proposed fast algorithm directly employs time-domain samples, and hence, does not need the fast Fourier transform (FFT) operation. The proposed algorithm has a lower complexity (required complex multiplications ∼ O(N)) than conventional techniques.

A gated sense amplifier (GSA) consisting of a low-Vt gated preamplifier (LGA) and a high-Vt sense amplifier (SA) is proposed. The gating scheme of the LGA enables quick amplification of an initial cell signal voltage (vS0) because of its low Vt and prevents the cell signal from degrading due to interference noise between data lines. As for a conventional sense amplifier (CSA), this new type of noise causes sensing error, and the noise-generation mechanism was clarified for the first time by analysis of vS0. The high-Vt SA holds the amplified signal and keeps subthreshold current low. Moreover, the gating scheme of the low-Vt MOSFETs in the LGA drives the I/O line quickly. The GSA thus simultaneously achieves fast sensing, low-leakage data holding, and fast I/O driving, even for sub-1-V mid-point sensing. The GSA is promising for future sub-1-V gigabit dynamic random-access memory (DRAM) because of reduced variations in the threshold voltage of MOSFETs; thus, the offset voltage of the LGA is reduced. The effectiveness of the GSA was verified with a 70-nm 512-Mbit DRAM chip. It demonstrated row access time (tRCD) of 16.4 ns and read access (tAA) of 14.3 ns at array voltage of 0.9 V.

Reversible color component transforms derived by the LU factorization are briefly described. It is possible to obtain an reversible implementation to a given component transform, even if the original transform is irreversible. Some examples are presented and their performances are compared in image compression.

Along with the miniaturization of CMOS-LSIs, control methods for LSIs have been extensively developed. The most predominant method is to digitize observed values as early as possible and to use digital control. Thus, many types of analog-to-digital converters (ADCs) have been developed such as temperature, time, delay, and frequency converters. ADCs are the easiest circuits into which digital correction methods can be introduced because their outputs are digital. Various types of calibration method have been developed, which has markedly improved the figure of merits by alleviating margins for device variations. The above calibration and correction methods not only overcome a circuit's weak points but also give us the chance to develop quite new circuit topologies and systems. In this paper, several digital calibration and correction methods for major analog-to-digital converters are described, such as pipelined ADCs, delta-sigma ADCs, and successive approximation ADCs.

Program comprehension using dynamic information is one of key tasks of software maintenance. Software visualization with sequence diagrams is a promising technique to help developer comprehend the behavior of object-oriented systems effectively. There are many tools that can support automatic generation of a sequence diagram from execution traces. However it is still difficult to understand the behavior because the size of automatically generated sequence diagrams from the massive amounts of execution traces tends to be beyond developer's capacity. In this paper, we propose an execution trace slicing and visualization method. Our proposed method is capable of slice calculation based on a behavior model which can treat dependencies based on static and dynamic analysis and supports for various programs including exceptions and multi-threading. We also introduce our tool that perform our proposed slice calculation on the Eclipse platform. We show the applicability of our proposed method by applying the tool to two Java programs as case studies. As a result, we confirm effectiveness of our proposed method for understanding the behavior of object-oriented systems.

It is shown that it is feasible to apply 0.5-V 6-T SRAM cells in a 25-nm high-speed 1-Gb e-SRAM. In particular, for coping with rapidly reduced voltage margin as VDD is reduced, a boosted word-voltage scheme is first proposed. Second, Vt variations are reduced with repair techniques and nanoscale FD-MOSFETs to further widen the voltage margin. Third, a worst case design is developed, for the first time, to evaluate the cell. This design features a dynamic margin analysis and takes subthreshold current, temperature, and Vt variations and their combination in the cell into account. Fourth, the proposed scheme is evaluated by applying the worst-case design and a 25-nm planar FD-SOI MOSFET. It is consequently found that the scheme provides a wide margin and high speed even at 0.5 V. A 0.5-V high-speed 25-nm 1-Gb SRAM is thus feasible. Finally, to further improve the scheme, it is shown that it is necessary to use FinFETs and suppress and compensate process, voltage, and temperature variations in a chip and wafer.

In a wireless multi-hop network between a source node (S) and a destination node (D), multipath routing in which S redundantly sends the same packets to D through multiple routes at the same time is effective for enhancing the reliability of the wireless data transmission by means of route diversity. However, when applying the multipath routing to a factory where huge robots are moving around, if closer multiple routes are selected, the probability that they are blocked by the robots at the same time becomes higher, so the reliability in terms of packet loss rate cannot be enhanced. In this paper, we propose a multipath routing method which can select physically distant multiple routes without any knowledge on the locations of nodes. We introduce a single metric composed of “the distance between routes” and “the route quality” by means of scalarization in multi-objective maximization problem and apply a genetic algorithm (GA) for searching for adequate routes which maximize the metric. Computer simulation results show that the proposed method can adaptively control the topologies of selected routes between S and D, and effectively reduce the packet loss rates.