This paper proposes a write resistance tracking circuit (WRTC) to improve the memory window of HfOx-based resistive memory. With a 50-ns single voltage pulse, the minimal resistance of the high resistance state in the 1-kb array of resistive switching elements can increase from 25 kΩ to 65 kΩ by using the proposed verify circuit. The WRTC uses the transition current detection method based on the feedback of the memory cell to control the write driver. The WRTC achieves distinct bistable resistance states, avoids the occurrence of over-RESET, and enhances the memory window of the RRAM cell.

This paper presents a system for automatic generation of dancing animation that is synchronized with a piece of music by re-using motion capture data. Basically, the dancing motion is synthesized according to the rhythm and intensity features of music. For this purpose, we propose a novel meta motion graph structure to embed the necessary features including both rhythm and intensity, which is constructed on the motion capture database beforehand. In this paper, we consider two scenarios for non-streaming music and streaming music, where global search and local search are required respectively. In the case of the former, once a piece of music is input, the efficient dynamic programming algorithm can be employed to globally search a best path in the meta motion graph, where an objective function is properly designed by measuring the quality of beat synchronization, intensity matching, and motion smoothness. In the case of the latter, the input music is stored in a buffer in a streaming mode, then an efficient search method is presented for a certain amount of music data (called a segment) in the buffer with the same objective function, resulting in a segment-based search approach. For streaming applications, we define an additional property in the above meta motion graph to deal with the unpredictable future music, which guarantees that there is some motion to match the unknown remaining music. A user study with totally 60 subjects demonstrates that our system outperforms the stat-of-the-art techniques in both scenarios. Furthermore, our system improves the synthesis speed greatly (maximal speedup is more than 500 times), which is essential for mobile applications. We have implemented our system on commercially available smart phones and confirmed that it works well on these mobile phones.

This paper presents a possibility of Electromagnetic (EM) analysis against cryptographic modules outside their security boundaries. The mechanism behind the information leakage is explained from the view point of Electromagnetic Compatibility: electric fluctuation released from cryptographic modules can conduct to peripheral circuits based on ground bounce, resulting in radiation. We demonstrate the consequence of the mechanism through experiments where the ISO/IEC standard block cipher AES (Advanced Encryption Standard) is implemented on an FPGA board and EM radiations from power and communication cables are measured. Correlation Electromagnetic Analysis (CEMA) is conducted in order to evaluate the information leakage. The experimental results show that secret keys are revealed even though there are various disturbing factors such as voltage regulators and AC/DC converters between the target module and the measurement points. We also discuss information-suppression techniques as electrical-level countermeasures against such CEMAs.

High performance, low area multipliers are highly desired for modern and future DSP systems due to the increasing demand of high speed DSP applications. In this paper, we present an efficient architecture for an LUT-based truncated multiplier and its application in RGB to YCbCr color space conversion which can be used for digital TV, image and video processing systems. By employing an improved split LUT-based architecture and LUT optimization method, the proposed multiplier can reduce the value of area-delay product by up to 52% compared with other constant multiplier methods. The FPGA implementation of a color space conversion application employing the proposed multiplier also results in significant reduction of area-delay product of up to 48%.

In 2009, Wang et al. proposed an efficient and secure dynamic ID-based remote user authentication scheme based on the one-way secure hash function. This letter demonstrates that Wang et al.'s scheme is still vulnerable to impersonation attacks.

This paper presents a new type of electromagnetic interference (EMI) measurement system. An EMI Camera LSI (EMcam) with a 124 on-chip 25050 µm2 loop antenna matrix in 65 nm CMOS is developed. EMcam achieves both the 2D electric scanning and 60 µm-level spatial precision. The down-conversion architecture increases the bandwidth of EMcam and enables the measurement of EMI spectrum up to 3.3 GHz. The shared IF-block scheme is proposed to relax both the increase of power and area penalty, which are inherent issues of the matrix measurement. The power and the area are reduced by 74% and 73%, respectively. EMI measurement with the smallest 3212 µm2 antenna to date is also demonstrated.

The RFID tag system has received a lot of attention for ubiquitous computing. An RFID tag is attached to an object. With the unique ID of the RFID tag, a user identifies the object provided with the RFID tag and derives appropriate information about the object. One important application in the RFID technology is localizing RFID tags, which can be very useful in acquiring the position information concerning the RFID tags. It can be applied to navigation systems and positional detection systems for mobile robots. This paper proposes a new adaptive multi-range-sensing method for 3D localization of passive RFID tags by using a probabilistic approach. In this method, a mobile object (human, robot, etc.) with an RFID reader estimates the positions of RFID tags with multiple communication ranges dynamically. The effectiveness of the proposed method was demonstrated in experiments.

In this paper, a low-complexity symbol-spaced turbo frequency domain equalization (FDE) algorithm based on Laurent decomposition is proposed for precoded binary continuous phase modulation (CPM) with modulation index h=1/2. At the transmitter, a precoder is utilized to eliminate the inherent memory of the CPM signal. At the receiver, a matched filter based on Laurent decomposition is utilized to make the detection symbol-spaced. As a result, the symbol-spaced iteration can be taken between the equalizer and the decoder directly without a CPM demodulator, and we derive a symbol-spaced soft interference cancellation frequency domain equalization (SSIC-FDE) algorithm for binary CPM with h=1/2. A new data block structure for FDE of partial response CPM is also presented. The computational complexity analysis and simulations show that this approach provides a complexity reduction and an impressive performance improvement over previously proposed turbo FDE algorithm for binary CPM with h=1/2 in multi-path fading channels.

We propose a fast and precise transient response and frequency characteristics simulation method for switching converters. This method uses a behavioral simulation tool without using a SPICE-like analog simulator. The nonlinear operation of the circuit is considered, and the nonlinear function is realized by defining the nonlinear formula based on the circuit operation and by applying feedback. To assess the accuracy and simulation time of the proposed simulation method, we designed current-mode buck and boost converters and fabricated them using a 0.18-µm high-voltage CMOS process. The comparison in the transient response and frequency characteristics among SPICE, the proposed program on a behavioral simulation tool which we named NSTVR (New Simulation Tool for Voltage Regulators) and experiments of fabricated IC chips showed good agreement, while NSTVR was more than 22 times faster in transient response and 85 times faster in frequency characteristics than SPICE in CPU time in a boost converter simulation.

This paper presents fundamental concepts, overall process and recent research issues of Mining Software Repositories. The data sources such as source control systems, bug tracking systems or archived communications, data types and techniques used for general MSR problems are also presented. Finally, evaluation approaches, opportunities and challenge issues are given.

In the near future, decentralized network systems consisting of a huge number of sensor nodes are expected to play an important role. In such a network, each node should control itself by means of a local interaction algorithm. Although such local interaction algorithms improve system reliability, how to design a local interaction algorithm has become an issue. In this paper, we describe a local interaction algorithm in a partial differential equation (or PDE) and propose a new design method whereby a PDE is derived from the solution we desire. The solution is considered as a pattern of nodes' control values over the network each of which is used to control the node's behavior. As a result, nodes collectively provide network functions such as clustering, collision and congestion avoidance. In this paper, we focus on a periodic pattern comprising sinusoidal waves and derive the PDE whose solution exhibits such a pattern by exploiting the Fourier method.

Chemical sensors are one of the oldest fields of research closely related to the semiconductor technology. From the Ion-Sensitive Field-Effect Transistors (ISFET) in the 70's, through Micro-Electro-Mechanical-System (MEMS) sensors from the end of the 80's, chemical sensors are combining in the 90's MEMS technology with LSI intelligence to devise more selective, sensitive and autonomous devices to analyse complex mixtures. A brief history of chemical sensors from the ISFET to the nowadays LSI integrated sensors is first detailed. Then the states-of-the-art of LSI integrated chemical sensors and their wide range of applications are discussed. Finally the authors propose a brand-new usage of integrated wireless MEMS sensors for remote surveillance of chemical substances, such as food-industry or pharmaceutical products, that are stored in closed environment like a bottle, for a long period. In such environment, in-situ analyse is necessary, and electrical cables, for energy supply or data transfer, cannot be used. Thanks to integrated MEMS, an autonomous long-term in-situ quality deterioration tracking system is possible.

Radiation integral areas are localized and reduced based upon the locality of scattering phenomena. In the high frequency, the scattering field is given by the currents, not the entire region, but on the local areas near the scattering centers, such as the stationary phase points and edge diffraction points, due to the cancelling effect of integrand in the radiation integral. The numerical calculation which this locality is implemented into has been proposed for 2-dimensional problems. The scattering field can be approximated by integrating the currents weighted by the adequate function in the local areas whose size and position are determined appropriately. Fresnel zone was previously introduced as the good criterion to determine the local areas, but the determination method was slightly different, depending on the type of scattering centers. The objective of this paper is to advance the Fresnel zone criteria in a 2-dimensional case to the next stage with enhanced generality and applicability. The Fresnel zone number is applied not directly to the actual surface but to the virtual one associated with the modified surface-normal vector satisfying the reflection law. At the same time, the argument in the weighting function is newly defined by the Fresnel zone number instead of the actual distance from the scattering centers. These two revisions bring about the following three advantages; the uniform treatment of various types scattering centers, the smallest area in the localization and applicability to 3-dimensional problems.

Sparse representation based classification (SRC) has emerged as a new paradigm for solving face recognition problems. Further research found that the main limitation of SRC is the assumption of pixel-accurate alignment between the test image and the training set. A. Wagner used a series of linear programs that iteratively minimize the sparsity of the registration error. In this paper, we propose another face registration method called three-point positioning method. Experiments show that our proposed method achieves better performance.

Recently, the 3-D vertical Floating Gate (FG) type NAND cell arrays with the Sidewall Control Gate (SCG), such as ESCG, DC-SF and S-SCG, are receiving attention to overcome the reliability issues of Charge Trap (CT) type device. Using this novel cell structure, highly reliable flash cell operations were successfully implemented without interference effect on the FG type cell. However, the 3-D vertical FG type cell has large cell size by about 60% for the cylindrical FG structure. In this point of view, we intensively investigate the scalability of the FG width of the 3-D vertical FG NAND cells. In case of the planar FG type NAND cell, the FG height cannot be scaled down due to the necessity of obtaining sufficient coupling ratio and high program speed. In contrast, for the 3-D vertical FG NAND with SCG, the FG is formed cylindrically, which is fully covered with surrounded CG, and very high CG coupling ratio can be achieved. As results, the scaling of FG width of the 3-D vertical FG NAND cell with S-SCG can be successfully demonstrated at 10 nm regime, which is almost the same as the CT layer of recent BE-SONOS NAND.

Although the Tunnel Field-Effect Transistor (TFET) is a promising device for ultra-low power CMOS technology due to the ability to reduce power supply voltage and very small off-current, there have been few reports on the control of VT for TFETs. Unfortunately, the TFET needs a different technique to adjust VT than the MOSFET by channel doping because most of TFETs are fabricated on SOI substrates. In this paper, we propose a technique to control VT of the TFET by putting an additional VT-control doping region (VDR) between source and channel. We examine how much VT is changed by doping concentration of VDR. The change of doping concentration modulates VT because it changes the semiconductor work function difference, ψs,channel-ψs,source, at off-state. Also, the effect of the size of VDR is investigated. The region can be confined to the silicon surface because most of tunneling occurs at the surface. At the same time, we study the optimum width of this region while considering the mobility degradation by doping. Finally, the effect of the SOI thickness on the VDR adjusted VT of TFET is also investigated.

Applying Distributed Video Coding (DVC) to mobile devices that have limited computation and power resources can be a very challenging problem due to its high-complexity decoding. To address this, this paper proposes a DVC bitstream organizer. The proposed DVC bitstream organizer reduces the complexity associated with repetitive channel decoding and SI generation in a flexible manner. It allows users to choose a means of minimizing the computational complexity of the DVC decoder according to their preferences and the device's resource limitations. An experiment shows that the proposed method increases decoding speeds by up to 25 times.

In this work, the effect of device dimension variation and metal wiring scheme on the RF performance of MOSFETs based on 0.13-µm RFCMOS technology has been investigated. Two sets of experiments have been carried out. In the first experiment, two types of source metal wiring options, each with various gate poly pitches, have been investigated. The results showed that the extrinsic capacitances (Cegs, Cegd) and parasitic resistances tend to increase with increasing gate poly pitch. Both cutoff frequency (fT) and maximum oscillation frequency (fmax) showed substantial degradation for the larger gate poly pitches. Based on measurement, we propose a simplified model for extrinsic parasitic capacitance as a function of gate poly pitch with different source metal wiring schemes. For the second experiment, the impact of gate metal wiring scheme and the number of gate fingers Nf on the RF performance of MOSFET has been studied. Two different types of gate metal wiring schemes, one with poly layer and the other with M2 layer, are compared. The measurement showed that the capacitance is slightly increased, while gate resistance significantly reduced, with the M2 gate wiring. As a result, fT is slightly degraded but fmax is significantly improved, especially for larger Nf, with the M2 gate wiring. The results in this work provide useful information regarding device dimension and metal wiring scheme for various RF applications of RF CMOS technology.

In this paper, we investigate the performance of Thorup's algorithm by comparing it to Dijkstra's algorithm for large-scale network simulations. One of the challenges toward the realization of large-scale network simulations is the efficient execution to find shortest paths in a graph with N vertices and M edges. The time complexity for solving a single-source shortest path (SSSP) problem with Dijkstra's algorithm with a binary heap (DIJKSTRA-BH) is O((M + N) log N). An sophisticated algorithm called Thorup's algorithm has been proposed. The original version of Thorup's algorithm (THORUP-FR) has the time complexity of O(M + N). A simplified version of Thorup's algorithm (THORUP-KL) has the time complexity of O(M α(N) + N) where α(N) is the functional inverse of the Ackerman function. In this paper, we compare the performances (i.e., execution time and memory consumption) of THORUP-KL and DIJKSTRA-BH since it is known that THORUP-FR is at least ten times slower than Dijkstra's algorithm with a Fibonaccii heap. We find that (1) THORUP-KL is almost always faster than DIJKSTRA-BH for large-scale network simulations, and (2) the performances of THORUP-KL and DIJKSTRA-BH deviate from their time complexities due to the presence of the memory cache in the microprocessor.

In this paper, we derive a simple formula to generate a wide-sense systematic generator matrix(we call it quasi-systematic) B for a Reed-Solomon code. This formula can be utilized to construct an efficient interpolation based erasure-only decoder with time complexity O(n2) and space complexity O(n). Specifically, the decoding algorithm requires 3kr + r2 - 2r field additions, kr + r2 + r field negations, 2kr + r2 - r + k field multiplications and kr + r field inversions. Compared to another interpolation based erasure-only decoding algorithm derived by D.J.J. Versfeld et al., our algorithm is much more efficient for high-rate Reed-Solomon codes.