Hu, Huang and Fan proposed a fully secure hierarchical identity-based encryption (IEICE Trans. Fundamentals, Vol.E92-A, No.6, pp.1494–1499, 2009) that achieves constant size of ciphertext and tight security reduction. Unfortunately, Park and Lee (IEICE Trans. Fundamentals, Vol.E93-A, No.6, pp.1269–1272, 2010) found that the security proof of Hu et al.'s scheme is incorrect; that is, the security of Hu et al.'s scheme cannot be reduced to their claimed q-ABDHE assumption. However, it is unclear whether Hu et al.'s scheme is still secure. In this letter, we provide an attack to show that the scheme is not secure against the chosen-plaintext attack.

This paper presents a new type of electromagnetic interference (EMI) measurement system. An EMI Camera LSI (EMcam) with a 124 on-chip 25050 µm2 loop antenna matrix in 65 nm CMOS is developed. EMcam achieves both the 2D electric scanning and 60 µm-level spatial precision. The down-conversion architecture increases the bandwidth of EMcam and enables the measurement of EMI spectrum up to 3.3 GHz. The shared IF-block scheme is proposed to relax both the increase of power and area penalty, which are inherent issues of the matrix measurement. The power and the area are reduced by 74% and 73%, respectively. EMI measurement with the smallest 3212 µm2 antenna to date is also demonstrated.

This paper presents a tutorial overview of Continuous-Time Delta-Sigma Modulators (CTDSM); their operating principles to understand what is important intuitively and architectures to achieve higher conversion efficiency and to operate low supply voltage, design methods against loop stability problem, tuning methods of the bandwidth and so on. A survey of cutting-edge CMOS implementations is described.

This paper presents a system for automatic generation of dancing animation that is synchronized with a piece of music by re-using motion capture data. Basically, the dancing motion is synthesized according to the rhythm and intensity features of music. For this purpose, we propose a novel meta motion graph structure to embed the necessary features including both rhythm and intensity, which is constructed on the motion capture database beforehand. In this paper, we consider two scenarios for non-streaming music and streaming music, where global search and local search are required respectively. In the case of the former, once a piece of music is input, the efficient dynamic programming algorithm can be employed to globally search a best path in the meta motion graph, where an objective function is properly designed by measuring the quality of beat synchronization, intensity matching, and motion smoothness. In the case of the latter, the input music is stored in a buffer in a streaming mode, then an efficient search method is presented for a certain amount of music data (called a segment) in the buffer with the same objective function, resulting in a segment-based search approach. For streaming applications, we define an additional property in the above meta motion graph to deal with the unpredictable future music, which guarantees that there is some motion to match the unknown remaining music. A user study with totally 60 subjects demonstrates that our system outperforms the stat-of-the-art techniques in both scenarios. Furthermore, our system improves the synthesis speed greatly (maximal speedup is more than 500 times), which is essential for mobile applications. We have implemented our system on commercially available smart phones and confirmed that it works well on these mobile phones.

This paper proposes a write resistance tracking circuit (WRTC) to improve the memory window of HfOx-based resistive memory. With a 50-ns single voltage pulse, the minimal resistance of the high resistance state in the 1-kb array of resistive switching elements can increase from 25 kΩ to 65 kΩ by using the proposed verify circuit. The WRTC uses the transition current detection method based on the feedback of the memory cell to control the write driver. The WRTC achieves distinct bistable resistance states, avoids the occurrence of over-RESET, and enhances the memory window of the RRAM cell.

This paper presents a possibility of Electromagnetic (EM) analysis against cryptographic modules outside their security boundaries. The mechanism behind the information leakage is explained from the view point of Electromagnetic Compatibility: electric fluctuation released from cryptographic modules can conduct to peripheral circuits based on ground bounce, resulting in radiation. We demonstrate the consequence of the mechanism through experiments where the ISO/IEC standard block cipher AES (Advanced Encryption Standard) is implemented on an FPGA board and EM radiations from power and communication cables are measured. Correlation Electromagnetic Analysis (CEMA) is conducted in order to evaluate the information leakage. The experimental results show that secret keys are revealed even though there are various disturbing factors such as voltage regulators and AC/DC converters between the target module and the measurement points. We also discuss information-suppression techniques as electrical-level countermeasures against such CEMAs.

Ultra-wideband (UWB) technology is an excellent candidate for supporting wireless personal area networks (WPANs) because of its wide bandwidth, low transmission power, low complexity and multipath immunity. We study density-aware exclusive region (ER)-based scheduling for a nonuniform UWB-WPAN. Using a generalized radius for the ER based on statistical topology, we propose a scheduling scheme that uses a radius for the ER that varies according to the density information around the destination in the nonuniform network. Computer simulations show that (i) our approach to the radius of the generalized ER provides better scheduling performance than the radius solution of the conventional work [3] and (ii) scheduling that is based on an adaptive ER radius can always outperform both the fixed ER-based scheme and the TDMA scheme with respect to network throughput.

A 4th-order programmable continuous-time filter (CTF) for hard-disk-drive (HDD) read channels was developed with 65-nm CMOS process technology. The CTF cutoff frequency and boost are programmable by switching units of the operational trans-conductance amplifier (OTA) banks and the capacitor banks. The switches are operated by lifted local-supply voltage to reduce on-resistance of the transistors. The CTF characteristics were robust against process technology variations and supply voltage and temperature ranges due to the introduction of a digitally assisted compensation scheme with analog auto-tuning circuits and digital calibration sequences. The digital calibration sequences, which fit into the operation sequence of the HDD read channel, compensate for the tuning circuits of the process technology variations, and the tuning circuits compensate for the CTF characteristics over the supply voltage and temperature ranges. As a result, the CTF had a programmability of 100–1000-MHz cutoff frequency and 0–12-dB boost.

We have developed a long-range asynchronous on-chip data-transmission link based on multiple-valued single-track signaling for a highly reliable asynchronous Network-on-Chip. In the proposed signaling, 1-bit data with control information is represented by using a one-digit multi-level signal, so serial data can be transmitted asynchronously using only a single wire. The small number of wires alleviates the routing complexity of wiring long-range interconnects. The use of current-mode signaling makes it possible to transmit data at high speed without buffers or repeaters over a long interconnect wire because of the low-voltage swing of signaling, and it leads to low-latency data transmission. We achieve a latency of 0.45 ns, a throughput of 1.25 Gbps, and energy dissipation of 0.58 pJ/bit with a 10-mm interconnect wire under a 0.13 µm CMOS technology. This represents an 85% decrease in latency, a 150% increase in throughput, and a 90% decrease in energy dissipation compared to a conventional serial asynchronous data-transmission link.

We propose a fast and precise transient response and frequency characteristics simulation method for switching converters. This method uses a behavioral simulation tool without using a SPICE-like analog simulator. The nonlinear operation of the circuit is considered, and the nonlinear function is realized by defining the nonlinear formula based on the circuit operation and by applying feedback. To assess the accuracy and simulation time of the proposed simulation method, we designed current-mode buck and boost converters and fabricated them using a 0.18-µm high-voltage CMOS process. The comparison in the transient response and frequency characteristics among SPICE, the proposed program on a behavioral simulation tool which we named NSTVR (New Simulation Tool for Voltage Regulators) and experiments of fabricated IC chips showed good agreement, while NSTVR was more than 22 times faster in transient response and 85 times faster in frequency characteristics than SPICE in CPU time in a boost converter simulation.

The performance of successive approximation register (SAR) analog-to-digital converter (ADC) is well balanced between power and speed compare to the conventional flash or pipeline architecture. The nonlinearities suffer from the CDAC mismatch and comparator offset degrades SAR ADC performance in terms of DNL and INL. An on chip histogram-based digitally assisted background calibration technique is proposed to cancel and relax the aforesaid nonlinearities. The calibration is performed using the input signal, watching the digital codes in the specified vicinity of the decision boundaries, and feeding back to control the compensation capacitor periodically. The calibration does not require special calibration signal or additional analog hardware which is simple and amenable to hardware or software implementations. A 9-bit SAR ADC with split CDAC has been implemented in a 65 nm CMOS technology and it achieves a peak SNDR of 50.81 dB and consumes 1.34 mW from a 1.2-V supply. +0.4/-0.4 LSB DNL and +0.5/-0.7 LSB INL are achieved after calibration. The ADC has input capacitance of 180 fF and occupies an area of 0.10.13 mm2.

We present a new framework of the data-reusing (DR) adaptive algorithms by incorporating a constraint on noise, referred to as a noise constraint. The motivation behind this work is that the use of the statistical knowledge of the channel noise can contribute toward improving the convergence performance of an adaptive filter in identifying a noisy linear finite impulse response (FIR) channel. By incorporating the noise constraint into the cost function of the DR adaptive algorithms, the noise constrained DR (NC-DR) adaptive algorithms are derived. Experimental results clearly indicate their superior performance over the conventional DR ones.

MISTY1 is a 64-bit block cipher that has provable security against differential and linear cryptanalysis. MISTY1 is one of the algorithms selected in the European NESSIE project, and it is recommended for Japanese e-Government ciphers by the CRYPTREC project. In this paper, we report on 12th order differentials in 3-round MISTY1 with FL functions and 44th order differentials in 4-round MISTY1 with FL functions both previously unknown. We also report that both data complexity and computational complexity of higher order differential attacks on 6-round MISTY1 with FL functions and 7-round MISTY1 with FL functions using the 46th order differential can be reduced to as much as 1/22 of the previous values by using multiple 44th order differentials simultaneously.

To improve the observability during the post-silicon validation, it is the key to select the limited trace signals effectively for the data acquisition. This paper proposes an automated trace signal selection algorithm, which uses the pruning-based strategy to reduce the exploration space. First, the restoration range is covered for each candidate signals. Second, the constraints are generated based on the conjunctive normal form (CNF) to avoid the conflict. Finally the candidates are selected through pruning-based enumeration. The experimental results indicate that the proposed algorithm can bring higher restoration ratios and is more effective compared to existing methods.

A power analysis attack is a well-known side-channel attack but the efficiency of the attack is frequently degraded by the existence of power components, irrelative to the encryption included in signals used for the attack. To enhance the performance of the power analysis attack, we propose a preprocessing method based on extracting encryption-related parts from the measured power signals. Experimental results show that the attacks with the preprocessed signals detect correct keys with much fewer signals, compared to the conventional power analysis attacks.

In this paper, a low-complexity symbol-spaced turbo frequency domain equalization (FDE) algorithm based on Laurent decomposition is proposed for precoded binary continuous phase modulation (CPM) with modulation index h=1/2. At the transmitter, a precoder is utilized to eliminate the inherent memory of the CPM signal. At the receiver, a matched filter based on Laurent decomposition is utilized to make the detection symbol-spaced. As a result, the symbol-spaced iteration can be taken between the equalizer and the decoder directly without a CPM demodulator, and we derive a symbol-spaced soft interference cancellation frequency domain equalization (SSIC-FDE) algorithm for binary CPM with h=1/2. A new data block structure for FDE of partial response CPM is also presented. The computational complexity analysis and simulations show that this approach provides a complexity reduction and an impressive performance improvement over previously proposed turbo FDE algorithm for binary CPM with h=1/2 in multi-path fading channels.

In this paper, to reduce the memory size requirements of IFFT for OFDM-based applications, we propose a new IFFT design technique based on a combined integer mapping of three IFFT input signals: modulated data, pilot and null signals. The proposed method focuses on reducing the size of memory cells in the first two stages of the single-path delay feedback (SDF) IFFT architectures since the first two stages require 75% of the total memory cells. By simulations of 2048-point IFFT design for cognitive radio systems, it is shown that the proposed IFFT design method achieves more than 13% reduction in gate count and 11% reduction in power consumption compared with conventional IFFT design.

In the work we introduce novel approach to remote sensing from space for the estimation of sea wave heights with a spaceborne high precision two-frequency radar altimeter with nadir synthesis antenna aperture. Experiments show considerable reduction of the decorrelation factor of the correlation coefficient and so significant enhancement of the sensitivity of the altimeter for the estimation for the sea wave status.

A simple DFT-based noise variance estimator for orthogonal frequency division multiplexing access (OFDMA) systems is proposed. The conventional DFT-based estimator differentiates the channel impulse response and noise in the time domain. However, for partial frequency response, its time domain signal will leak to all taps due to the windowing effect. The noise and channel leakage power become mixed. In order to accurately derive the noise power, we propose a novel symmetric extension method to reduce the channel leakage power. This method is based on the improved signal continuity at the boundaries introduced by symmetric extension. Numerical results show that the normalized mean square error (NMSE) of our proposed method is significantly lower than that of the conventional DFT method.

The RFID tag system has received a lot of attention for ubiquitous computing. An RFID tag is attached to an object. With the unique ID of the RFID tag, a user identifies the object provided with the RFID tag and derives appropriate information about the object. One important application in the RFID technology is localizing RFID tags, which can be very useful in acquiring the position information concerning the RFID tags. It can be applied to navigation systems and positional detection systems for mobile robots. This paper proposes a new adaptive multi-range-sensing method for 3D localization of passive RFID tags by using a probabilistic approach. In this method, a mobile object (human, robot, etc.) with an RFID reader estimates the positions of RFID tags with multiple communication ranges dynamically. The effectiveness of the proposed method was demonstrated in experiments.