A 9-bit 100-MS/s successive approximation register (SAR) ADC with low power and small area has been implemented in 65-nm CMOS technology. A tri-level charge redistribution technique is proposed to reduce DAC switching energy and settling time. By connecting bottom plates of differential capacitor arrays for charge sharing, extra reference voltage is avoided. Two reference voltages charging and discharging the capacitors are chosen to be supply voltage and ground in order to save energy and achieve a rail-to-rail input range. Split capacitor arrays with mismatch calibration are implemented for small area and small input capacitance without linearity degradation. The ADC achieves a peak SNDR of 53.1 dB and consumes 1.46 mW from a 1.2-V supply, resulting in a figure of merit (FOM) of 39 fJ/conversion-step. The total active area is 0.012 mm2 and the input capacitance is 180 fF.

This paper presents a gate delay estimation method that takes into account dynamic power supply noise. We review STA based on static IR-drop analysis and a conventional method for dynamic noise waveform, and reveal their limitations and problems that originate from circuit structures and higher delay sensitivity to voltage in advanced technologies. We then propose a gate delay computation that overcomes the problems with iterative computations and consideration of input voltage drop. Evaluation results with various circuits and noise injection timings show that the proposed method estimates path delay fluctuation well within 1% error on average.

In renewable power generators, because of high initial cost and duty cycle of systems, efficiency parameter has an important place. For this reason, line frequency controlled multilevel inverters are one of most proper choices for renewable power converters. Among these, diode-clamped multilevel inverter structures are one of most important and best efficient inverters. In this paper, a simple diode-clamped equivalent circuit for exploring the efficiency under resistive loads is proposed, and based on this simple circuit, the on-state power dissipation in improved and original diode-clamped multilevel inverter under resistive loads is analyzed. Then, comparative efficiency equations are extracted for inverters that use metal oxide semiconductor field-effect transistors (MOSFETs) and other p-n junction as switches. These equations enable us to have a better idea of conducting power dissipation in diode-clamped and help us to choose appropriate switches for having a lower on-state power dissipation. Some cases are studied and in the end it is proven that the calculated efficiency under resistive load is a boundary for inductive load with the same impedance in diode-clamped inverter with p-n junction switches. This means that calculating the efficiency under resistive loads enables us to approximately predict efficiency under inductive loads.

Scan-based side-channel attacks retrieve a secret key in a cryptography circuit by analyzing scanned data. Since they must be considerable threats to a cryptosystem LSI, we have to protect cryptography circuits from them. RSA is one of the most important cryptography algorithms because it effectively realizes a public-key cryptography system. RSA is extensively used but conventional scan-based side-channel attacks cannot be applied to it because it has a complicated algorithm. This paper proposes a scan-based side-channel attack which enables us to retrieve a secret key in an RSA circuit. The proposed method is based on detecting intermediate values calculated in an RSA circuit. We focus on a 1-bit time-sequence which is specific to some intermediate values. By monitoring the 1-bit time-sequence in the scan path, we can find out the register position specific to the intermediate value and we can know whether this intermediate value is calculated or not in the target RSA circuit. We can retrieve a secret key one-bit by one-bit from MSB to LSB. The experimental results demonstrate that a 1,024-bit secret key used in the target RSA circuit can be retrieved using 30.2 input messages within 98.3 seconds and its 2,048-bit secret key can be retrieved using 34.4 input within 634.0 seconds.

A dual-mode pulse-triggered flip-flop design supporting functional versatility is presented. A low-complexity unified logic module, consisting of only five transistors, for dual-mode pulse generation is devised using pass transistor logic (PTL). Potential threshold voltage loss problem is successfully resolved to ensure the signal integrity. Despite the extra logic for dual-mode operations, the circuit complexity of the proposed design is comparable to those of the single mode designs. Simulations in different process corners and switching activities prove the competitive performance of proposed design against various single mode designs.

This paper proposes a prioritized aggregation method that supports compressed video transmission on millimeter wave wireless personal area network (mmWave WPAN) systems. Frame aggregation is an effective means to improve system efficiency and throughput for wide band systems such as mmWave WPAN. It is required by the applications that the mmWave WPAN systems should provide Gbps or multiGbps transmission capability. The proposed scheme targets not only transmission efficiency but also support of compressed video transmission which currently is very popular. The proposal combines MAC layer aggregation with PHY layer skew modulation to facilitate the video transmission in a way that more important data is better protected. Simulation results show that the average peak signal to noise ratio (PSNR) performance is improved by 5 dB compared to conventional method, while the Gbps transmission requirement is fulfilled.

A mobile ad-hoc network (MANET) consists of a collection of wireless mobile nodes without any fixed network infrastructure. Since the mobile nodes form a constantly changing topology, the design of efficient and scalable routing protocols is a fundamental challenge in MANETs. In the current literature, position-based routing protocols are regarded as having better scalability and lower control overhead than topology-based routing protocols. Since location services are the most critical part of position-based routing protocols, we present a multi-home-region scheme, Distributed Virtual Home Region with Spatial Awareness (DVHR-SA), to improve the performance of location service in this paper. Our scheme adaptively selects different update and query procedures according to the location of a source node. The simulation results show that DVHR-SA shortens the lengths of the update, query and reply paths. Our scheme also reduces the overall network message overhead. Therefore, DVHR-SA is considerably fast and stable.

A design methodology of Random Switching Logic (RSL) using CMOS standard cell libraries is proposed to counter power analysis attacks against cryptographic hardware modules. The original RSL proposed in 2004 requires a unique RSL-gate for random data masking and glitch suppression to prevent secret information leakage through power traces. In contrast, our new methodology enables to use general logic gates supported by standard cell libraries. In order to evaluate its practical performance in hardware size and speed as well as resistance against power analysis attacks, an AES circuit with the RSL technique was implemented as a cryptographic LSI using 130-nm and 90-nm CMOS standard cell library. From the results of attack experiments that used a million traces, we confirmed that the RSL-AES circuit has very high DPA and CPA resistance thanks to the contributions of both the masking function and the glitch suppressing function.

Distributed networks employing collaborative transmission (CT) from remote antennas can provide improved system capacity and cell-edge performance, by using appropriate transmission strategies. When compared to conventional non-collaborative transmission (NCT) from one base station (BS), we show that CT from two adjacent BSs can be beneficial in terms of the capacity, even when the transmission rate is normalized by the number of collaborating BSs. We further demonstrate that performing adaptive transmission (AT) between NCT and CT based on the instantaneous channel conditions provide an additional gain in capacity. The exact amount of achievable gain is quantified by the closed-form formula for the capacity distribution, which is derived using the Jacobian transformation. The presented distribution is immediately applicable to 6-sectored distributed cellular network, for which we present numerical verification of the results.

The biggest challenge in multi-cell MIMO multiplexing systems is how to effectively suppress the other-cell interference (OCI) since the OCI severely decrease the system performance. Cooperation among cells is one of the most promising solutions to OCI problems. However, this solution suffers greatly from delay and overhead issues, which make it impractical. A coordinated MIMO system with a simplified cooperation between the base stations is a compromise between the theory and practice. We aim to devise an effective resource allocation algorithm based on a coordinated MIMO system that largely alleviates the OCI. In this paper, we propose a joint resource allocation algorithm incorporating intra-cell beamforming multiplexing and inter-cell interference suppression, which adaptively allocates the transmitting power and schedules users while achieving close to an optimal system throughput under proportional fairness consideration. We formulate this problem as a nonlinear combinational optimization problem, which is hard to solve. Then, we decouple the variables and transform it into a problem with convex sub-problems that can be solve but still need heavy computational complexity. In order to implement the algorithm in real-time scenarios, we reduce the computational complexity by assuming an equal power allocation utility to do user scheduling before the power allocation. Extensive simulation results show that the joint resource allocation algorithm can achieve a higher throughput and better fairness than the traditional method while maintains the proportional fairness. Moreover, the low-complexity algorithm obtains a better fairness and less computational complexity with only a slight loss in throughput.

We edit in this paper several archives on the research and development in the field of microwave circuit technology in Japan, that originated with the invention of Yagi-Uda antenna in 1925, together with generally unknown historical topics in the period from the 1920s up until the end of World War II. As the main subject, we investigate the origin and evolution of the Multiply Split-Anode Magnetron, and clarify that the basic magnetron technology had been established until 1939 under the direction of Yoji Ito in cooperation of expert engineers between the Naval Technical Institute (NTI) and the Nihon Musen Co., while the Cavity Magnetron was invented by Shigeru Nakajima of the Nihon Musen Co. in May 1939, and further that physical theory of the Multiply Split-Anode Cavity Magnetron Oscillation and the design theory of the Cavity Magnetron were established in collaboration between the world-known physicists and the expert engineers at the NTI Shimada Laboratory in the wartime. In addition, we clarify that Sin-itiro Tomonaga presented the Scattering Matrix representation of Microwave Circuits, and others. The development mentioned above was carried out, in strict secrecy, in an unusual wartime situation up until 1945.

This paper presents a voltage reference that utilizes the virtually diode-connected MOS transistors, biased in the weak-inversion region. The proposed architecture increases the gain of the feedback loop that consequently reduces the system sensitivity, and hence improves the PSRR. The circuit is designed and simulated in a standard 0.18 µm CMOS technology. The simulation results in HSPICE indicate the successful operation of the circuit as follows: the PSRR at DC frequency is 86 dB and for the temperature range from -55C to 125C, the variation of the output reference voltage is less than 66 ppm/C.

This paper investigates primary signal detection by using a quiet period (QP) in cognitive wireless communications. In particular, we provide an analytical model for studying the impact of QPs on the system performance. Our analysis shows that two successive QPs have a significant impact on system performance. Moreover, the analytical results obtained reveal an optimum period of two successive QPs that maximize system performance.

This paper introduces a cycle-accurate Simulator for a dynamically REconfigurable MUlti-media System, called SimREMUS. SimREMUS can either be used at transaction-level, which allows the modeling and simulation of higher-level hardware and embedded software, or at register transfer level, if the dynamic system behavior is desired to be observed at signal level. Trade-offs among a set of criteria that are frequently used to characterize the design of a reconfigurable computing system, such as granularity, programmability, configurability as well as architecture of processing elements and route modules etc., can be quickly evaluated. Moreover, a complete tool chain for SimREMUS, including compiler and debugger, is developed. SimREMUS could simulate 270 k cycles per second for million gates SoC (System-on-a-Chip) and produced one H.264 1080p frame in 15 minutes, which might cost days on VCS (platform: CPU: E5200@ 2.5 Ghz, RAM: 2.0 GB). Simulation showed that 1080p@30 fps of H.264 High Profile@ Level 4 can be achieved when exploiting a 200 MHz working frequency on the VLSI architecture of REMUS.

TCP's performance significantly degrades in multi-hop wireless networks because TCP's retransmission timeouts (RTOs) are frequently triggered regardless of congestion due to sudden delay and wireless transmission errors. Such RTOs non-related to congestions lead to TCP's unnecessary behaviors such as retransmitting all the outstanding packets which might be located in the bottleneck queue or reducing sharply its sending rate and increasing exponentially its back-off value even when the network is not congested. Since traditional TCP has no ability to identify if a RTO is triggered by congestion or not, it is unavoidable for TCP to underutilize available bandwidth by blindly reducing its sending rate for all the RTOs. In this paper, we propose an algorithm to detect the RTOs non-related to congestion in order to let TCP respond to the RTOs differently according to the cause. When a RTO is triggered, our algorithm estimates the queue usage in the network path during the go-back-N retransmissions, and decides if the RTO is triggered by congestion or not when the retransmissions end. If any RTO non-related to congestion is detected, our algorithm prevents TCP from increasing unnecessarily its back-off value as well as reducing needlessly its sending rate. Throughout the extensive simulation scenarios, we observed how frequently RTOs are triggered regardless of congestion, and evaluated our algorithm in terms of accuracy and goodput. The experiment results show that our algorithm has the highest accuracy among the previous works and the performance enhancement reaches up to 70% when our algorithm is applied to TCP.

In this paper, a scheme for constructing the flat frequency spectrum of interleaved frequency division multiple access (IFDMA) is proposed. Since IFDMA is one of the single carrier modulation schemes, the frequency spectrum components are fluctuated and depend on the information data sequence. Even if IFDMA modulation scheme makes frequency spectrum dispersive for obtaining frequency diversity gain, frequency diversity gain is reduced by the fluctuation of frequency spectrum. In addition, in decision directed channel estimation (DDCE), which achieves good channel estimation accuracy in fast fading environment, the accuracy of channel transfer function estimated at the significant attenuated frequency component is much degraded. In the proposed technique, a random phase sequence is multiplied to the information data sequence for constructing the flat frequency spectrum. As a result, the frequency diversity gain is enlarged and the accuracy of channel estimation by DDCE is improved. Furthermore, we consider the blind estimation technique for the random phase sequence selected by transmitter. We show the effects of the proposed scheme by computer simulation.

This paper presents a construction of a single-event-upset (SEU) tolerant reset-set (RS) flip-flop (FF). The proposed RS-FF consists of four identical parts which form an interlocking feedback loop just like DICE. The area and average power consumption of the proposed RS-FFs are 1.101.48 and 1.201.63 times smaller than those of the conventional SEU tolerant RS-FFs, respectively.

Recent advances in cooperative communication and wireless Network Coding (NC) may lead to huge performance gains in relay systems. In this context, we focus on the two-way relay scenario, where two nodes exchange information via a common relay. We design a practical Superposition Coding (SC) based NC scheme for Decode-and-Forward (DF) half-duplex relaying, where the goal is to increase the achievable rate. By taking advantage of the direct link and by providing a suboptimal yet efficient power division among the superposed layers, our proposed SC two-way relaying scheme outperforms the reference schemes, including the well-known 3-step DF-NC scheme and the capacity of 2-step schemes for a large set of SNRs, while approaching closely the performance bound.

The selection cooperation is a basic and attractive scheme of cooperative diversity in the multiple relays scenario. Most previous schemes of selection cooperation consist only one relay-stage in which one relay is selected to retransmit, and the signal from the selected relay is not utilized by other relays. In this paper, we introduce a two relay-stage selection cooperation scheme. The performance can be improved by letting all other relays to utilize the signal from the first selected relay to make another selection and retransmission in the second relay-stage. We derive the closed-form expression of the outage probability of the proposed scheme in the high SNR regime. Both theoretical and numerical results suggest that the proposed scheme can reduce the outage probability compared with the traditional scheme with only one relay-stage. Furthermore, we demonstrate that more than two relay-stage can not further reduce the outage probability. We also study the dependence of the proposed scheme on stage lengths and topology, and analyze the increased overhead.

This paper presents two circuits to measure pulse width distribution of single event transients (SETs). We first review requirements for SET measurement in accelerated neutron radiation test and point out problems of previous works, in terms of time resolution, time/area efficiency for obtaining large samples and certainty in absolute values of pulse width. We then devise two measurement circuits and a pulse generator circuit that satisfy all the requirements and attain sub-FO1-inverter-delay resolution, and propose a measurement procedure for assuring the absolute width values. Operation of one of the proposed circuits was confirmed by a radiation experiment of alpha particles with a fabricated test chip.