Workflow technology has spread over the wide areas which require process control (e.g. logistics and e-business) or resource coordination (e.g. cooperative work and grid computing). Among various types of workflow, we introduce a case of ad-hoc workflow process in a Korean telecom company. Since such a service process is generally accompanied with customer's participation, the procedure and state are flexibly changed and sometimes capricious to cope with customer's request and operator's unexpected situation. In case of network service provisioning or problem shooting processes, customers often request the changes of their service types or visit appointments, which result in flexible and adaptive management of the process instances. In this paper, we present a novel approach to workflow modeling based on modified ECA rules (named P-ECA) for the purpose of ad-hoc workflow process modeling. The rule-based workflow modeling is comprehensible to engineers and can be implemented in programs at ease; therefore it is expected that it can be widely adopted for the ad-hoc and adaptive workflow modeling which requires dynamic changes of its states by internal or external events.

The biggest challenge in multi-cell MIMO multiplexing systems is how to effectively suppress the other-cell interference (OCI) since the OCI severely decrease the system performance. Cooperation among cells is one of the most promising solutions to OCI problems. However, this solution suffers greatly from delay and overhead issues, which make it impractical. A coordinated MIMO system with a simplified cooperation between the base stations is a compromise between the theory and practice. We aim to devise an effective resource allocation algorithm based on a coordinated MIMO system that largely alleviates the OCI. In this paper, we propose a joint resource allocation algorithm incorporating intra-cell beamforming multiplexing and inter-cell interference suppression, which adaptively allocates the transmitting power and schedules users while achieving close to an optimal system throughput under proportional fairness consideration. We formulate this problem as a nonlinear combinational optimization problem, which is hard to solve. Then, we decouple the variables and transform it into a problem with convex sub-problems that can be solve but still need heavy computational complexity. In order to implement the algorithm in real-time scenarios, we reduce the computational complexity by assuming an equal power allocation utility to do user scheduling before the power allocation. Extensive simulation results show that the joint resource allocation algorithm can achieve a higher throughput and better fairness than the traditional method while maintains the proportional fairness. Moreover, the low-complexity algorithm obtains a better fairness and less computational complexity with only a slight loss in throughput.

Reliable data transmission is desirable in wireless sensor networks due to the high packet loss rate during multi-hop transmissions. To reliably transmit data for event-driven applications, packet loss recovery mechanism is needed. For loss recovery, sensor nodes need to keep packets in their buffers until transmissions successfully complete. However, since sensor nodes have limited memory, packets cannot be buffered for a long period of time. This letter proposes an efficient buffer management technique that caches data packets for appropriate amount of time to minimize the resource requirements and at the same time provide reliable data transmission among sensor nodes.

We develop a mathematical framework for the extrinsic information transfer (EXIT) analysis to assess the convergence behavior of maximum a posteriori (MAP)-based joint iterative decoding of correlated sources, which are separately encoded and transmitted over noisy channels. Unlike the previous work, our approach focuses on the case side information about the correlation is not perfectly given at the joint decoder but is extracted from decoder output and updated in an iterative manner. The presented framework provides a convenient way to compare between schemes. We show that it allows us to easily and accurately predict joint decoding gain and turbo cliff position.

Base Station (BS) cooperation has been considered as a promising technology to mitigate co-channel interference (CCI), yielding great capacity improvement in cellular systems. In this paper, by combining frequency domain cooperation and space domain cooperation together, we design a new CCI mitigation scheme to maximize the total utility for a multi-cell OFDMA network. The scheme formulates the CCI mitigation problem as a mixture integer programming problem, which involves a joint user-set-oriented subcarrier assignment and power allocation. A computationally feasible algorithm based on Lagrange dual decomposition is derived to evaluate the optimal value of the problem. Moreover, a low-complexity suboptimal algorithm is also presented. Simulation results show that our scheme outperforms the counterparts incorporating BS cooperation in a single domain considerably, and the proposed low-complexity algorithm achieves near optimal performance.

We present a hardware sharing method for design space exploration of multi-processor embedded systems. In our prior work, we had developed a system-level design tool named SystemBuilder which automatically synthesizes target implementation of a system from a functional description. In this work, we have extended SystemBuilder so that it can automatically synthesize an area-efficient implementation which shares a hardware module among different applications. With SystemBuilder, designers only need to enable an option in order to share a hardware module. The designers, therefore, can easily explore a design space including hardware sharing in short time. A case study shows the effectiveness of the hardware sharing on design space exploration.

A cognitive radio will have to sense and discover the spectral environments where it would not cause primary radios to interfere. Because the primary radios have the right to use the frequency, the cognitive radios as the secondary radios must detect radio signals before use. However, the secondary radios also need identifying the primary and other secondary radios where the primary radios are vulnerable to interference. In this paper, a method of simultaneously identifying signals of primary and secondary radios is proposed. The proposed bandwidth differentiation assumes the primary and secondary radios use orthogonal frequency division multiplexing (OFDM), and the secondary radios use at the lower number of subcarriers than the primary radios. The false alarm and detection probabilities are analytically evaluated using the characteristic function method. Numerical evaluations are also conducted on the assumption the primary radio is digital terrestrial television broadcasting. Result showed the proposed method could achieve the false alarm probability of 0.1 and the detection probability of 0.9 where the primary and secondary radio powers were 2.5 dB and 3.6 dB higher than the noise power. In the evaluation, the reception signals were averaged over the successive 32 snapshots, and the both the primary and secondary radios used QPSK. The power ratios were 4.7 dB and 8.4 dB where both the primary and secondary radios used 64QAM.

A mobile ad-hoc network (MANET) consists of a collection of wireless mobile nodes without any fixed network infrastructure. Since the mobile nodes form a constantly changing topology, the design of efficient and scalable routing protocols is a fundamental challenge in MANETs. In the current literature, position-based routing protocols are regarded as having better scalability and lower control overhead than topology-based routing protocols. Since location services are the most critical part of position-based routing protocols, we present a multi-home-region scheme, Distributed Virtual Home Region with Spatial Awareness (DVHR-SA), to improve the performance of location service in this paper. Our scheme adaptively selects different update and query procedures according to the location of a source node. The simulation results show that DVHR-SA shortens the lengths of the update, query and reply paths. Our scheme also reduces the overall network message overhead. Therefore, DVHR-SA is considerably fast and stable.

Scan-based side-channel attacks retrieve a secret key in a cryptography circuit by analyzing scanned data. Since they must be considerable threats to a cryptosystem LSI, we have to protect cryptography circuits from them. RSA is one of the most important cryptography algorithms because it effectively realizes a public-key cryptography system. RSA is extensively used but conventional scan-based side-channel attacks cannot be applied to it because it has a complicated algorithm. This paper proposes a scan-based side-channel attack which enables us to retrieve a secret key in an RSA circuit. The proposed method is based on detecting intermediate values calculated in an RSA circuit. We focus on a 1-bit time-sequence which is specific to some intermediate values. By monitoring the 1-bit time-sequence in the scan path, we can find out the register position specific to the intermediate value and we can know whether this intermediate value is calculated or not in the target RSA circuit. We can retrieve a secret key one-bit by one-bit from MSB to LSB. The experimental results demonstrate that a 1,024-bit secret key used in the target RSA circuit can be retrieved using 30.2 input messages within 98.3 seconds and its 2,048-bit secret key can be retrieved using 34.4 input within 634.0 seconds.

A 9-bit 100-MS/s successive approximation register (SAR) ADC with low power and small area has been implemented in 65-nm CMOS technology. A tri-level charge redistribution technique is proposed to reduce DAC switching energy and settling time. By connecting bottom plates of differential capacitor arrays for charge sharing, extra reference voltage is avoided. Two reference voltages charging and discharging the capacitors are chosen to be supply voltage and ground in order to save energy and achieve a rail-to-rail input range. Split capacitor arrays with mismatch calibration are implemented for small area and small input capacitance without linearity degradation. The ADC achieves a peak SNDR of 53.1 dB and consumes 1.46 mW from a 1.2-V supply, resulting in a figure of merit (FOM) of 39 fJ/conversion-step. The total active area is 0.012 mm2 and the input capacitance is 180 fF.

TCP's performance significantly degrades in multi-hop wireless networks because TCP's retransmission timeouts (RTOs) are frequently triggered regardless of congestion due to sudden delay and wireless transmission errors. Such RTOs non-related to congestions lead to TCP's unnecessary behaviors such as retransmitting all the outstanding packets which might be located in the bottleneck queue or reducing sharply its sending rate and increasing exponentially its back-off value even when the network is not congested. Since traditional TCP has no ability to identify if a RTO is triggered by congestion or not, it is unavoidable for TCP to underutilize available bandwidth by blindly reducing its sending rate for all the RTOs. In this paper, we propose an algorithm to detect the RTOs non-related to congestion in order to let TCP respond to the RTOs differently according to the cause. When a RTO is triggered, our algorithm estimates the queue usage in the network path during the go-back-N retransmissions, and decides if the RTO is triggered by congestion or not when the retransmissions end. If any RTO non-related to congestion is detected, our algorithm prevents TCP from increasing unnecessarily its back-off value as well as reducing needlessly its sending rate. Throughout the extensive simulation scenarios, we observed how frequently RTOs are triggered regardless of congestion, and evaluated our algorithm in terms of accuracy and goodput. The experiment results show that our algorithm has the highest accuracy among the previous works and the performance enhancement reaches up to 70% when our algorithm is applied to TCP.

In this letter, we address a strategy to enhance the signal-to-interference plus noise ratio (SINR) of the worst-case user by using cooperative transmission from a set of geographically separated antennas. Unlike previously reported schemes which are based on either the power control of individual antennas or cooperative orthogonal transmission, the presented strategy utilizes the minimum-mean-squared error (MMSE) filter structure for beamforming, which provides increased robustness to the external interference as well as the background noise at the receiver. By iteratively updating the cooperative transmission beamforming vector and power control (PC), the balanced SINR is obtained for all users, while the transmission power from each antenna also converges to within the constrained value. It is demonstrated that proposed MMSE beamforming significantly outperforms other existing schemes in terms of the achievable minimum SINR.

Clock driver suffers from delay variation due to manufacturing and environmental variabilities as well as combinational cells. The delay variation causes clock skew and jitter, and varies both setup and hold timing margins. This paper presents a timing verification method that takes into consideration delay variation inside a clock network due to both manufacturing variability and dynamic power supply noise. We also discuss that setup and hold slack computation inherently involves a structural correlation problem due to common paths, and demonstrate that assigning individual random variables to upstream clock drivers provides a notable accuracy improvement in clock skew estimation with limited increase in computational cost. We applied the proposed method to industrial designs in 90 nm process. Experimental results show that dynamic delay variation reduces setup slack by over 500 ps and hold slack by 16.4 ps in test cases.

This paper proposes an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The processor consists of multiple PE (processing element) cores and a selective set-associative cache memory. The PE-cores have the same instruction set architecture but differ in their clock speeds and energy consumptions. Only a single PE-core is activated at a time and the other PE-cores are deactivated using clock gating and signal gating techniques. The major advantage over the DVS processors is a small overhead for changing its performance. The gate-level simulation demonstrates that our processor can change its performance within 1.5 microsecond and dissipates about 10 nano-joule while conventional DVS processors need hundreds of microseconds and dissipate a few micro-joule for the performance transition. This makes it possible to apply our multi-performance processor to many real-time systems and to perform finer grained and more sophisticated dynamic voltage control.

This paper investigates primary signal detection by using a quiet period (QP) in cognitive wireless communications. In particular, we provide an analytical model for studying the impact of QPs on the system performance. Our analysis shows that two successive QPs have a significant impact on system performance. Moreover, the analytical results obtained reveal an optimum period of two successive QPs that maximize system performance.

Multi-pattern matching is a key technique for implementing network security applications such as Network Intrusion Detection/Protection Systems (NIDS/NIPSes) where every packet is inspected against tens of thousands of predefined attack signatures written in regular expressions (regexes). To this end, Deterministic Finite Automaton (DFA) is widely used for multi-regex matching, but existing DFA-based researches have claimed high throughput at an expense of extremely high memory cost, so fail to be employed in devices such as high-speed routers and embedded systems where the available memory is quite limited. In this paper, we propose a parallel architecture of DFA called Parallel DFA (PDFA) taking advantage of the large amount of concurrent flows to increase the throughput with nearly no extra memory cost. The basic idea is to selectively store the underlying DFA in memory modules that can be accessed in parallel. To explore its potential parallelism we intensively study DFA-split schemes from both state and transition points in this paper. The performance of our approach in both the average cases and the worst cases is analyzed, optimized and evaluated by numerical results. The evaluation shows that we obtain an average speedup of 100 times compared with traditional DFA-based matching approach.

This paper proposes two algorithms to balance energy consumption among sensor nodes by distributing the workload of image compression tasks within a cluster on wireless sensor networks. The main point of the proposed algorithms is to adopt the energy threshold, which is used when we implement the exchange and/or assignment of tasks among sensor nodes. The threshold is well adaptive to the residual energy of sensor nodes, input image, compressed output, and network parameters. We apply the lapped transform technique, an extended version of the discrete cosine transform, and run length encoding before Lempel-Ziv-Welch coding to the proposed algorithms to improve both quality and compression rate in image compression scheme. We extensively conduct computational experiments to verify the our methods and find that the proposed algorithms achieve not only balancing the total energy consumption among sensor nodes and, thus, increasing the overall network lifetime, but also reducing block noise in image compression.

This paper introduces a cycle-accurate Simulator for a dynamically REconfigurable MUlti-media System, called SimREMUS. SimREMUS can either be used at transaction-level, which allows the modeling and simulation of higher-level hardware and embedded software, or at register transfer level, if the dynamic system behavior is desired to be observed at signal level. Trade-offs among a set of criteria that are frequently used to characterize the design of a reconfigurable computing system, such as granularity, programmability, configurability as well as architecture of processing elements and route modules etc., can be quickly evaluated. Moreover, a complete tool chain for SimREMUS, including compiler and debugger, is developed. SimREMUS could simulate 270 k cycles per second for million gates SoC (System-on-a-Chip) and produced one H.264 1080p frame in 15 minutes, which might cost days on VCS (platform: CPU: E5200@ 2.5 Ghz, RAM: 2.0 GB). Simulation showed that 1080p@30 fps of H.264 High Profile@ Level 4 can be achieved when exploiting a 200 MHz working frequency on the VLSI architecture of REMUS.

This paper presents a voltage reference that utilizes the virtually diode-connected MOS transistors, biased in the weak-inversion region. The proposed architecture increases the gain of the feedback loop that consequently reduces the system sensitivity, and hence improves the PSRR. The circuit is designed and simulated in a standard 0.18 µm CMOS technology. The simulation results in HSPICE indicate the successful operation of the circuit as follows: the PSRR at DC frequency is 86 dB and for the temperature range from -55C to 125C, the variation of the output reference voltage is less than 66 ppm/C.

In this letter, an eigenspace of network topology is introduced to increase a spatial capacity. The network topology is represented as an adjacency matrix. By an eigenvector of adjacency matrix, efficient two way transmission can be realized in wireless distributed networks. It is confirmed by numerical analysis that the scheme with an eigenvector of adjacency matrix supplies higher spatial capacity and reliability than that of conventional scheme.