The key issue in cognitive radio is to design a reliable spectrum sensing method that is able to detect the signal in the target channel as well as to recognize its type. In this paper, focusing on classifying different orthogonal frequency-division multiplexing (OFDM) signals, we propose a two-step detection and identification approach based on the analysis of the cyclic autocorrelation function. The key parameters to separate different OFDM signals are the subcarrier spacing and symbol duration. A symmetric peak detection method is adopted in the first step, while a pulse detection method is used to determine the symbol duration. Simulations validate the proposed method.

Placing a guard trace next to a signal line is the conventional technique for reducing the common-mode radiation from a printed circuit board. In this paper, the suppression of common-mode radiation from printed circuit boards having guard traces is estimated and evaluated using the imbalance difference model, which was proposed by the authors. To reduce common-mode radiation further, a procedure for designing a transmission line with guard traces is proposed. Guard traces connected to a return plane through vias are placed near a signal line and they decrease a current division factor (CDF). The CDF represents the degree of imbalance of a transmission line, and a common-mode electromotive force depends on the CDF. Thus, by calculating the CDF, we can estimate the reduction in common-mode radiation. It is reduced not only by placing guard traces, but also by narrowing the signal line to compensate for the variation in characteristic impedance due to the guard traces. Experimental results showed that the maximum reduction in common-mode radiation was about 14 dB achieved by placing guard traces on both sides of the signal line, and the calculated reduction agreed with the measured one within 1 dB. According to the CDF and characteristic impedance calculations, common-mode radiation can be reduced by about 25 dB while keeping the characteristic impedance constant by changing the gap between the signal line and the guard trace and by narrowing the width of the signal line.

This paper presents a system architecture for sensor signal digitization utilizing a band-pass sigma-delta modulator (BP ΣΔM). The first version of the proposed system architecture was implemented in 5 V 0.7 µm CMOS technology. The proposed system architecture is useful for our capacitive pressure sensor measurement. The paper describes the possibilities of using the proposed enhanced system architecture in impedance spectroscopy and in capacitive pressure sensor measurement. The BP ΣΔM is well suited for wireless applications. This paper shows another way how to use its advantages.

This paper proposes a frequency domain nulling filter and Turbo equalizer to suppress interference in the uplink of one-cell reuse single-carrier time division multiple access (TDMA) systems. In the proposed system, the desired signal in a reference cell is interfered by interference signals including adjacent-channel interference (ACI), co-channel interference (CCI), and intersymbol interference (ISI). At the transmitter, after a certain amount of spectrum is nulled considering the expected CCI, the suppressed power due to nulling is reallocated to the remaining spectrum components so as to keep the total transmit power constant. In this process, when mitigation of ACI is necessary, after a certain amount of spectrum at both edges is nulled using an edge-removal filter, the aforementioned process is conducted. At the receiver, frequency domain SC/MMSE Turbo equalizer (FDTE) is employed to suppress ISI due to spectrum nulling process in the transmitter as well as the multipath fading. Computer simulations confirm that the proposed scheme is effective in suppression of CCI, ACI and ISI in one-cell reuse single-carrier TDMA systems.

We analyze the performance of an opportunistic transmission strategy for Wireless Sensor Networks (WSNs). We consider a transmission strategy called Binary Decision-Based Transmission (BDT), which is a common form of opportunistic transmission. The BDT scheme initiates transmission only when the channel quality exceeds the optimum threshold to avoid unsuccessful transmissions that waste energy. We formulate the Markov Decision Process (MDP) to identify an optimum threshold for transmission decisions in the BDT scheme.

A 60-GHz phase-locked loop (PLL) with an inductor-less prescaler is fabricated in a 90-nm CMOS process. The inductor-less prescaler has a smaller chip area than previously reported ones. The PLL operates from 61 to 63 GHz and consumes 78 mW from a 1.2 V supply. The phase noise at 100 kHz and 1 MHz offset from carrier are -72 and -80 dBc/Hz, respectively. The prescaler occupies 8040 µm2. The active area of the PLL is 0.31 mm2.

Among spatial diversity schemes, orthogonal space-time block code (OSTBC) and cyclic delay diversity (CDD) have been widely studied for the cooperative wireless relaying system. However, conventional OSTBC and CDD cannot cope with change in the number of relays owing to low throughput or error performance. In this letter, we propose the space-time cyclic delay diversity (STCDD) scheme which provides good error performance and full rate. Simulation results show that bit error rate (BER) performance of the proposed STCDD is superior to that of OSTBC and CDD when sufficient quality of source-relay channels are guaranteed.

We propose a dimension reduction algorithm for the receiver of the downlink of direct-sequence code-division multiple access (DS-CDMA) systems in which both the transmitters and the receivers employ antenna arrays of multiple elements. To estimate the high order channel parameters, we develop a layered architecture using dimension-reduced parameter estimation algorithms to estimate the frequency-selective multipath channels. In the proposed architecture, to exploit the space-time geometric characteristics of multipath channels, spatial beamformers and constrained (or unconstrained) temporal filters are adopted for clustered-multipath grouping and path isolation. In conjunction with the multiple access interference (MAI) suppression techniques, the proposed architecture jointly estimates the direction of arrivals, propagation delays, and fading amplitudes of the downlink fading multipaths. With the outputs of the proposed architecture, the signals of interest can then be naturally detected by using path-wise maximum ratio combining. Compared to the traditional techniques, such as the Joint-Angle-and-Delay-Estimation (JADE) algorithm for DOA-delay joint estimation and the space-time minimum mean square error (ST-MMSE) algorithm for signal detection, computer simulations show that the proposed algorithm substantially mitigate the computational complexity at the expense of only slight performance degradation.

Sanitizable signatures allow sanitizers to delete some pre-determined parts of a signed document without invalidating the signature. While ordinary sanitizable signatures allow verifiers to know how many subdocuments have been sanitized, invisibly sanitizable signatures do not leave any clue to the sanitized subdocuments; verifiers do not know whether or not sanitizing has been performed. Previous invisibly sanitizable signature scheme was constructed based on aggregate signature with pairings. In this article, we present the first invisibly sanitizable signature without using pairings. Our proposed scheme is secure under the RSA assumption.

Two-dimensional (2D) matrix symbols have higher storage capacity than conventional bar-codes, and hence have been used in various applications, including parts management in factories and Internet site addressing in camera-equipped mobile phones. These symbols generally utilize strong error control codes to protect data from errors caused by blots and scratches, and therefore require a large number of check bits. Because 2D matrix symbols are expressed in black and white dot patterns, blots and scratches often induce clusters of unidirectional errors (i.e., errors that affect black but not white dots, or vice versa). This paper proposes a new class of unidirectional lm ln-clustered error correcting codes capable of correcting unidirectional errors confined to a rectangle with lm rows and ln columns. The proposed code employs 2D interleaved parity-checks, as well as vertical and horizontal arithmetic residue checks. Clustered error pattern is derived using the 2D interleaved parity-checks, while vertical and horizontal positions of the error are calculated using the vertical and horizontal arithmetic residue checks. This paper also derives an upper bound on the number of codewords based on Hamming bound. Evaluation shows that the proposed code provides high code rate close to the bound. For example, for correcting a cluster of unidirectional 40 40 errors in 150 150 codeword, the code rate of the proposed code is 0.9272, while the upper bound is 0.9284.

In an embedded system where a single application or a class of applications is repeatedly executed on a processor, its cache configuration can be customized such that an optimal one is achieved. We can have an optimal cache configuration which minimizes overall memory access time by varying the three cache parameters: the number of sets, a line size, and an associativity. In this paper, we first propose two cache simulation algorithms: CRCB1 and CRCB2, based on Cache Inclusion Property. They realize exact cache simulation but decrease the number of cache hit/miss judgments dramatically. We further propose three more cache design space exploration algorithms: CRMF1, CRMF2, and CRMF3, based on our experimental observations. They can find an almost optimal cache configuration from the viewpoint of access time. By using our approach, the number of cache hit/miss judgments required for optimizing cache configurations is reduced to 1/10-1/50 compared to conventional approaches. As a result, our proposed approach totally runs an average of 3.2 times faster and a maximum of 5.3 times faster compared to the fastest approach proposed so far. Our proposed cache simulation approach achieves the world fastest cache design space exploration when optimizing total memory access time.

Internet routers need to classify incoming packets quickly into flows in order to support features such as Internet security, virtual private networks and Quality of Service (QoS). Packet classification uses information contained in the packet header, and a predefined rule table in the routers. Packet classification of multiple fields is generally a difficult problem. Hence, researchers have proposed various algorithms. This study proposes a multi-dimensional encoding method in which parameters such as the source IP address, destination IP address, source port, destination port and protocol type are placed in a multi-dimensional space. Similar to the previously best known algorithm, i.e., bitmap intersection, multi-dimensional encoding is based on the multi-dimensional range lookup approach, in which rules are divided into several multi-dimensional collision-free rule sets. These sets are then used to form the new coding vector to replace the bit vector of the bitmap intersection algorithm. The average memory storage of this encoding is θ (LNlog N) for each dimension, where L denotes the number of collision-free rule sets, and N represents the number of rules. The multi-dimensional encoding practically requires much less memory than bitmap intersection algorithm. Additionally, the computation needed for this encoding is as simple as bitmap intersection algorithm. The low memory requirement of the proposed scheme means that it not only decreases the cost of packet classification engine, but also increases the classification performance, since memory represents the performance bottleneck in the packet classification engine implementation using a network processor.

We describe the applicability of photonic crystal fiber (PCF) with an enlarged effective area Aeff to a distributed Raman amplification (DRA) transmission. We investigate the DRA transmission performance numerically over a large Aeff PCF taking account of the signal-to-noise ratio (SNR) improvement RSNR in the S, C, and L bands. We show that an RSNR of 3 dB can be expected by utilizing DRA with a maximum pump power of 500 mW when the Aeff of the PCF is 230 µm2.

An inductive buffer peaking technique is proposed and demonstrated to extend the bandwidth of a 10-Gbit/s transimpedance amplifier (TIA) for optical communications. A TIA using this peaking technique is fabricated based on InGaP/GaAs HBT technology. The advantage of the proposed technique is verified by comparisons based on simulations and experiments. For these comparisons, three different types of TIAs using a basic gain stage, a shunt peaking gain stage and the proposed gain stage, respectively, are fabricated and measured. The measured performance of the proposed TIA shows that this bandwidth extension technique using inductive buffer peaking can be applied to circuit designs which demand wideband frequency response with low power consumption.

Ball Grid Array packages in which I/O pins are arranged in a grid array pattern realize a number of connections between chips and a printed circuit board, but it takes much time in manual routing. We propose a fast routing method for 2-layer Ball Grid Array packages that iteratively modifies via assignment. In experiments, in most cases, via assignment and global routing on both of layers in which all nets are realized and the violation of wire congestion on layer 1 is small are speedily obtained.

This paper proposes a method to construct a basis conversion matrix between two given bases in Fpm. In the proposed method, Gauss period normal basis (GNB) works as a bridge between the two bases. The proposed method exploits this property and construct a basis conversion matrix mostly faster than EDF-based algorithm on average in polynomial time. Finally, simulation results are reported in which the proposed method compute a basis conversion matrix within 30 msec on average with Celeron (2.00 GHz) when mlog p≈160.

Vector Coding (VC) is a novel vector modulation scheme that partitions a SISO (Single-Input Single-Output) channel into orthogonal subchannels by singular value decomposition (SVD). Because the orthogonal transmissions enabled by VC cannot cope with inter block interference (IBI) that is inevitable in delay spread channels, this paper proposes an IBI cancelling demodulator which can remove IBI by an iterative technique. We also show that code elimination in which insignificant eigencodes with lowermost eigenvalues are intentionally removed from transmission vectors greatly reduces BER (Bit Error Rate). The VC which utilizes the IBI cancelling demodulator and code elimination to reduce BER is compared with the original VC in not only delay spread SISO channels but also delay spread MIMO (Multi-Input Multi-Output) channels while emphasis is placed on the MIMO cases. Simulation results show that, under a predetermined BER, the enhanced MIMO-VC can improve effective transmission rate than the natural extension of VC to delay spread MIMO channels.

Recent progress in scaled CMOS technologies can enhance signal bandwidth and clock frequency of analog-digital mixed VLSIs. However, the inevitable reduction of supply voltage causes a signal voltage mismatch between a non-scaled analog chip and a scaled A-D mixed chip. To overcome this problem, we present a Delta-Amplifier (DeltAMP) which can handle larger signal amplitude than the supply voltage. DeltaAMP folds a delta signal of an input voltage within a window using a virtual ground amplifier, modulation switches and comparators. For reconstruction of the folded delta signal to the ordinal signal, Analog-Time-Digital conversion (ATD) was also proposed, in which pulse-width analog information obtained at the comparators in DeltAMP was converted to a digital signal by counting. A test chip of DeltAMP with ATD was designed and fabricated using a 90 nm CMOS technology. A 2 Vpp input voltage range and 50 µW power consumption were achieved by the measurements with a 0.5 V supply. High accuracy of 62 dB SNR was obtained at signal bandwidth of 120 kHz.

Intrusion detection system (IDS) has played an important role as a device to defend our networks from cyber attacks. However, since it is unable to detect unknown attacks, i.e., 0-day attacks, the ultimate challenge in intrusion detection field is how we can exactly identify such an attack by an automated manner. Over the past few years, several studies on solving these problems have been made on anomaly detection using unsupervised learning techniques such as clustering, one-class support vector machine (SVM), etc. Although they enable one to construct intrusion detection models at low cost and effort, and have capability to detect unforeseen attacks, they still have mainly two problems in intrusion detection: a low detection rate and a high false positive rate. In this paper, we propose a new anomaly detection method based on clustering and multiple one-class SVM in order to improve the detection rate while maintaining a low false positive rate. We evaluated our method using KDD Cup 1999 data set. Evaluation results show that our approach outperforms the existing algorithms reported in the literature; especially in detection of unknown attacks.

In this paper, we solve the call admission control (CAC) and routing problem in an integrated network that handles several classes of calls of different values and with different resource requirements. The problem of maximizing the average reward (or cost) of admitted calls per unit time is naturally formulated as a semi-Markov Decision Process (SMDP) problem, but is too complex to allow for an exact solution. Thus in this paper, a policy gradient algorithm, together with a decomposition approach, is proposed to find the dynamic (state-dependent) optimal CAC and routing policy among a parameterized policy space. To implement that gradient algorithm, we approximate the gradient of the average reward. Then, we present a simulation-based algorithm to estimate the approximate gradient of the average reward (called GSMDP algorithm), using only a single sample path of the underlying Markov chain for the SMDP of CAC and routing problem. The algorithm enhances performance in terms of convergence speed, rejection probability, robustness to the changing arrival statistics and an overall received average revenue. The experimental simulations will compare our method's performance with other existing methods and show the robustness of our method.