To reduce RFID tag identification delay, we propose a novel Dynamic Splitting protocol (DS) which is an improvement of the Query tree protocol (QT). DS controls the number of branches of a tree dynamically. An improved performance of DS relative to QT is verified by analytical results and simulation studies.

An integral multi-disciplinary chain optimization based on a high-level cascaded Shannon-based channel modeling is proposed. It is argued that the analog part of the front-end (FE) will become a bottleneck in the overall chain. This requires a FE-centric design approach, aiming for maximizing the effective data capacity, and for an optimal exploitation of this capacity for given power dissipation. At high level, this asks for a new view on the so-called client-server relations in the chain. To substantiate this vision, some examples of research projects in our group are addressed. These include FE-driven transmission schemes, duty-cycled operation with wake-up radio, programmable FEs, smart antenna-FE combinations, smart and flexible converters, and smart pre and post correction.

We propose a sketch-based modeling system where all user input is performed from a unique viewpoint. The strokes drawn by the user must not then be restricted to the drawing plane: their orientation in the 3D space is automatically determined by the system. The desired surface is reconstructed from a grid made of two groups of similar lines, that are considered co-planar. The orientation of the two sets of planes is determined by assuming that at the intersection of a representative line of each group, those two lines are perpendicular.

Intrusion detection system (IDS) has played an important role as a device to defend our networks from cyber attacks. However, since it is unable to detect unknown attacks, i.e., 0-day attacks, the ultimate challenge in intrusion detection field is how we can exactly identify such an attack by an automated manner. Over the past few years, several studies on solving these problems have been made on anomaly detection using unsupervised learning techniques such as clustering, one-class support vector machine (SVM), etc. Although they enable one to construct intrusion detection models at low cost and effort, and have capability to detect unforeseen attacks, they still have mainly two problems in intrusion detection: a low detection rate and a high false positive rate. In this paper, we propose a new anomaly detection method based on clustering and multiple one-class SVM in order to improve the detection rate while maintaining a low false positive rate. We evaluated our method using KDD Cup 1999 data set. Evaluation results show that our approach outperforms the existing algorithms reported in the literature; especially in detection of unknown attacks.

This paper proposes a method to construct a basis conversion matrix between two given bases in Fpm. In the proposed method, Gauss period normal basis (GNB) works as a bridge between the two bases. The proposed method exploits this property and construct a basis conversion matrix mostly faster than EDF-based algorithm on average in polynomial time. Finally, simulation results are reported in which the proposed method compute a basis conversion matrix within 30 msec on average with Celeron (2.00 GHz) when mlog p≈160.

A 60-GHz phase-locked loop (PLL) with an inductor-less prescaler is fabricated in a 90-nm CMOS process. The inductor-less prescaler has a smaller chip area than previously reported ones. The PLL operates from 61 to 63 GHz and consumes 78 mW from a 1.2 V supply. The phase noise at 100 kHz and 1 MHz offset from carrier are -72 and -80 dBc/Hz, respectively. The prescaler occupies 8040 µm2. The active area of the PLL is 0.31 mm2.

An inductive buffer peaking technique is proposed and demonstrated to extend the bandwidth of a 10-Gbit/s transimpedance amplifier (TIA) for optical communications. A TIA using this peaking technique is fabricated based on InGaP/GaAs HBT technology. The advantage of the proposed technique is verified by comparisons based on simulations and experiments. For these comparisons, three different types of TIAs using a basic gain stage, a shunt peaking gain stage and the proposed gain stage, respectively, are fabricated and measured. The measured performance of the proposed TIA shows that this bandwidth extension technique using inductive buffer peaking can be applied to circuit designs which demand wideband frequency response with low power consumption.

Recent progress in scaled CMOS technologies can enhance signal bandwidth and clock frequency of analog-digital mixed VLSIs. However, the inevitable reduction of supply voltage causes a signal voltage mismatch between a non-scaled analog chip and a scaled A-D mixed chip. To overcome this problem, we present a Delta-Amplifier (DeltAMP) which can handle larger signal amplitude than the supply voltage. DeltaAMP folds a delta signal of an input voltage within a window using a virtual ground amplifier, modulation switches and comparators. For reconstruction of the folded delta signal to the ordinal signal, Analog-Time-Digital conversion (ATD) was also proposed, in which pulse-width analog information obtained at the comparators in DeltAMP was converted to a digital signal by counting. A test chip of DeltAMP with ATD was designed and fabricated using a 90 nm CMOS technology. A 2 Vpp input voltage range and 50 µW power consumption were achieved by the measurements with a 0.5 V supply. High accuracy of 62 dB SNR was obtained at signal bandwidth of 120 kHz.

Two-dimensional (2D) matrix symbols have higher storage capacity than conventional bar-codes, and hence have been used in various applications, including parts management in factories and Internet site addressing in camera-equipped mobile phones. These symbols generally utilize strong error control codes to protect data from errors caused by blots and scratches, and therefore require a large number of check bits. Because 2D matrix symbols are expressed in black and white dot patterns, blots and scratches often induce clusters of unidirectional errors (i.e., errors that affect black but not white dots, or vice versa). This paper proposes a new class of unidirectional lm ln-clustered error correcting codes capable of correcting unidirectional errors confined to a rectangle with lm rows and ln columns. The proposed code employs 2D interleaved parity-checks, as well as vertical and horizontal arithmetic residue checks. Clustered error pattern is derived using the 2D interleaved parity-checks, while vertical and horizontal positions of the error are calculated using the vertical and horizontal arithmetic residue checks. This paper also derives an upper bound on the number of codewords based on Hamming bound. Evaluation shows that the proposed code provides high code rate close to the bound. For example, for correcting a cluster of unidirectional 40 40 errors in 150 150 codeword, the code rate of the proposed code is 0.9272, while the upper bound is 0.9284.

In an embedded system where a single application or a class of applications is repeatedly executed on a processor, its cache configuration can be customized such that an optimal one is achieved. We can have an optimal cache configuration which minimizes overall memory access time by varying the three cache parameters: the number of sets, a line size, and an associativity. In this paper, we first propose two cache simulation algorithms: CRCB1 and CRCB2, based on Cache Inclusion Property. They realize exact cache simulation but decrease the number of cache hit/miss judgments dramatically. We further propose three more cache design space exploration algorithms: CRMF1, CRMF2, and CRMF3, based on our experimental observations. They can find an almost optimal cache configuration from the viewpoint of access time. By using our approach, the number of cache hit/miss judgments required for optimizing cache configurations is reduced to 1/10-1/50 compared to conventional approaches. As a result, our proposed approach totally runs an average of 3.2 times faster and a maximum of 5.3 times faster compared to the fastest approach proposed so far. Our proposed cache simulation approach achieves the world fastest cache design space exploration when optimizing total memory access time.

Ball Grid Array packages in which I/O pins are arranged in a grid array pattern realize a number of connections between chips and a printed circuit board, but it takes much time in manual routing. We propose a fast routing method for 2-layer Ball Grid Array packages that iteratively modifies via assignment. In experiments, in most cases, via assignment and global routing on both of layers in which all nets are realized and the violation of wire congestion on layer 1 is small are speedily obtained.

Frequency-domain equalization (FDE) has been studied for suppressing inter-symbol interference (ISI) due to frequency selective fading in single carrier systems. When a high-mobility terminal is assumed in the system, channel transition within an FDE block cannot be ignored. The ISI reduction performance of FDE degrades since the cyclicity of the channel matrix is lost. To solve this problem, a method of dividing the received data block into multiple subblocks has been proposed, where pseudo cyclic prefix (CP) processing is introduced to realize periodicity in each subblock. In this method, the performance is degraded by the inherently-inaccurate pseudo CP. In this paper, we study the application of frequency-domain turbo equalization (FDTE) to subblock processing for improving the accuracy of pseudo CP. The simulation results show that FDTE with subblock processing yields remarkable performance improvements.

Dimensionality reduction is one of the important preprocessing steps in practical pattern recognition. SEmi-supervised Local Fisher discriminant analysis (SELF)--which is a semi-supervised and local extension of Fisher discriminant analysis--was shown to work excellently in experiments. However, when data dimensionality is very high, a naive use of SELF is prohibitive due to high computational costs and large memory requirement. In this paper, we introduce computational tricks for making SELF applicable to large-scale problems.

The Chikazawa-Yamagishi scheme is an ID-based key distribution scheme which is based on the RSA cryptosystem. There are several variant schemes to improve the efficiency and the security of the Chikazawa-Yamagishi scheme. Unfortunately, all of the proposed schemes have some weaknesses. First, all the proposed schemes require time synchronization of the communicating parties. Second, none of the proposed schemes provide both forward secrecy and security against session state reveal attacks. In this paper, we suggest an ID-based key distribution scheme which does not require time synchronization and provides both forward secrecy and security against session state reveal attacks.

A classification method is presented for differentiating honeycombed High Resolution Computed Tomographic (HRCT) images from normal HRCT images. For successful classification of honeycombed HRCT images, a complete set of methods and algorithms is described from segmentation to extraction to feature selection to classification. Wavelet energy is selected as a feature for classification using K-means clustering. Test data of 20 patients are used to validate the method.

A lexicon-driven segmentation-recognition scheme on Bangla handwritten city-name recognition is proposed for Indian postal automation. In the proposed scheme, at first, binarization of the input document is done and then to take care of slanted handwriting of different individuals a slant correction technique is performed. Next, due to the script characteristics of Bangla, a water reservoir concept is applied to pre-segment the slant corrected city-names into possible primitive components (characters or its parts). Pre-segmented components of a city-name are then merged into possible characters to get the best city-name using the lexicon information. In order to merge these primitive components into characters and to find optimum character segmentation, dynamic programming (DP) is applied using total likelihood of the characters of a city-name as an objective function. To compute the likelihood of a character, Modified Quadratic Discriminant Function (MQDF) is used. The features used in the MQDF are mainly based on the directional features of the contour points of the components. We tested our system on 84 different Bangla city-names and 94.08% accuracy was obtained from the proposed system.

Probabilistic model checking is an emerging verification technology for probabilistic analysis. Its use has been started not only in computer science but also in interdisciplinary fields. In this paper, we show that probabilistic model checking allows one to analyze the magnetic behaviors of the one-dimensional Ising model, which describes physical phenomena of magnets. The Ising model consists of elementary objects called spins and its dynamics is often represented as the Metropolis method. To analyze the Ising model with probabilistic model checking, we build Discrete Time Markov Chain (DTMC) models that represent the behavior of the Ising model. Two representative physical quantities, i.e., energy and magnetization, are focused on. To assess these quantities using model checking, we devise formulas in Probabilistic real time Computation Tree Logic (PCTL) that represent the quantities. To demonstrate the feasibility of the proposed approach, we show the results of an experiment using the PRISM model checker.

In this letter, we propose a new power allocation scheme for random unitary beamforming assuming a discrete transmission rate with a small amount of feedback information and low latency. Simulation results show that the proposed scheme can improve throughput compared to the conventional power allocation scheme.

The 3GPP Long Term Evolution Advanced (LTE-A) system, as compared to the LTE system, is anticipated to include several new features and enhancements, such as the usage of channel bandwidth beyond 20 MHz (up 100 MHz), higher order multiple input multiple output (MIMO) for both downlink and uplink transmissions, larger capacity especially for cell edge user equipment, and voice over IP (VoIP) users, and wider coverage and etc. This paper presents some key enabling technologies including flexible uplink access schemes, advanced uplink MIMO receiver designs, cell search, adaptive hybrid ARQ, and multi-resolution MIMO precoding, for the LTE-A system.

An interference cancellation (ICAN) scheme for mobile communication radio repeaters is presented. When a radio repeater has a gain that is larger than the isolation between its transmit and receive antennas, it oscillates due to feedback interference signals. To prevent feedback oscillation of a radio repeater, we first formulate a feedback oscillation model of the radio repeater and then derive an ICAN model from that model. From the derived ICAN model, we show that the stability and the signal quality of the repeater depend on the repeater's gain and delay, the propagation delay on feedback paths, feedback channel characteristics, and the capability of the feedback channel estimation algorithm. It is also shown that the stability condition of the repeater does not guarantee the quality of the repeater's output signal. To guarantee repeater's stability and signal quality, an ICAN scheme based on an iterative algorithm is subsequently proposed. The simulation results confirm the relationship between the stability and signal quality of the repeater and the impact of the aforementioned factors. Using the proposed ICAN scheme, a mean error vector magnitude (quality indicator) of about 6.3% for the repeater's output signal was achieved.