An inductive buffer peaking technique is proposed and demonstrated to extend the bandwidth of a 10-Gbit/s transimpedance amplifier (TIA) for optical communications. A TIA using this peaking technique is fabricated based on InGaP/GaAs HBT technology. The advantage of the proposed technique is verified by comparisons based on simulations and experiments. For these comparisons, three different types of TIAs using a basic gain stage, a shunt peaking gain stage and the proposed gain stage, respectively, are fabricated and measured. The measured performance of the proposed TIA shows that this bandwidth extension technique using inductive buffer peaking can be applied to circuit designs which demand wideband frequency response with low power consumption.

In this paper, we solve the call admission control (CAC) and routing problem in an integrated network that handles several classes of calls of different values and with different resource requirements. The problem of maximizing the average reward (or cost) of admitted calls per unit time is naturally formulated as a semi-Markov Decision Process (SMDP) problem, but is too complex to allow for an exact solution. Thus in this paper, a policy gradient algorithm, together with a decomposition approach, is proposed to find the dynamic (state-dependent) optimal CAC and routing policy among a parameterized policy space. To implement that gradient algorithm, we approximate the gradient of the average reward. Then, we present a simulation-based algorithm to estimate the approximate gradient of the average reward (called GSMDP algorithm), using only a single sample path of the underlying Markov chain for the SMDP of CAC and routing problem. The algorithm enhances performance in terms of convergence speed, rejection probability, robustness to the changing arrival statistics and an overall received average revenue. The experimental simulations will compare our method's performance with other existing methods and show the robustness of our method.

We propose a new modulation, phase-silence-shift-keying (PSSK), whose symbol error rate (SER) performance is improved by 6 dB compared with phase-shift-keying (PSK). To prove this, theoretical analysis of probability of error is provided and simulation results are presented.

Even though it is very important to retrieve similar trajectories with a given query trajectory, there has been a little research on trajectory retrieval in spatial networks, like road networks. In this paper, we propose an efficient indexing scheme for retrieving moving object trajectories in spatial networks. For this, we design a signature-based indexing scheme for efficiently dealing with the trajectories of current moving objects as well as for maintaining those of past moving objects. In addition, we provide an insertion algorithm for storing the segment information of a moving object trajectory as well as a retrieval algorithm to find a set of moving objects whose trajectories match the segments of a query trajectory. Finally, we show that our signature-based indexing scheme achieves at least twice better performance on trajectory retrieval than the leading trajectory indexing schemes, such as TB-tree, FNR-tree, and MON-tree.

A high-speed and ultra-low-voltage divide-by-4/5 counter with dynamic floating input D flip-flop (DFIDFF) is presented in this paper. The proposed DFIDFF and control logic gates are merged to reduce effective capacitance of internal and external nodes, and increase the operating speed of divide-by-4/5 counter. The proposed divide-by-4/5 counter is fabricated in a 0.13-µm CMOS process. The measured maximum operating frequency and power consumption of the counter are 600 MHz and 8.35 µW at a 0.5 V supply voltage. HSPICE simulations demonstrate that the proposed counter (divide-by-4) reduces power-delay product (PDP) by 37%, 71%, and 57% from those of the TGFF counter, Yang's counter [1], and the E-TSPC counter [2], respectively.

In this paper the time-domain analysis of two parallel traces is investigated. First, the telegrapher's equations for transmission line are applied to the parallel traces on printed circuit board (PCB), and are solved by using the mode decomposition technique. The time-domain solutions are then obtained by using the inverse Laplace transform. Although the Fourier-transform technique is also applicable for this problem, the solution is given numerically. Contrarily, the inverse Laplace transform successfully leads to an analytical expression for the transmission characteristics. The analytical expression is represented by series, which clearly explains the coupling mechanism. The analytical expression for the fundamental section of a meander delay line is investigated in detail. The analytical solution is validated by measurements, and the characteristics of the distortions in the output waveforms of meander delay lines due to the crosstalk are also investigated.

In this paper, estimation accuracy of channel frequency response (CFR) according to least squared (LS) criterion with two transmit antennas for the time domain synchronous-orthogonal frequency division multiplexing (TDS-OFDM) system is investigated. To minimize the estimation variance, the conditions to guide the pseudo-noise (PN) sequence design are discussed and three training sequence design schemes are proposed accordingly. Simulations show that the proposed PN sequence design scheme is effective, while the implementation complexity for the channel estimation is low.

In this paper, we study the capacity and performance of nonorthogonal pulse position modulation (NPPM) for Ultra-Wideband (UWB) communication systems over both AWGN and IEEE802.15.3a channels. The channel capacity of NPPM is determined for a time-hopping multiple access UWB communication system. The error probability and performance bounds are derived for a multiuser environment. It is shown that with proper selection of the pulse waveform and modulation index, NPPM can achieve a higher capacity than orthogonal PPM, and also provide better performance than orthogonal PPM with the same throughput.

Time-interleaved (TI) analog-to-digital converters (ADCs) are frequently advocated as a power-efficient solution to realize the high sampling rates required in single-chip transceivers for the emerging communication schemes: ultra-wideband, fast serial links, cognitive-radio and software-defined radio. However, the combined effects of multiple distortion sources due to channel mismatches (bandwidth, offset, gain and timing) severely affect system performance and power consumption of a TI ADC and need to be accounted for since the earlier design phases. In this paper, system-level design of TI ADCs is addressed through a platform-based methodology, enabling effective investigation of different speed/resolution scenarios as well as the impact of parallelism on accuracy, yield, sampling-rate, area and power consumption. Design space exploration of a TI successive approximation ADC is performed top-down via Monte Carlo simulations, by exploiting behavioral models built bottom-up after characterizing feasible implementations of the main building blocks in a 90-nm 1-V CMOS process. As a result, two implementations of the TI ADC are proposed that are capable to provide an outstanding figure-of-merit below 0.15 pJ/conversion-step.

Analog multipliers are one of the most important building blocks in analog signal processing circuits. The performance with high linearity and wide input range is usually required for analog four-quadrant multipliers in most applications. Therefore, a highly linear and wide input range four-quadrant CMOS analog multiplier using active feedback is proposed in this paper. Firstly, a novel configuration of four-quadrant multiplier cell is presented. Its input dynamic range and linearity are improved significantly by adding two resistors compared with the conventional structure. Then based on the proposed multiplier cell configuration, a four-quadrant CMOS analog multiplier with active feedback technique is implemented by two operational amplifiers. Because of both the proposed multiplier cell and active feedback technique, the proposed multiplier achieves a much wider input range with higher linearity than conventional structures. The proposed multiplier was fabricated by a 0.6 µm CMOS process. Experimental results show that the input range of the proposed multiplier can be up to 5.6Vpp with 0.159% linearity error on VX and 4.8Vpp with 0.51% linearity error on VY for 2.5V power supply voltages, respectively.

A high-sensitivity pickup tube using HARP (high-gain avalanche rushing amorphous photoconductor) photoconductive film, which makes use of the avalanche multiplication phenomenon, has been studied for making a high-sensitivity television camera. The avalanche multiplication factor, i.e., sensitivity, was increased by thickening the film. A 35-µm-thick HARP film, which was more sensitive than the previous 25-µm-thick film with an avalanche multiplication factor of about 600, and a 2/3rd-inch pickup tube using the film were developed. Measurements on the pickup tube demonstrated that it had an avalanche multiplication factor of about 1000, low lag, and high resolution. Moreover, image defects caused by shooting of intense spot lights were investigated, and it was found that exposing the film to UV light before operation and controlling the temperature of the film during operation could suppress the defects.

Power and ground planes on multilayer PCBs can effectively radiate electromagnetic fields excited by the IC simultaneous switching noise. The high frequency electromagnetic radiation is often calculated from the electric field along the edge of the PCB, which can be estimated with a cavity model using magnetic walls. The excitation of the cavity modes is related to the via current passing through the power bus planes at the interconnection between IC package and PCB. Usually the attention is focused on the differential-mode current of the package pins, but in the present paper it is shown that the common-mode current flowing out from package pins plays a very important role in the excitation of cavity modes, and its neglect implies a fatal underestimation of the electromagnetic radiation from the power bus planes in some circumstances. A second important contribute to the radiation is given by the common mode current on the pins, together with the current flowing on the PCB ground plane. With the proposed equivalent circuit, the effectiveness of decoupling inductors depending on their location and on the value of the parasitic capacitance is studied.

To build a stable power distribution network for high-speed digital systems, simultaneous switching noise (SSN) should be sufficiently suppressed in multi-layer PCBs and packages. In this paper, a novel hybrid uni-planar compact electromagnetic bandgap (UC-EBG) with two triangular-type unit cells designed on power/ground planes is proposed for the ultra-broadband suppression of SSN. The SSN suppression performance of the proposed structure is validated both numerically and experimentally. A -35 dB suppression bandwidth for SSN is achieved, starting at 800 MHz and extending to 15 GHz and beyond, thereby covering almost the entire noise band.

The electromagnetic fields emitted from an electrostatic discharge (ESD) event occurring between charged metals cause seriously damage high-tech equipment. In order to clarify the generation mechanism of such ESD fields and also to reduce them, we previously proposed a finite-difference time-domain (FDTD) algorithm based on a delta-gap feeding method and a frequency dispersion characteristic formula (Naito's formula) of ferrite material for simulating the ESD fields due to a spark between the charged metals with ferrite core attachment. In the present study, by integrating the above FDTD algorithm and a spark-resistance formula, we simulated both of the ESD itself and the resultant fields for the metal bars with ferrite core attachment, and demonstrated that the core attachment close to the spark gap suppresses the magnetic field level. This finding was also validated via 6-GHz wide-band measurement of the magnetic near-field.

An integral equation approach with a new solution procedure using moment method (MoM) is applied for the computation of coupled currents on the surface of a printed dipole antenna and inside its high-permittivity three-dimensional dielectric substrate. The main purpose of this study is to validate the accuracy and reliability of the previously proposed MoM procedure by authors for the solution of a coupled volume-surface integral equations system. In continuation of the recent works of authors, a mixed-domain MoM expansion using Legendre polynomial basis function and cubic geometric modeling are adopted to solve the tensor-volume integral equation. In mixed-domain MoM, a combination of entire-domain and sub-domain basis functions, including three-dimensional Legnedre polynomial basis functions with different degrees is utilized for field expansion inside dielectric substrate. In addition, the conventional Rao-Wilton-Glisson (RWG) basis function is employed for electric current expansion over the printed structure. The accuracy of the proposed approach is verified through a comparison with the MoM solutions based on the spectral domain Green's function for infinitely large substrate and the results of FDTD method.

Recent progress in scaled CMOS technologies can enhance signal bandwidth and clock frequency of analog-digital mixed VLSIs. However, the inevitable reduction of supply voltage causes a signal voltage mismatch between a non-scaled analog chip and a scaled A-D mixed chip. To overcome this problem, we present a Delta-Amplifier (DeltAMP) which can handle larger signal amplitude than the supply voltage. DeltaAMP folds a delta signal of an input voltage within a window using a virtual ground amplifier, modulation switches and comparators. For reconstruction of the folded delta signal to the ordinal signal, Analog-Time-Digital conversion (ATD) was also proposed, in which pulse-width analog information obtained at the comparators in DeltAMP was converted to a digital signal by counting. A test chip of DeltAMP with ATD was designed and fabricated using a 90 nm CMOS technology. A 2 Vpp input voltage range and 50 µW power consumption were achieved by the measurements with a 0.5 V supply. High accuracy of 62 dB SNR was obtained at signal bandwidth of 120 kHz.

Vector Coding (VC) is a novel vector modulation scheme that partitions a SISO (Single-Input Single-Output) channel into orthogonal subchannels by singular value decomposition (SVD). Because the orthogonal transmissions enabled by VC cannot cope with inter block interference (IBI) that is inevitable in delay spread channels, this paper proposes an IBI cancelling demodulator which can remove IBI by an iterative technique. We also show that code elimination in which insignificant eigencodes with lowermost eigenvalues are intentionally removed from transmission vectors greatly reduces BER (Bit Error Rate). The VC which utilizes the IBI cancelling demodulator and code elimination to reduce BER is compared with the original VC in not only delay spread SISO channels but also delay spread MIMO (Multi-Input Multi-Output) channels while emphasis is placed on the MIMO cases. Simulation results show that, under a predetermined BER, the enhanced MIMO-VC can improve effective transmission rate than the natural extension of VC to delay spread MIMO channels.

In an embedded system where a single application or a class of applications is repeatedly executed on a processor, its cache configuration can be customized such that an optimal one is achieved. We can have an optimal cache configuration which minimizes overall memory access time by varying the three cache parameters: the number of sets, a line size, and an associativity. In this paper, we first propose two cache simulation algorithms: CRCB1 and CRCB2, based on Cache Inclusion Property. They realize exact cache simulation but decrease the number of cache hit/miss judgments dramatically. We further propose three more cache design space exploration algorithms: CRMF1, CRMF2, and CRMF3, based on our experimental observations. They can find an almost optimal cache configuration from the viewpoint of access time. By using our approach, the number of cache hit/miss judgments required for optimizing cache configurations is reduced to 1/10-1/50 compared to conventional approaches. As a result, our proposed approach totally runs an average of 3.2 times faster and a maximum of 5.3 times faster compared to the fastest approach proposed so far. Our proposed cache simulation approach achieves the world fastest cache design space exploration when optimizing total memory access time.

We describe the applicability of photonic crystal fiber (PCF) with an enlarged effective area Aeff to a distributed Raman amplification (DRA) transmission. We investigate the DRA transmission performance numerically over a large Aeff PCF taking account of the signal-to-noise ratio (SNR) improvement RSNR in the S, C, and L bands. We show that an RSNR of 3 dB can be expected by utilizing DRA with a maximum pump power of 500 mW when the Aeff of the PCF is 230 µm2.

Two-dimensional (2D) matrix symbols have higher storage capacity than conventional bar-codes, and hence have been used in various applications, including parts management in factories and Internet site addressing in camera-equipped mobile phones. These symbols generally utilize strong error control codes to protect data from errors caused by blots and scratches, and therefore require a large number of check bits. Because 2D matrix symbols are expressed in black and white dot patterns, blots and scratches often induce clusters of unidirectional errors (i.e., errors that affect black but not white dots, or vice versa). This paper proposes a new class of unidirectional lm ln-clustered error correcting codes capable of correcting unidirectional errors confined to a rectangle with lm rows and ln columns. The proposed code employs 2D interleaved parity-checks, as well as vertical and horizontal arithmetic residue checks. Clustered error pattern is derived using the 2D interleaved parity-checks, while vertical and horizontal positions of the error are calculated using the vertical and horizontal arithmetic residue checks. This paper also derives an upper bound on the number of codewords based on Hamming bound. Evaluation shows that the proposed code provides high code rate close to the bound. For example, for correcting a cluster of unidirectional 40 40 errors in 150 150 codeword, the code rate of the proposed code is 0.9272, while the upper bound is 0.9284.