A novel voltage measurement circuit which utilizes process variation is proposed. Using the proposed circuit, the voltage of a nonperiodic waveform at a particular time point can be accurately captured by a single clock pulse (one-shot measurement). The proposed circuit can be designed without compensation circuits against process variation, and thus occupies only a small area. An analytical expression of offset voltage for the comparator utilizing process variation (UPV-comparator), which plays a key role in the proposed circuit, is derived and design considerations for the proposed circuit are discussed. The circuit operation is confirmed through SPICE simulation using 90 nm CMOS device models. The -0.04 and -3 dB bandwidths (99% and 50% amplitudes) of the proposed circuit are about 10 MHz and far over 1 GHz, respectively. The circuit area is also estimated using an experimental layout.

This paper describes the modeling and the analysis methodology to evaluate Simultaneous Switching Noise (SSN) for the combined system of the package with the 4-layer Printed Circuit Board (PCB), which the 64 Simultaneous Switching Outputs (SSOs) were included using a simple IBIS model. Simulation results showed that the ground plane in both package and PCB can be used as the reference to reduce SSN more effectively than the power plane. For the source synchronous timing technique such as used in a DDR SDRAM memory bus in the model shown in this paper, the skew control circuit tequiniqe is easy to apply in the chip design instead of using embedded capacitors in the package's substrate. And also the radiated emission and eye diagram analysis were studied.

Complex bandpass ΔΣAD modulators can provide superior performance to a pair of real bandpass ΔΣAD modulators of the same order. They process just input I and Q signals, not image signals, and AD conversion can be realized with low power dissipation, so that they are desirable for such low-IF receiver applications. This paper proposes a new architecture for complex bandpass Δ ΣAD modulators with cross-noise-coupled topology, which effectively raises the order of the complex modulator and achieves higher SQNDR (Signal to Quantization Noise and Distortion Ratio) with low power dissipation. By providing the cross-coupled quantization noise injection to internal I and Q paths, noise coupling between two quantizers can be realized in complex form, which enhances the order of noise shaping in complex domain, and provides a higher-order NTF using a lower-order loop filter in the complex ΔΣAD modulator. Proposed higher-order modulator can be realized just by adding some passive capacitors and switches, the additional integrator circuit composed of an operational amplifier is not necessary, and the performance of the complex modulator can be effectively raised without more power dissipation. We have performed simulation with MATLAB to verify the effectiveness of the proposed architecture. The simulation results show that the proposed architecture can achieve the realization of higher-order enhancement, and improve SQNDR of the complex bandpass ΔΣAD modulator.

In advance of network communication society by the internet, the way how to send data fast with a little loss becomes an important transportation problem. A generalized maximum flow algorithm gives the best solution for the transportation problem that which route is appropriated to exchange data. Therefore, the importance of the maximum flow algorithm is growing more and more. In this paper, we propose a Maximum-Flow Neural Network (MF-NN) in which branch nonlinearity has a saturation characteristic and by which the maximum flow problem can be solved with analog high-speed parallel processing. That is, the proposed neural network for the maximum flow problem can be realized by a nonlinear resistive circuit where each connection weight between nodal neurons has a sigmodal or piece-wise linear function. The parallel hardware of the MF-NN will be easily implemented.

A signal detection system using noise statistical processing is proposed. By approaching the problems of low voltage and high noise from miniaturization of a device from a stochastic point of view, a faint-signal receiving system that can effectively detect subthreshold and noise level signals has been developed. In addition, an alternative to statistical processing is proposed, and would be successfully implemented on a circuit. For the proposed signal detection method, the detection sensitivity was investigated using numerical simulation, and the detection sensitivity was sufficiently high to detect even a signal with a signal-to-inherent-noise ratio of -14 dB. Thus, it is anticipated that the application of this system to an integrated circuit will have a significant impact on signal processing.

This letter derives the packet error rate (PER) in terms of the retry limit and the channel error probability in wireless local area networks (WLANs), when an additional number of retries is allocated to a block of packets to be transmitted. We prove that the lower bound of the PER is the dropping probability which is defined as the probability of any given packet being dropped after its retry limit has been reached.

This paper presents a cache way enabling mechanism using branch target addresses. This mechanism uses branch prediction information to avoid the power consumption due to unnecessary cache way access by enabling only the cache way(s) that should be accessed. The proposed cache way enabling mechanism reduces the power consumption of the instruction cache by 63% without any performance degradation of the processor. An ARM1136 processor simulator and the Synopsys PrimeTime are used to perform the performance/power simulation and static timing analysis of the proposed mechanisms respectively.

Halftoning is an important process to convert a gray scale image into a binary image with black and white pixels. The Direct Binary Search (DBS) is one of the well-known halftoning methods that can generate high quality binary images for middle tone of original gray scale images. However, binary images generated by the DBS have clippings, that is, have no tone in highlights and shadows of original gray scale images. The first contribution of this paper is to show the reason why the DBS generates binary images with clippings, to clarify the range of tone in original images that may have clipping, and to present a clipping-free DBS-based halftoning algorithm. The key idea is to apply the ordered dither using a threshold array generated by DBS-based method, to highlights and shadows, and then use the DBS. The second contribution is to extend the DBS to generate L-level multitone images with each pixel taking one of the intensity levels , , ..., . However, clippings appear in highlights, middle tone, and shadows of generated L-level multitone images. The third contribution of this paper is to modify the multitone version of the DBS to generate a clipping-free L-level multitone images. The resulting multitone images are so good that they reproduce the tones and the details of the original gray scale images very well.

This paper proposes a VoIP (Voice over Internet Protocol) session capacity expansion method that uses periodic packet transmission suppression control for wireless LANs. The proposed method expands the VoIP session capacity of an AP without critically degrading the QoS (Quality of Service) of all stations. Simulation results show the proposed method with 0.5% packet suppression control on each station expands a VoIP session capacity by up to 5% compared to a legacy method while satisfying required QoS for all stations.

In this paper, a novel model of Gaussian pulse propagation in optical fiber is proposed to comprehensively analyze the impact of Group Velocity Dispersion (GVD) on the performance of two-dimensional wavelength hopping/time spreading optical code division multiple access (2-D WH/TS OCDMA) systems. In addition, many noise and interferences, including multiple access interference (MAI), optical beating interference (OBI), and receiver's noise are included in the analysis. Besides, we propose to use the heterodyne detection receiver so that the receiver's sensitivity can be improved. Analytical results show that, under the impact of GVD, the number of supportable users is extremely decreased and the maximum transmission length (i.e. the length at which BER 10-9 can be maintained) is remarkably shortened in the case of normal single mode fiber (ITU-T G.652) is used. The main factor that limits the system performance is time skewing. In addition, we show how the impact of GVD is relieved by dispersion-shifted fiber (ITU-T G.653). For example, a system with 321 Gbit/s users can achieve a maximum transmission length of 111 km when transmitted optical power per bit is -5 dBm.

A new in vitro experimental tool was developed to study the mechanism of the ultrasonic closing clicks' genesis of mechanical heart valves. Since the newly developed tester adopted compressed air flow directly instead of the blood analog fluid to drive the mechanical heart valve, it is not possibe to generate any cavitation. Closing clicks were measured with a small accelerometer at the surface of the valve holder made of silicone rubber. Ultrasonic closing clicks as well as audible closing clicks, similar to those measured clinically, could be observed using this setup. Thus, it was confirmed that the ultrasonic closing clicks can be generated without the existence of cavitation. Simultaneous measurements of the valve motion were made with a high-speed video camera, and the analysis of the video frames and clicks showed that higher frequency signal components of more than 50 kHz could be generated only at the instant of the closure, which means the collision of the occluder with the housing. Eighteen miniature accelerometers with an area of one square millimeter were developed and stuck on the housing to monitor the distribution of the housing vibrations in detail, and it was found that the vibrations correspond to the ultrasonic closing clicks propagated from the valve stop: the collision point of the occluder with the housing. This fact indicated that the generation of ultrasonic closing clicks are limited to the small area of the collision. From those results, it was concluded that the major origin of the ultrasonic closing clicks' genesis should be the collision of the occluder with the housing.

A deep submicron semiconductor technology has increased process variations. This fact makes the estimate of the worst-case design margin difficult. In order to realize robust designs, we are investigating such a typical-case design methodology, which we call Constructive Timing Violation (CTV). In the CTV-based design, we can relax timing constraints. However, relaxing timing constraints might cause some timing errors. While we have applied the CTV-based design to a processor, unfortunately, the timing error recovery has serious impact on processor performance. In this paper, we investigate enhancement techniques of the CTV-based design. In addition, in order to accurately evaluate the CTV-based design, we build a co-simulation framework to consider circuit delay at the architectural level. From the co-simulation results, we find the performance penalty is significantly reduced by the enhancement techniques.

Sensor networks have promising applications such as battlefield surveillance, biological detection, and emergency navigation, etc. Crucial problems in sensor networks are energy-efficiency and collision avoidance in wireless communication. To deal with the problems, we consider a self-stabilizing solution to the construction of k disjoint sense-sleep trees, where range adjustment and the use of GPS are allowed. Each root is determined by its identifier and is distinguished by its color, the identification of a tree. Using a dominating k-partition rule, each non-root node first determines a color irrelevant to the root. Then, the non-root node determines a parent node that is equally colored with minimal distance. If there is no appropriate parent, the range is extended or shrunk until the nearest parent is determined. Finally, we perform a simulation.

This paper introduces a step response based method to predict the eye diagram for high-speed signaling systems. The method is able to predict accurately the worst-case eye diagram, and is orders of magnitude faster than the method using SPICE simulation with input of random bits. The proposed method is applied to search optimal equalizer parameters for lower-power transmission-line signaling schemes. Simulation results show that the scheme with driver-side series capacitor achieves much better eye area, and signaling throughput than the conventional scheme with only resistive terminations.

This paper proposes a software-controllable variable line-size (SC-VLS) cache architecture for low power embedded systems. High bandwidth between logic and a DRAM is realized by means of advanced integrated technology. System-in-Silicon is one of the architectural frameworks to realize the high bandwidth. An ASIC and a specific SRAM are mounted onto a silicon interposer. Each chip is connected to the silicon interposer by eutectic solder bumps. In the framework, it is important to reduce the DRAM energy consumption. The specific DRAM needs a small cache memory to improve the performance. We exploit the cache to reduce the DRAM energy consumption. During application program executions, an adequate cache line size which produces the lowest cache miss ratio is varied because the amount of spatial locality of memory references changes. If we employ a large cache line size, we can expect the effect of prefetching. However, the DRAM energy consumption is larger than a small line size because of the huge number of banks are accessed. The SC-VLS cache is able to change a line size to an adequate one at runtime with a small area and power overheads. We analyze the adequate line size and insert line size change instructions at the beginning of each function of a target program before executing the program. In our evaluation, it is observed that the SC-VLS cache reduces the DRAM energy consumption up to 88%, compared to a conventional cache with fixed 256 B lines.

The capacity of multiuser OFDM systems can be maximized by allocating resources (subcarrier and power) to the user with the highest instantaneous channel gain. This assumes complete channel state information (CSI) at the transmitter, which is achieved by every user reporting its CSI for all subcarriers to the transmitter via feedback channel. In practice, due to the limited capacity of the feedback channel, the completeness of CSI may be severely restricted especially with a large number of users transmitting a large amount of feedback information. In order to reduce the amount of feedback information while preserving the maximal capacity, quality based CSI feedback (QCF) is proposed in this letter. The system capacity is derived with QCF and compared with that of full CSI feedback. The results show that QCF successfully reduces the amount of feedback information with little capacity loss.

In this letter, a pre-processed lattice reduction (PLR) scheme is developed for the lattice reduction aided (LRA) detection of multiple input multiple-output (MIMO) systems in spatially correlated channel. The PLR computes the LLL-reduced matrix of the equivalent matrix, which is the product of the present channel matrix and unimodular transformation matrix for LR of spatial correlation matrix, rather than the present channel matrix itself. In conjunction with PLR followed by recursive lattice reduction (RLR) scheme [7], pre-processed RLR (PRLR) is shown to efficiently carry out the LR of the channel matrix, especially for the burst packet message in spatially and temporally correlated channel while matching the performance of conventional LRA detection.

A PN junction current model for advanced MOSFETs is proposed and implemented into HiSIM2, a complete surface-potential-based MOSFET model. The model includes forward diode currents and reverse diode currents, and requires a total of 13 model parameters covering all bias conditions. Model simulation results reproduce measurements for different device geometries over a wide range of bias and temperature values.

Circuits utilizing advanced process technologies have to correctly account for device parameter variation to optimize its performance. In this paper, analytical formulas for evaluating path delay variation of Multi-Threshold CMOS (MTCMOS) circuits are proposed. The proposed formulas express path delay and its variation as functions of process parameters that are determined by fabrication technology (threshold voltage, carrier mobility, etc.) and the circuit parameters that are determined by circuit structure (equivalent load capacitance and the concurrently switching gates). Two procedures to obtain the circuit parameter sets necessary in the calculation of the proposed formulas are also defined. With the proposed formulas, calculation time of a path delay variation becomes three orders faster than that of Monte-Carlo simulation. The proposed formulas are suitably applied for efficient design of MTCMOS circuits considering process variation.

In this paper, we propose an effective Web cache admission control algorithm. By selectively admitting objects into the cache, the proposed algorithm can significantly reduce the amount of disk I/O on a Web cache while maintaining a high hit ratio. The proposed algorithm adaptively adjusts its own admission control parameter, requiring no user-supplied parameters. Through extensive experiments, we show the effectiveness of the proposed algorithm.