A scheduling algorithm aims to minimize the overall execution time of the program by properly allocating and arranging the execution order of the tasks on the core processors such that the precedence constraints among the tasks are preserved. In this paper, we present a new scheduling algorithm by using geometry analysis of the Task Precedence Graph (TPG) based on A* search technique and uses a computationally efficient cost function for guiding the search with reduced complexity and pruning techniques to produce an optimal solution for the allocation/scheduling problem of a parallel application to parallel and multiprocessor architecture. The main goal of this work is to significantly reduce the search space and achieve the optimality or near optimal solution. We implemented the algorithm on general task graph problems that are processed on most of related search work and obtain the optimal scheduling with a small number of states. The proposed algorithm reduced the exhaustive search by at least 50% of search space. The viability and potential of the proposed algorithm is demonstrated by an illustrative example.

Complex bandpass ΔΣAD modulators can provide superior performance to a pair of real bandpass ΔΣAD modulators of the same order. They process just input I and Q signals, not image signals, and AD conversion can be realized with low power dissipation, so that they are desirable for such low-IF receiver applications. This paper proposes a new architecture for complex bandpass Δ ΣAD modulators with cross-noise-coupled topology, which effectively raises the order of the complex modulator and achieves higher SQNDR (Signal to Quantization Noise and Distortion Ratio) with low power dissipation. By providing the cross-coupled quantization noise injection to internal I and Q paths, noise coupling between two quantizers can be realized in complex form, which enhances the order of noise shaping in complex domain, and provides a higher-order NTF using a lower-order loop filter in the complex ΔΣAD modulator. Proposed higher-order modulator can be realized just by adding some passive capacitors and switches, the additional integrator circuit composed of an operational amplifier is not necessary, and the performance of the complex modulator can be effectively raised without more power dissipation. We have performed simulation with MATLAB to verify the effectiveness of the proposed architecture. The simulation results show that the proposed architecture can achieve the realization of higher-order enhancement, and improve SQNDR of the complex bandpass ΔΣAD modulator.

Equipping wireless routers with multiple radios further improves the capacity by transmitting over multiple radios simultaneously using orthogonal channels. Efficient channel assignment schemes can greatly alleviate the interference effect of nearby transmissions. One of the distinctive features in wireless multi-hop networks is the lack of any central controller, in which each node makes its own decisions. Therefore, fully cooperative behaviors, such as cooperation for increasing link capacity, alleviating interferences for one another, might not be directly applied. In this paper, we aim to present some applications to show how such a framework can be invoked to design efficient channel assignment algorithms in a non-cooperative, topology-blind environment as well as in environments where the competing players share perfect information about channel usage and topology environment and so on. Simulation results are presented to illustrate the effectiveness of the algorithms.

In advance of network communication society by the internet, the way how to send data fast with a little loss becomes an important transportation problem. A generalized maximum flow algorithm gives the best solution for the transportation problem that which route is appropriated to exchange data. Therefore, the importance of the maximum flow algorithm is growing more and more. In this paper, we propose a Maximum-Flow Neural Network (MF-NN) in which branch nonlinearity has a saturation characteristic and by which the maximum flow problem can be solved with analog high-speed parallel processing. That is, the proposed neural network for the maximum flow problem can be realized by a nonlinear resistive circuit where each connection weight between nodal neurons has a sigmodal or piece-wise linear function. The parallel hardware of the MF-NN will be easily implemented.

A new in vitro experimental tool was developed to study the mechanism of the ultrasonic closing clicks' genesis of mechanical heart valves. Since the newly developed tester adopted compressed air flow directly instead of the blood analog fluid to drive the mechanical heart valve, it is not possibe to generate any cavitation. Closing clicks were measured with a small accelerometer at the surface of the valve holder made of silicone rubber. Ultrasonic closing clicks as well as audible closing clicks, similar to those measured clinically, could be observed using this setup. Thus, it was confirmed that the ultrasonic closing clicks can be generated without the existence of cavitation. Simultaneous measurements of the valve motion were made with a high-speed video camera, and the analysis of the video frames and clicks showed that higher frequency signal components of more than 50 kHz could be generated only at the instant of the closure, which means the collision of the occluder with the housing. Eighteen miniature accelerometers with an area of one square millimeter were developed and stuck on the housing to monitor the distribution of the housing vibrations in detail, and it was found that the vibrations correspond to the ultrasonic closing clicks propagated from the valve stop: the collision point of the occluder with the housing. This fact indicated that the generation of ultrasonic closing clicks are limited to the small area of the collision. From those results, it was concluded that the major origin of the ultrasonic closing clicks' genesis should be the collision of the occluder with the housing.

A signal detection system using noise statistical processing is proposed. By approaching the problems of low voltage and high noise from miniaturization of a device from a stochastic point of view, a faint-signal receiving system that can effectively detect subthreshold and noise level signals has been developed. In addition, an alternative to statistical processing is proposed, and would be successfully implemented on a circuit. For the proposed signal detection method, the detection sensitivity was investigated using numerical simulation, and the detection sensitivity was sufficiently high to detect even a signal with a signal-to-inherent-noise ratio of -14 dB. Thus, it is anticipated that the application of this system to an integrated circuit will have a significant impact on signal processing.

This paper focuses on the collaborative learning of mathematics in which learners effectively acquire knowledge of common exercises through discussion with other learners. During collaborative learning, learners sometimes cannot solve exercises successfully, because they cannot derive answers by themselves or they hesitate to propose answers through discussion. To cope with such situations, this paper proposes two support functions using diagrams to encourage active discussion, since diagrams are often used to graphically illustrate mathematical concepts. One function indicates the differences between learner diagrams and the group diagram in order to encourage participation in discussions. To compare the characteristics of diagrams drawn by different learners, internal representation of the diagram, which consists of types of figures and remarkable relations to other figures, is introduced. The other function provides hints in the group diagram so that all learners can consider their answers collaboratively through discussions. Since preparing hints for all exercises is difficult, rules for drawing supplementary figures, which are general methods for drawing supplementary figures that correspond to individual answering methods/formulas, are also developed. By applying available rules to current group diagram, appropriate supplementary figures that can solve current learning situations may be generated. The experimental results showed that the generated hints successfully increased the number of utterances in the groups. Moreover, learners were also able to derive answers by themselves and tended to propose more opinions in discussions when the uniqueness of their diagrams was indicated.

Process variation is becoming a primal concern in timing closure of LSI (Large Scale Integrated Circuit) with the progress of process technology scaling. To overcome this problem, SSTA (Statistical Static Timing Analysis) has been intensively studied since it is expected to be one of the most efficient ways for performance estimation. In this paper, we study variation of output transition-time. We firstly clarify that the transition-time variation can not be expressed accurately by a conventional first-order sensitivity-based approach in the case that the input transition-time is slow and the output load is small. We secondly reveal quadratic dependence of the output transition-time to operating margin in voltage. We finally propose a procedure through which the estimation of output transition-time becomes continuously accurate in wide range of input transition-time and output load combinations.

Tracking a large quantity of moving target tags simultaneously is essential for the localization and guidance of people in welfare facilities like hospitals and sanatoriums for the aged. The locating system using active RFID technology consists of a number of fixed RFID readers and tags carried by the target objects, or senior people. We compare the performances of several determination algorithms which use the power measurement of received signals emitted by the moving active RFID tags. This letter presents a study on the effect of collision in tracking large quantities of objects based on active RFID real time location system (RTLS). Traditional trilateration, fingerprinting, and well-known LANDMARC algorithm are evaluated and compared with varying number of moving tags through the SystemC-based computer simulation. From the simulation, we show the tradeoff relationship between the number of moving tags and estimation accuracy.

A PN junction current model for advanced MOSFETs is proposed and implemented into HiSIM2, a complete surface-potential-based MOSFET model. The model includes forward diode currents and reverse diode currents, and requires a total of 13 model parameters covering all bias conditions. Model simulation results reproduce measurements for different device geometries over a wide range of bias and temperature values.

We propose an MRAM macro architecture for SoCs to reduce their area size. The shared write-selection transistor (SWST) architecture is based on 2T1MTJ MRAM cell technology, which enables the same fast access time with a smaller cell area than that of 6T SRAMs. We designed a 4-Mb macro using the SWST architecture with a 0.15-µm CMOS process and a 0.24-µm MRAM process. The macro cell array consists of 81T64MTJ cell array elements, each storing 64 bits of data. The area size is reduced by more than 30%. By introducing a leakage-replication (LR) read scheme, a wide read margin on a test chip is accomplished and 50-ns access time is achieved with SPICE simulation. The 2T1MTJ macro and 81T64MTJ macro can be integrated into a single SoC.

The capacity of multiuser OFDM systems can be maximized by allocating resources (subcarrier and power) to the user with the highest instantaneous channel gain. This assumes complete channel state information (CSI) at the transmitter, which is achieved by every user reporting its CSI for all subcarriers to the transmitter via feedback channel. In practice, due to the limited capacity of the feedback channel, the completeness of CSI may be severely restricted especially with a large number of users transmitting a large amount of feedback information. In order to reduce the amount of feedback information while preserving the maximal capacity, quality based CSI feedback (QCF) is proposed in this letter. The system capacity is derived with QCF and compared with that of full CSI feedback. The results show that QCF successfully reduces the amount of feedback information with little capacity loss.

The problem of analyzing transient in transmission line circuits is studied with emphasis on obtaining the transient voltage and current distributions. A new method for solving Telegrapher equation that characterizes the uniform transmission lines is presented. It not only gives the time domain solution of the line terminal voltage and current, but also their distributions within the lines. The method achieves its goal by treating the voltage and current distributions as distributed state variables and transforms the Telegrapher equation into an ordinary differential equation. This allows the coupled transmission lines to be treated as a single component that behaves like other lumped dynamic components, such as capacitors and inductors. Using Backward Differentiation Formulae for time discretization, the transmission line component is converted to its time domain companion model, from which its local truncation error for time step control can be derived. As the shapes of the voltage and current distributions get more complicated with time, they can be approximated by piecewise exponential functions with controllable accuracy. A segmentation algorithm is thus devised so that the line is dynamically bisected to guarantee that the total piecewise exponential approximation error is only a small fraction of the local truncation error. Using this approach, the user can see the line voltage and current at any point and time freely without explicitly segment the line before starting the simulation.

This paper introduces a step response based method to predict the eye diagram for high-speed signaling systems. The method is able to predict accurately the worst-case eye diagram, and is orders of magnitude faster than the method using SPICE simulation with input of random bits. The proposed method is applied to search optimal equalizer parameters for lower-power transmission-line signaling schemes. Simulation results show that the scheme with driver-side series capacitor achieves much better eye area, and signaling throughput than the conventional scheme with only resistive terminations.

In this letter, a pre-processed lattice reduction (PLR) scheme is developed for the lattice reduction aided (LRA) detection of multiple input multiple-output (MIMO) systems in spatially correlated channel. The PLR computes the LLL-reduced matrix of the equivalent matrix, which is the product of the present channel matrix and unimodular transformation matrix for LR of spatial correlation matrix, rather than the present channel matrix itself. In conjunction with PLR followed by recursive lattice reduction (RLR) scheme [7], pre-processed RLR (PRLR) is shown to efficiently carry out the LR of the channel matrix, especially for the burst packet message in spatially and temporally correlated channel while matching the performance of conventional LRA detection.

Three-dimensional integrated circuits (3-D ICs), i.e., stacked dies, can alleviate the interconnect problem coming with the decreasing feature size and increasing integration density, and promise a solution to heterogenous integration. The vertical connection, which is generally implemented by the through-the-silicon via, is a key technology for 3-D ICs. In this paper, given 3-D circuit placement or floorplan results with white space reserved between blocks for inter-layer interconnections, we proposed methods for assigning inter-layer signal via locations. Introducing a grid structure on the chip, the inter-layer via assignment of two-layer chips can be optimally solved by a convex-cost max-flow formulation with signal via congestion optimized. As for 3-D ICs with three or more layers, the inter-layer signal via assignment is modeled as an integral min-cost multi-commodity flow problem, which is solved by a heuristic method based on the lagrangian relaxation. Relaxing the capacity constraints in the grids, we transfer the min-cost multi-commodity flow problem to a sequence of lagrangian sub-problems, which are solved by finding a sequence of shortest paths. The complexity of solving a lagrangian sub-problem is O(nntng2), where nnt is the number of nets and ng is the number of grids on one chip layer. The experimental results demonstrated the effectiveness of the method.

A new analog mismatch model in circuit level has been developed. MOS transistor's small signal parameters are modeled in term of their matching character for both strong- and weak-inversion operations. Mismatch analysis on basic CMOS amplifiers are conducted with proposed model and Monte Carlo SPICE simulations. We successfully derived simple analytical formula on performance mismatch for analog CMOS circuits, which is verified to be accurate in using actual analog circuit design, within an average error of less than 10%.

Noise removal in engineering drawing is an important operation performed before other image analysis tasks. Many algorithms have been developed to remove salt-and-pepper noise from document images. Cleaning algorithms should remove noise while keeping the real part of the image unchanged. Some algorithms have disadvantages in cleaning operation that leads to removing of weak features such as short thin lines. Others leave the image with hairy noise attached to image objects. In this article a noise removal procedure called TrackAndMayDel (TAMD) is developed to enhance the noise removal of salt-and-pepper noise in binary images of engineering drawings. The procedure could be integrated with third party algorithms' logic to enhance their ability to remove noise by investigating the structure of pixels that are part of weak features. It can be integrated with other algorithms as a post-processing step to remove noise remaining in the image such as hairy noise attached with graphical elements. An algorithm is proposed by incorporating TAMD in a third party algorithm. Real scanned images from GREC'03 contest are used in the experiment. The images are corrupted by salt-and-pepper noise at 10%, 15%, and 20% levels. An objective performance measure that correlates with human vision as well as MSE and PSNR are used in this experiment. Performance evaluation of the introduced algorithm shows better-quality images compared to other algorithms.

The recognition performance of the conventional 3D face recognition algorithm using ICP (Iterative Closest Point) is degraded for the 3D face data with expression changes. Addressing this problem, we consider the use of the expression-invariant local regions of a face. We find the expression-invariant regions through the distance analysis between 3D face data with the neutral expression and smile, and propose a robust 3D face recognition algorithm using passive stereo vision. We demonstrate efficient recognition performance of the proposed algorithm compared with the conventional ICP-based algorithm through the experiment using a stereo face image database which includes the face images with expression changes.

The high-speed and low-power system LSIs in recent years have crucial need for managing power supply noise so that it might not substantially affect the circuit functionality and performance. The decoupling capacitance is known as an effective measure for suppressing the power supply noise. In this paper, we propose a design methodology for decoupling capacitance budgeting, in which the decoupling capacitance is distributed appropriately over the LSI chip area in order to suppress the power supply noise of each local region. For efficient budgeting, we introduced a new concept of power-capacitance ratio, which is the ratio of power dissipation to capacitance. The proposed method first performs a simplified power supply noise analysis by using a lumped circuit model to determine the total required on-chip capacitance, and calculate the power-capacitance ratio. Then, in the layout design phase, the decoupling capacitance budgeting is performed by using the above power-capacitance ratio as a guideline. The effectiveness of the proposed method was verified by using SPICE simulations on example chip models of 90 nm technology node. The verification results show that, even for a chip with very wide on-chip variation in power density, the proposed method can suppress the power supply noise of each local region effectively.