This paper presents a memory-efficient motion estimation (ME) technique for high-resolution video compression. The main objective is to reduce the external memory access, especially for limited local memory resource. The reduction of memory access can successfully save the notorious power consumption. The key to reduce the memory accesses is based on center-biased algorithm in that the center-biased algorithm performs the motion vector (MV) searching with the minimum search data. While considering the data reusability, the proposed dual-search-windowing (DSW) approaches use the secondary windowing as an option per searching necessity. By doing so, the loading of search windows can be alleviated and hence reduce the required external memory bandwidth. The proposed techniques can save up to 81% of external memory bandwidth and require only 135 MBytes/sec, while the quality degradation is less than 0.2 dB for 720 p HDTV clips coded at 8 Mbits/sec.

An adaptive per-survivor processing maximum likelihood sequence estimation (PSP-MLSE) using state-space based recursive least-squares (RLS) is proposed for rapidly time varying multi-path fading channels. Unlike PSP-MLSE using Kalman filtering, it does not require the knowledge of model statistics, and with an aid of state-space modeling, it has a robust performance to the fade rate, compared to PSP-MLSE using conventional RLS.

This letter presents a novel approach for traffic light detection in a video frame captured by an in-vehicle camera. The algorithm consists of rotated principal component analysis (RPCA), modified amplitude thresholding with respect to the histograms of the PC planes and final filtering with a neural network. The proposed algorithm achieves an average detection rate of 96% and is very robust to variations in the image quality.

A modified successive interference cancellation (SIC) algorithm for orthogonal frequency division multiplexing (OFDM) system is presented. The presented modified SIC algorithm makes use of an index sequence to avoid the subcarriers re-ordering calculation. Furthermore, by combining the SIC with the conventional zero-forcing (ZF) detection, computation complexity of the presented algorithm can be significantly reduced and meanwhile excellent performance can be maintained.

This paper studies the impact of dummy fill for chemical mechanical polishing (CMP)-induced capacitance variation on buffer insertion based on a virtual CMP fill estimation model. Compared with existing methods, our algorithm is more feasible by performing buffer insertion not in post-process but during early physical design. Our contributions are threefold. First, we introduce an improved fast dummy fill amount estimation algorithm based on [4], and use some speedup techniques (tile merging, fill factor and amount assigning) for early estimation. Second, based on some reasonable assumptions, we present an optimum virtual dummy fill method to estimate dummy position and the effect on the interconnect capacitance. Then the dummy fill estimation model was verified by our experiments. Third, we use this model in early buffer insertion after layer assignment considering the effects of dummy fill. Experimental results verified the necessity of early dummy fill estimation and the validity of our algorithm. Buffer insertion considering dummy fill during early physical design is necessary and our algorithm is promising.

Retinopathy of Prematurity (ROP) is an infant disease characterized by increased dilation and tortuosity of the retinal blood vessels. Automatic tortuosity evaluation from retinal digital images is very useful to facilitate an ophthalmologist in the ROP screening and to prevent childhood blindness. This paper proposes a method to automatically classify the image into tortuous and non-tortuous. The process imitates expert ophthalmologists' screening by searching for clearly tortuous vessel segments. First, a skeleton of the retinal blood vessels is extracted from the original infant retinal image using a series of morphological operators. Next, we propose to partition the blood vessels recursively using an adaptive linear interpolation scheme. Finally, the tortuosity is calculated based on the curvature of the resulting vessel segments. The retinal images are then classified into two classes using segments characterized by the highest tortuosity. For an optimal set of training parameters the prediction is as high as 100%.

Optical Burst Switched (OBS) networks are considered as promising candidates for the next generation network architecture which does not need high-speed switch technologies. In OBS networks, contention resolution is one of the significant problems. Generally, setup reservations are operated per burst in OBS networks. To transmit multiple successive bursts successfully, the effective wavelength reservation must be implemented and enhanced network performance must be realized. In the proposed method, when an optical burst is generated and its destination is the same as that of the preceding burst or the path until the destination includes the entire path of the preceding burst, the subsequent burst is assigned to the same wavelength as the preceding burst and transmitted sequentially. The main aim in the proposed method is the efficient use of wavelength resources and the reduction of burst loss probability. We simulate and evaluate the effectiveness of the proposed method. As a result, it is verified that the proposed method can reduce the burst loss probably.

We fabricated both thin film transistors (TFTs) and diodes using zinc oxide (ZnO) and pentacene, and investigated their basic characteristics. We found that field-effect mobility is influenced by the interface state between the semiconductor and dielectric layers. Furthermore, the complementary metal oxide semiconductor (CMOS) inverter using a p-channel pentacene field-effect transistor (FET) and an n-channel ZnO FET showed a relatively high voltage gain (8-12) by optimizing the device structure. The hybrid complementary inverters described here are expected for application in flexible displays, radio frequency identification cards (RFID) tags, and others.

In this paper, we propose a partially-parallel irregular LDPC decoder based on IEEE 802.11n standard targeting high throughput and small area applications. The design is based on a novel sum-delta message passing algorithm characterized as follows: (i) Decoding throughput is greatly improved by utilizing the difference value between the updated and the original value to remove redundant computations. (ii) Registers and memory are optimized to store only the frequently used messages to decrease the hardware cost. (iii) Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200 MHz, with 11% area reduction. The synthesis result also demonstrates the competitiveness to the fully-parallel regular LDPC decoders in terms of the tradeoff between throughput, area and power.

In this paper we introduce new M-ary sequences of length pq, called generalized M-ary related-prime sequences, where p and q are distinct odd primes, and M is a common divisor of p-1 and q-1. We show that their out-of-phase autocorrelation values are upper bounded by the maximum between q-p+1 and 5. We also construct a family of generalized M-ary related-prime sequences and show that the maximum correlation of the proposed sequence family is upper bounded by p+q-1.

Recently much attention has been paid to quantum circuit design to prepare for the future "quantum computation era." Like the conventional logic synthesis, it should be important to verify and analyze the functionalities of generated quantum circuits. For that purpose, we propose an efficient verification method for quantum circuits under a practical restriction. Thanks to the restriction, we can introduce an efficient verification scheme based on decision diagrams called Decision Diagrams for Matrix Functions (DDMFs). Then, we show analytically the advantages of our approach based on DDMFs over the previous verification techniques. In order to introduce DDMFs, we also introduce new concepts, quantum functions and matrix functions, which may also be interesting and useful on their own for designing quantum circuits.

In this letter, we first provide the closed-form exact outage probability of opportunistic single relay selection in decode-and-forward (DF) relaying with the direct source-destination link under arbitrarily distributed Rayleigh fading channels. The signals from the source and the selected relay are combined at the destination by using maximal ratio combining (MRC). We derive the probability density function (PDF) and the cumulative density function (CDF) of received SNR at the destination. Numerical results show that the analytic results exactly match with the simulated ones.

In the context of multiple constant multiplication (MCM) design, we propose a novel common sub-expression elimination (CSE) algorithm that models the optimal synthesis of coefficients into a 0-1 mixed-integer linear programming (MILP) problem with a user-defined generic logic depth constraint. We also propose an efficient solution space, which combines all minimal signed digit (MSD) representations and the shifted sum (difference) of coefficients. In the examples we demonstrate, the combination of the proposed algorithm and solution space gives a better solution comparing to existing algorithms.

This letter presents a novel framework in high-level synthesis where hardware modules synthesized from functions in a given ANSI-C program can call the other software functions in the program. This enables high-level synthesis from C programs that contains calls to hard-to-synthesize functions, such as dynamic memory management, I/O request, or very large and complex functions. A single-thread implementation scheme is shown, whose correctness has been verified through register transfer level simulation.

In wireless sensor networks (WSNs), localization using the received signal strength (RSS) method is famous for easy adaptation and low cost where measuring the distance between sensor nodes. However, in real localization systems, the RSS is strongly affected by many surrounding factors and tends to be unstable, so that it degrades accuracy in distance measurement. In this paper, we propose the angle-referred calibration based RSS method where angle relation between sensor nodes is used to perform the calibration for better performance in distance measurement. As a result, the proposed scheme shows that it can provide high precision.

This paper proposes an efficient design algorithm for power/ground (P/G) network synthesis with dynamic signal consideration, which is mainly caused by Ldi/dt noise and Cdv/dt decoupling capacitance (DECAP) current in the distribution network. To deal with the nonlinear global optimization under synthesis constraints directly, the genetic algorithm (GA) is introduced. The proposed GA-based synthesis method can avoid the linear transformation loss and the restraint condition complexity in current SLP, SQP, ICG, and random-walk methods. In the proposed Hybrid Grid Synthesis algorithm, the dynamic signal is simulated in the gene disturbance process, and Trapezoidal Modified Euler (TME) method is introduced to realize the precise dynamic time step process. We also use a hybrid-SLP method to reduce the genetic execute time and increase the network synthesis efficiency. Experimental results on given power distribution network show the reduction on layout area and execution time compared with current P/G network synthesis methods.

Abdalla et al. proposed a gateway-oriented password-based authenticated key exchange (GPAKE) protocol among a client, a gateway, and an authentication server, where a password is only shared between the client and the authentication server. The goal of their scheme is to securely establish a session key between the client and the gateway by the help of the authentication server without revealing any information on the password to the gateway. Recently, Byun et al. showed that Abdalla et al.'s GPAKE is insecure against undetectable on-line password guessing attacks. They also proposed a modified version to overcome the attacks. In this letter, we point out that Byun et al.'s modified GPAKE protocol is still insecure against the same attacks. We then make a suggestion for improvement.

As the semiconductor feature size decreases, the crosstalk due to the capacitive coupling of interconnects influences signal propagation delay more seriously. Moreover, the increase of the operating frequency further emphasizes the necessity of more accurate timing analysis. In this paper, we propose new gate models to calculate gate output waveforms under crosstalk effects, which can be used for gate-level delay estimation. We classify the operation modes of metal-oxide-semiconductor (MOS) devices of a gate into 3 regions, and then develop simple linear models for each region. In addition, we present a non-iterative gate modeling method that is more efficient than previous iterative methods. In the experiments, the proposed method exhibits a maximum error of 10.70% and an average error of 2.63% when it computes the 50% delays of two or three complementary MOS (CMOS) inverters driving parallel wires. In comparison, the existing method has a maximum error of 25.94% and an average error of 3.62% under these conditions.

This paper proposes a closed-form eye-diagram model for on-chip distortionless transmission lines with intentionally inserted shunt conductance. We derive expressions of eye-opening both in voltage and time, by assuming a piece-wise linear waveform model. The model is experimentally verified with various length, shunt conductance and resistive termination. We also apply the proposed model to design space exploration, and demonstrate that the proposed model helps estimate the optimal shunt conductance and resistive termination according to required signaling length and throughput.

Threshold Inverter Quantization (TIQ) technique has been gaining its importance in high speed flash A/D converters due to its fast data conversion speed. It eliminates the need of resistor ladders for reference voltages generation which requires substantial power consumption. The key to TIQ comparators design is to generate 2n - 1 different sized TIQ comparators for an n-bit A/D converter. This paper presents a highly efficient TIQ comparator design methodology based on an analytical model as well as SPICE simulation experimental model. One can find any sets of TIQ comparators efficiently using the proposed method. A 6-bit TIQ A/D converter has been designed in a 0.18 µm standard CMOS technology using the proposed method, and compared to the previous measured results in order to verify the proposed methodology.