In this paper, a novel model of Gaussian pulse propagation in optical fiber is proposed to comprehensively analyze the impact of Group Velocity Dispersion (GVD) on the performance of two-dimensional wavelength hopping/time spreading optical code division multiple access (2-D WH/TS OCDMA) systems. In addition, many noise and interferences, including multiple access interference (MAI), optical beating interference (OBI), and receiver's noise are included in the analysis. Besides, we propose to use the heterodyne detection receiver so that the receiver's sensitivity can be improved. Analytical results show that, under the impact of GVD, the number of supportable users is extremely decreased and the maximum transmission length (i.e. the length at which BER 10-9 can be maintained) is remarkably shortened in the case of normal single mode fiber (ITU-T G.652) is used. The main factor that limits the system performance is time skewing. In addition, we show how the impact of GVD is relieved by dispersion-shifted fiber (ITU-T G.653). For example, a system with 321 Gbit/s users can achieve a maximum transmission length of 111 km when transmitted optical power per bit is -5 dBm.

A new analog mismatch model in circuit level has been developed. MOS transistor's small signal parameters are modeled in term of their matching character for both strong- and weak-inversion operations. Mismatch analysis on basic CMOS amplifiers are conducted with proposed model and Monte Carlo SPICE simulations. We successfully derived simple analytical formula on performance mismatch for analog CMOS circuits, which is verified to be accurate in using actual analog circuit design, within an average error of less than 10%.

Three-dimensional integrated circuits (3-D ICs), i.e., stacked dies, can alleviate the interconnect problem coming with the decreasing feature size and increasing integration density, and promise a solution to heterogenous integration. The vertical connection, which is generally implemented by the through-the-silicon via, is a key technology for 3-D ICs. In this paper, given 3-D circuit placement or floorplan results with white space reserved between blocks for inter-layer interconnections, we proposed methods for assigning inter-layer signal via locations. Introducing a grid structure on the chip, the inter-layer via assignment of two-layer chips can be optimally solved by a convex-cost max-flow formulation with signal via congestion optimized. As for 3-D ICs with three or more layers, the inter-layer signal via assignment is modeled as an integral min-cost multi-commodity flow problem, which is solved by a heuristic method based on the lagrangian relaxation. Relaxing the capacity constraints in the grids, we transfer the min-cost multi-commodity flow problem to a sequence of lagrangian sub-problems, which are solved by finding a sequence of shortest paths. The complexity of solving a lagrangian sub-problem is O(nntng2), where nnt is the number of nets and ng is the number of grids on one chip layer. The experimental results demonstrated the effectiveness of the method.

This paper presents a cache way enabling mechanism using branch target addresses. This mechanism uses branch prediction information to avoid the power consumption due to unnecessary cache way access by enabling only the cache way(s) that should be accessed. The proposed cache way enabling mechanism reduces the power consumption of the instruction cache by 63% without any performance degradation of the processor. An ARM1136 processor simulator and the Synopsys PrimeTime are used to perform the performance/power simulation and static timing analysis of the proposed mechanisms respectively.

Circuits utilizing advanced process technologies have to correctly account for device parameter variation to optimize its performance. In this paper, analytical formulas for evaluating path delay variation of Multi-Threshold CMOS (MTCMOS) circuits are proposed. The proposed formulas express path delay and its variation as functions of process parameters that are determined by fabrication technology (threshold voltage, carrier mobility, etc.) and the circuit parameters that are determined by circuit structure (equivalent load capacitance and the concurrently switching gates). Two procedures to obtain the circuit parameter sets necessary in the calculation of the proposed formulas are also defined. With the proposed formulas, calculation time of a path delay variation becomes three orders faster than that of Monte-Carlo simulation. The proposed formulas are suitably applied for efficient design of MTCMOS circuits considering process variation.

This paper proposes a VoIP (Voice over Internet Protocol) session capacity expansion method that uses periodic packet transmission suppression control for wireless LANs. The proposed method expands the VoIP session capacity of an AP without critically degrading the QoS (Quality of Service) of all stations. Simulation results show the proposed method with 0.5% packet suppression control on each station expands a VoIP session capacity by up to 5% compared to a legacy method while satisfying required QoS for all stations.

This paper proposes a software-controllable variable line-size (SC-VLS) cache architecture for low power embedded systems. High bandwidth between logic and a DRAM is realized by means of advanced integrated technology. System-in-Silicon is one of the architectural frameworks to realize the high bandwidth. An ASIC and a specific SRAM are mounted onto a silicon interposer. Each chip is connected to the silicon interposer by eutectic solder bumps. In the framework, it is important to reduce the DRAM energy consumption. The specific DRAM needs a small cache memory to improve the performance. We exploit the cache to reduce the DRAM energy consumption. During application program executions, an adequate cache line size which produces the lowest cache miss ratio is varied because the amount of spatial locality of memory references changes. If we employ a large cache line size, we can expect the effect of prefetching. However, the DRAM energy consumption is larger than a small line size because of the huge number of banks are accessed. The SC-VLS cache is able to change a line size to an adequate one at runtime with a small area and power overheads. We analyze the adequate line size and insert line size change instructions at the beginning of each function of a target program before executing the program. In our evaluation, it is observed that the SC-VLS cache reduces the DRAM energy consumption up to 88%, compared to a conventional cache with fixed 256 B lines.

An on-chip CMOS preamplifier for direct signal readout from an electret capacitor microphone has been designed with high immunity to common-mode and supply noise. The Gm-Opamp-RC based high impedance preamplifier helps to remove all disadvantages of the conventional JFET based amplifier and can drive a following switched-capacitor sigma-delta modulator in order to realize a compact digital electret microphone. The proposed chip is designed based on 0.18 µm CMOS technology, and the simulation results show 86 dB of dynamic range with 4.5 µVrms of input-referred noise for an audio bandwidth of 20 kHz and a total harmonic distortion (THD) of 1% at 90 mVrms input. Power supply rejection ratio (PSRR) and common-mode rejection ration (CMRR) are more than 95 dB at 1 kHz. The proposed design dissipates 125 µA and can operate over a wide supply voltage range of 1.6 V to 3.3 V.

A deep submicron semiconductor technology has increased process variations. This fact makes the estimate of the worst-case design margin difficult. In order to realize robust designs, we are investigating such a typical-case design methodology, which we call Constructive Timing Violation (CTV). In the CTV-based design, we can relax timing constraints. However, relaxing timing constraints might cause some timing errors. While we have applied the CTV-based design to a processor, unfortunately, the timing error recovery has serious impact on processor performance. In this paper, we investigate enhancement techniques of the CTV-based design. In addition, in order to accurately evaluate the CTV-based design, we build a co-simulation framework to consider circuit delay at the architectural level. From the co-simulation results, we find the performance penalty is significantly reduced by the enhancement techniques.

Noise removal in engineering drawing is an important operation performed before other image analysis tasks. Many algorithms have been developed to remove salt-and-pepper noise from document images. Cleaning algorithms should remove noise while keeping the real part of the image unchanged. Some algorithms have disadvantages in cleaning operation that leads to removing of weak features such as short thin lines. Others leave the image with hairy noise attached to image objects. In this article a noise removal procedure called TrackAndMayDel (TAMD) is developed to enhance the noise removal of salt-and-pepper noise in binary images of engineering drawings. The procedure could be integrated with third party algorithms' logic to enhance their ability to remove noise by investigating the structure of pixels that are part of weak features. It can be integrated with other algorithms as a post-processing step to remove noise remaining in the image such as hairy noise attached with graphical elements. An algorithm is proposed by incorporating TAMD in a third party algorithm. Real scanned images from GREC'03 contest are used in the experiment. The images are corrupted by salt-and-pepper noise at 10%, 15%, and 20% levels. An objective performance measure that correlates with human vision as well as MSE and PSNR are used in this experiment. Performance evaluation of the introduced algorithm shows better-quality images compared to other algorithms.

In advance of network communication society by the internet, the way how to send data fast with a little loss becomes an important transportation problem. A generalized maximum flow algorithm gives the best solution for the transportation problem that which route is appropriated to exchange data. Therefore, the importance of the maximum flow algorithm is growing more and more. In this paper, we propose a Maximum-Flow Neural Network (MF-NN) in which branch nonlinearity has a saturation characteristic and by which the maximum flow problem can be solved with analog high-speed parallel processing. That is, the proposed neural network for the maximum flow problem can be realized by a nonlinear resistive circuit where each connection weight between nodal neurons has a sigmodal or piece-wise linear function. The parallel hardware of the MF-NN will be easily implemented.

A typical feature of MANETs is that network topology is dynamically changed by node movement. When we execute state transition testing for such protocols, first we draw the Finite State Machine (FSM) with respect to each number of neighbor nodes. Next, we create the state transition matrix from the FSMs. Then, we generate test cases from the state transition matrix. However, the state transition matrix is getting much large because the number of states and the number of transitions increase explosively with increase of the number of neighbor nodes. As a result, the number of test cases increases, too. In this paper, we propose a new method to reduce the number of test cases by using equivalent division method. In this method, we decide a representative input to each state, which is selected from equivalent inputs to the states. By using our proposed method, we can generate state transition matrix which is hard to affect increasing the number of neighbor nodes. As a consequence, the number of test cases can be reduced.

In RFID systems, collision resolution is a significant issue in fast tag identification. This letter presents a dynamic frame-slotted ALOHA algorithm that uses a collision factor (DFSA-CF). This method enables fast tag identification by estimating the next frame size with the collision factor in the current frame. Simulation results show that the proposed method reduces slot times Required for RFID identification. When the number of tags is larger than the frame size, the efficiency of the proposed method is greater than those of conventional algorithms.

This paper presents methods for controlling the intensity of emotional expressions and speaking styles of an arbitrary speaker's synthetic speech by using a small amount of his/her speech data in HMM-based speech synthesis. Model adaptation approaches are introduced into the style control technique based on the multiple-regression hidden semi-Markov model (MRHSMM). Two different approaches are proposed for training a target speaker's MRHSMMs. The first one is MRHSMM-based model adaptation in which the pretrained MRHSMM is adapted to the target speaker's model. For this purpose, we formulate the MLLR adaptation algorithm for the MRHSMM. The second method utilizes simultaneous adaptation of speaker and style from an average voice model to obtain the target speaker's style-dependent HSMMs which are used for the initialization of the MRHSMM. From the result of subjective evaluation using adaptation data of 50 sentences of each style, we show that the proposed methods outperform the conventional speaker-dependent model training when using the same size of speech data of the target speaker.

In this paper, we derive the exact average symbol error probability (SEP) of M-ary phase-shift keying and quadrature amplitude modulation signals over Stacy fading channels. The Stacy fading is modelled by a three-parameter generalized gamma or physically α-µ fading distribution, spanning a wide range of small-scale fading such as Rayleigh, Nakagami-m, and Weibull fading. The average SEP is generally expressed in terms of (generalized) Fox's H-functions, which particularizes to the previously known results for some special cases. We further analyze the diversity order achieved by orthogonal space-time block codes in multiple-input multiple-output (MIMO) Stacy fading channels.

Recently, a promising packet forwarding architecture COPE was proposed to essentially improve the throughput of multihop wireless networks, where each network node can intelligently encode multiple packets together and forward them in a single transmission. However, COPE is still in its infancy and has the following limitations: (1) COPE adopts the FIFO packet scheduling and thus does not provide different priorities for different types of packets. (2) COPE simply classifies all packets destined to the same nexthop into small-size or large-size virtual queues and examines only the head packet of each virtual queue to find coding solutions. Such a queueing structure will lose some potential coding opportunities, because among packets destined to the same nexthop at most two packets (the head packets of small-size and large-size queues) will be examined in the coding process, regardless of the number of flows. (3) The coding algorithm adopted in COPE is fast but cannot always find good solutions. In order to address the above limitations, in this paper we first present a new queueing structure for COPE, which can provide more potential coding opportunities, and then propose a new packet scheduling algorithm for this queueing structure to assign different priorities to different types of packets. Finally, we propose an efficient coding algorithm to find appropriate packets for coding. Simulation results demonstrate that this new COPE architecture can further greatly improve the node transmission efficiency.

An improved dual-band design method is presented for the 180coupler. It uses the non-uniform impedance ring structure for the arbitrary power division and a π-shaped branch for the dual-band operation The increased design freedom offered by the proposed structure helps to extend the useful dual-band operation range.

A method is proposed for estimating code and carrier phase parameters of GNSS reflected signals in low SNR (signal-to-noise ratio) environments. Simulation results show that the multipath impact on code and carrier with 0.022 C/A chips delay can be estimated in 0 dB SNR in the condition of 46 MHz sampling rate.

We report on the spurious suppression effect in low-microwave power transmitters by high temperature superconducting (HTS) bandpass filters (BPFs) which are promising for devices requiring BPFs with high-frequency selectivity. Some of the major issues on the power BPFs with HTS planar circuits for wireless communication applications are reviewed. As a case study for the HTS filter and its spurious suppression effect, this paper describes an example of the measured power spectrum density (PSD) on the suppression effect by one of our developed power BPFs with YBCO films for the 5 GHz band. It was designed with equivalent cascade resonators of 16 poles. We demonstrated the effect by HTS power filter in a power amplifier for the 5 GHz band.

In some applications, a short private exponent d is chosen to improve the decryption or signing process for RSA public key cryptosystem. However, in a typical RSA, if the private exponent d is selected first, the public exponent e should be of the same order of magnitude as φ(N). Sun et al. devised three RSA variants using unbalanced prime factors p and q to lower the computational cost. Unfortunately, Durfee & Nguyen broke the illustrated instances of the first and third variants by solving small roots to trivariate modular polynomial equations. They also indicated that the instances with unbalanced primes p and q are more insecure than the instances with balanced p and q. This investigation focuses on designing a new RSA variant with balanced p and q, and short exponents d and e, to improve the security of an RSA variant against the Durfee & Nguyen's attack, and the other existing attacks. Furthermore, the proposed variant (Scheme A) is also extended to another RSA variant (Scheme B) in which p and q are balanced, and a trade-off between the lengths of d and e is enable. In addition, we provide the security analysis and feasibility analysis of the proposed schemes.