In this paper, we propose and analyze a multi-level acknowledgement scheme for hybrid ARQ (H-ARQ) systems, which modifies the general ACK/NAK signals to represent multilevel information. For instance, the other signals except the ACK/NAK signals may be used for scheduling of retransmission in the H-ARQ scheme, which results in increasing the resolution of the uplink channel estimation signals. Simulation results demonstrate that when the retransmission interval is set to the optimal length, the proposed H-ARQ scheme shows a 0.5-2 dB gain with properly selected parameters.

This paper reexamines reflection and transmission of a TE plane wave from a two-dimensional random slab discussed in the previous paper [IEICE Trans. Electron., Vol.E79-C, no.10, pp.1327-1333, October 1996] by means of the stochastic functional approach with the multiply renormalizing approximation. A random wavefield representation is explicitly shown in terms of a Wiener-Hermite expansion. The first-order incoherent scattering cross section and the optical theorem are numerically calculated. Enhanced scattering as gentle peaks or dips on the angular distribution of the incoherent scattering is reconfirmed in the directions of reflection and backscattering, and is newly found in the directions of forward scattering and 'symmetrical forward scattering.' The mechanism of enhanced scattering is deeply discussed.

Most routing protocols in MANET use IP addresses as one of the most important routing information. To implement the routing protocol of MANET, the IP assignment in MANET should be solved. Allocating IP addresses is one of current key issues in the MANET, due to the absence of a centralized agent server. Previous methods require a large address space or can not use all the IP addresses of the given IP address space. For that reason, many IP addresses remain unused. To resolve this, we propose an IP address assignment protocol that uses the contiguous IP address assignment strategy without unused IP addresses. Simulations perform on ns-2 and confirm the viability of our protocol.

Both adaptive modulation and diversity combining are attractive techniques to combat fading and these two can be applicable to each digital-modulated symbol in OFDM transmission. In this letter, aiming to combat severe fading more effectively than the adaptive modulation, we theoretically analyze the benefit of a frequency diversity scheme within one OFDM symbol, which is a simple kind of coded OFDM (COFDM) based on IEEE 802.16 protocols. A simple closed form equation of bit error rate (BER) is derived, and then the advantages of correlated diversity gain and interference suppression by the diversity scheme are verified by both theoretical analysis and Monte Carlo simulation.

In this paper, we present a high-performance VC-1 main-profile decoder for high-definition (HD) video applications, which can decode HD 720p video streams with 30 fps at 80 MHz. We implemented the decoder with a one-poly eight-metal 0.13 µm CMOS process, which contains about 261,900 logic gates and on-chip memories of 13.9 KB SRAM and 13.1 KB ROM and occupies an area of about 5.1 mm2. In designing the VC-1 decoder, we used a template-based SoC design flow, with which we performed the design space exploration of the decoder by trying various configurations of communication channels. Moreover, we also describe architectures of the computation blocks optimized to satisfy the requirements of VC-1 HD applications.

In real-time data-dominated communication and multimedia processing applications, a multi-layer memory hierarchy is typically used to enhance the system performance and also to reduce the energy consumption. Savings of dynamic energy can be obtained by accessing frequently used data from smaller on-chip memories rather than from large background memories. This paper focuses on the reduction of the dynamic energy consumption in the memory subsystem of multidimensional signal processing systems, starting from the high-level algorithmic specification of the application. The paper presents a formal model which identifies those parts of arrays more intensely accessed, taking also into account the relative lifetimes of the signals. Tested on a two-layer memory hierarchy, this model led to savings of dynamic energy from 40% to over 70% relative to the energy used in the case of flat memory designs.

In this paper, an alternative approach is presented, to design equalizers (or matching networks) with commensurate (or equal length) transmission lines. The new method automatically yields the matching network topology with characteristic impedances of the commensurate lines. In the implementation process of the new technique first, the driving point impedance data of the matching network is generated by tracing a pre-selected transducer power gain shape, without optimization. Then, it is modelled as a realizable bounded-real input reflection coefficient in Richard domain, which in turn yields the desired equalizer topology with line characteristic impedances. This process results in an excellent initial design for the commercially available computer aided design (CAD) packages to generate final circuit layout for fabrication. An example is given to illustrate the utilization of the new method. It is expected that the proposed design technique is employed as a front-end, to commercially available computer aided design (CAD) packages which generate the actual equalizer circuit layout with physical dimensions for mass production.

This paper presents a high-level synthesis approach to minimize the total power consumption in behavioral synthesis under time and area constraints. The proposed method has two stages, functional unit (FU) energy optimization and interconnect energy optimization. In the first stage, active and inactive energies of the FUs are optimized using a multiple supply and threshold voltage scheme. Genetic algorithm (GA) based simultaneous assignment of supply and threshold voltages and module selection is proposed. The proposed GA based searching method can be used in large size problems to find a near-optimal solution in a reasonable time. In the second stage, interconnects are simplified by increasing their sharing. This is done by exploiting similar data transfer patterns among FUs. The proposed method is evaluated for several benchmarks under 90 nm CMOS technology. The experimental results show that more than 40% of energy savings can be achieved by our proposed method.

Intra coding in H.264/AVC has significantly enhanced video compression efficiency. However, computation complexity increases by the rate-distortion (RD) based mode decision. This paper proposes a novel fast mode decision algorithm in H.264/AVC intra prediction and its VLSI architecture. A novel edge-detection pattern is proposed and both edge-detection technique and spatial mode prediction technique are combined together to reduce the number of intra 44 candidate modes from 9 to an average of 2.50. VLSI architecture of intra mode decision module is designed with TSMC 0.18 µm CMOS technology. The maximum frequency of 285 MHz is achieved and 13.1k NAND gates are required. High frequency, efficient processing cycle reduction and small area make this design to be an excellent accelerator for HDTV 1080p@30 fps real time encoder.

This paper proposes a distributed stream multiplexing architecture for video codec LSIs with multi-chip configuration. This distributed architecture utilizes a built-in media multiplexing unit with an external stream input and inter-chip communication interfaces. Parallel protocol processing, with an autonomous inter-chip control mechanism to mix and concatenate packets through daisy-chained transfer paths, provides a complete multi-chip stream output at the end of the chain. Dispensing with external post-processing devices contributes to both high throughput and downsizing of high-end video codec systems. It is configurable for parallel encoding of super high-resolution video, multi-view/-angled HDTV vision and multiple HDTV programs. The architecture was successfully implemented in a fabricated single-chip MPEG-2 422P@HL codec LSI and utilized for the development of a super high-resolution video codec system.

The insoluble Prussian-blue (PB) pigment becomes possible to disperse in aqueous solution by covering their surfaces with ferrocyanide anions. The thin film fabricated with these water-dispersible PB nanoparticles shows evident electrochromic color changes between +0.8 V to -0.4 V on an ITO substrate. The mass change of the thin film during an electrochemical reaction is measured by means of electrochemical quartz crystal microbalance (EQCM). According to the EQCM analysis, the filling rate of water-dispersible PB nanoparticles in the film is 37.7% as compared with an assumed perfect crystal PB film.

A fast time-domain simulation technique of plane circuits via two-layer Cellular Neural Network (CNN)-based modeling, which is necessary for power/signal integrity evaluation in VLSIs, printed circuit boards, and packages, is presented. Using the new notation expressed by the two-layer CNN, 1,553 times faster simulation is achieved, compared with Berkeley SPICE (ngspice). In CNN community, CNNs are generally simulated by explicit numerical integration such as the forward Euler and Runge-Kutta methods. However, since the two-layer CNN is a stiff circuit, we cannot analyze it by using an explicit numerical integration method. Hence, to analyze the two-layer CNN and reduce the computational cost, the leapfrog method is introduced. This procedure would open an application of CNN to electronic design automation area.

In many different bioelectronic applications silicon field-effect devices such as transistors or nanowires are used. Usually native or thermally grown silicon oxides serve as interfacing layer to the liquid. For an effective voltage to current conversion of the devices, the main demands for interface layers are low leakage current, low defect density, and high input capacitance. In this article we describe the fabrication and characterization of ultra-thin silicon oxide/high-κ material stacks for bioelectronics. A combination of ultra-thin silicon oxide and DyScO3 revealed the best results. This material stack is particularly interesting for future fabrication of field-effect devices for bioelectronic applications.

In wireless sensor networks (WSNs), localization using the received signal strength (RSS) method is famous for easy adaptation and low cost where measuring the distance between sensor nodes. However, in real localization systems, the RSS is strongly affected by many surrounding factors and tends to be unstable, so that it degrades accuracy in distance measurement. In this paper, we propose the angle-referred calibration based RSS method where angle relation between sensor nodes is used to perform the calibration for better performance in distance measurement. As a result, the proposed scheme shows that it can provide high precision.

In this paper, we propose a partially-parallel irregular LDPC decoder based on IEEE 802.11n standard targeting high throughput and small area applications. The design is based on a novel sum-delta message passing algorithm characterized as follows: (i) Decoding throughput is greatly improved by utilizing the difference value between the updated and the original value to remove redundant computations. (ii) Registers and memory are optimized to store only the frequently used messages to decrease the hardware cost. (iii) Techniques such as binary sorting, parallel column operation, high performance pipelining are used to further speed up the message passing procedure. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200 MHz, with 11% area reduction. The synthesis result also demonstrates the competitiveness to the fully-parallel regular LDPC decoders in terms of the tradeoff between throughput, area and power.

Functional and formal verification are important methodologies for complex mixed-signal design validation. However the industry is still verifying such systems by pure simulation. This process lacks on error localization and formal verifications methods. This is the existing verification gap between the analog and digital blocks within a mixed-signal system. Our approach improves the verification process by creating temporal properties named mixed-signal assertions which are described by a combination of digital assertions and analog properties. The proposed method is a new assertion-based verification flow for designing mixed-signal circuits. The effectiveness of the approach is demonstrated on a Σ/Δ-converter.

As well as the schedule affects system performance, the control skew, i.e., the arrival time difference of control signals between registers, can be utilized for improving the system performance, enhancing robustness against delay variations, etc. The simultaneous optimization of the control step assignment and the control skew assignment is more powerful technique in improving performance. In this paper, firstly, we prove that, even if the execution sequence of operations which are assigned to the same resource is fixed, the simultaneous optimization problem under a fixed clock period is NP-hard. Secondly, we propose a heuristic algorithm for the simultaneous control step and skew optimization under given clock period, and we show how much the simultaneous optimization improves system performance. This paper is the first one that uses the intentional skew to shorten control steps under a specified clock period. The proposed algorithm has the potential to play a central role in various scenarios of skew-aware high level synthesis.

Organic static induction transistor (OSIT) is a promising driving device for the displays, since it shows high-speed, high-power and low-voltage operation. In this study, the OSIT with fine gate electrode patterned by electron beam exposure were fabricated. We investigated the basic electrical characteristics of copper phthalocyanine OSIT and compared with the calculation results obtained by two-dimensional (2D) device simulator. The experimental results show that the gate modulation improved by reducing the electrode gap and on/off current ratio depends on the gate gap.

In this paper, we propose an Adaptive Stochastic Collocation Method for block-based Statistical Static Timing Analysis (SSTA). A novel adaptive method is proposed to perform SSTA with delays of gates and interconnects modeled by quadratic polynomials based on Homogeneous Chaos expansion. In order to approximate the key atomic operator MAX in the full random space during timing analysis, the proposed method adaptively chooses the optimal algorithm from a set of stochastic collocation methods by considering different input conditions. Compared with the existing stochastic collocation methods, including the one using dimension reduction technique and the one using Sparse Grid technique, the proposed method has 10x improvements in the accuracy while using the same order of computation time. The proposed algorithm also shows great improvement in accuracy compared with a moment matching method. Compared with the 10,000 Monte Carlo simulations on ISCAS85 benchmark circuits, the results of the proposed method show less than 1% error in the mean and variance, and nearly 100x speeds up.

This paper presents a unified test compression technique for scan stimulus and unknown masking data with seamless integration of test generation, test compression and all unknown response masking for high quality manufacturing test cost reduction. Unlike prior test compression methods, the proposed approach considers the unknown responses during test pattern generation procedure, and then selectively encodes the less specified bits (either 1s or 0s) in each scan slice for compression while at the same time masks the unknown responses before sending them to the response compactor. The proposed test scheme could dramatically reduce test data volume as well as the number of required test channels by using only c tester channels to drive N internal scan chains, where c = 「 log 2N 」 + 2. In addition, because all the unknown responses could be exactly masked before entering into the response compactor, test loss due to unknown responses would be eliminated. Experimental results on both benchmark circuits and larger designs indicated the effectiveness of the proposed technique.