In this paper, we propose high performance IPv6-IPv4 translator, which translates all packets between IPv6 networks and IPv4 networks at high speed. In our previous work, we analyzed the performance factors of the existing S/W IPv6-IPv4 translators and proposed the improvement methods of each factor. To realize these methods, we also design and implement the IPv6-IPv4 translator with hardware core for the high-speed translation. To verify functionality of our translator core, the hardware emulation using prototyping as well as simulation is performed. Moreover, we show that our translator core can support high-performance translation.

A planar composite right/left-handed leaky wave antenna which operates at W-band is fabricated and its backward to forward beam scanning operation including broadside direction is confirmed experimentally. The scanning angle from 61 to 114 degrees with a frequency scanning range of 76 to 79 GHz is achieved.

The Reliability-Based Hybrid ARQ (RB-HARQ) scheme, which can be used with error correcting codes using soft-input soft-output (SISO) decoders such as convolutional codes and turbo codes has been proposed. In the RB-HARQ scheme, the error rate performance is improved by selecting the retransmission bits based on Log Likelihood Ratio (LLR) of each bit in the receiver. However, the receiver has to send the bit positions of retransmission bits to the transmitter. Therefore, the RB-HARQ scheme requires a great number of feedback bits. On the other hand, Low Density Parity Check (LDPC) codes are attracting a lot of interest, recently. Because LDPC codes can achieve near Shannon limit performance and be decoded easily compared to turbo code. In this paper, we evaluate the RB-HARQ scheme using LDPC code. Moreover, we propose a RB-HARQ scheme that requires a fewer feedback bits by utilizing a code structure of LDPC code. We refer to the scheme as the RB-HARQ (row base) scheme. We show that the RB-HARQ and RB-HARQ (row base) schemes using LDPC code have better error rate performance than the scheme without ARQ. We also show that the RB-HARQ (row base) scheme has a good trade-off between error rate performance and the number of feedback bits compared to the RB-HARQ scheme.

An RF adaptive array antenna (RF-AAA) configured with variable capacitors is proposed. This antenna system can control the power combining ratio and phase value of received signals. In this paper, we focus on the diversity effects of RF-AAA. First, we show the design methodology of the combiner circuit to realize the effective combining. Second, the perturbation method and the steepest gradient method are compared for the optimization algorithms to provide fast convergence and suboptimum solutions among the variable circuit constants. Finally, in simulation, we show the RF-AAA can achieve diversity antenna gains of 7.7 dB, 10.9 dB and 12.6 dB for 2-branch, 3-branch and 4-branch configuration, respectively, which have higher performance than the selection combining.

The modeling of gate delays has always been one of the most difficult and market-sensitive works. In submicron designs, the second-order effects such as the input-to-output coupling capacitance have a significant influence on gate delay as shown in this paper. However, the accurate analysis of the input-to-output coupling capacitance effect has not been presented in previous research. In this paper, an analytical model for the influence of the input-to-output coupling capacitance on CMOS inverter delay is proposed, in which a novel algorithm for computing overshooting time is given. Experimental results show good agreement with Spice simulations.

This paper analyzes automation surprises in human-machine systems with time information. Automation surprises are phenomena such that the underlying machine's behavior diverges from user's intention and may lead to critical situations. Thus, designing human-machine systems without automation surprises is one of fundamental issues to achieve reliable user interaction with the machines. In this paper, we focus on timed human-machine interaction and address their formal aspects. The presented framework is essentially an extension of untimed human-machine interaction and will cover the previously proposed methodologies. We employ timed automata as a model of human-machine systems with time information. Modeling the human-machine systems as timed automata enables one to deal with not only discrete behavior but also time constraints. Then, by introducing the concept of timed simulation of the machine model and the user model, conditions which guarantee the nonexistence of automation surprises are derived. Finally, we construct a composite model in which a machine model and a user model evolve concurrently and show that automation surprises can be detected by solving a reachability problem in the composite model.

This paper concerns the design, implementation and subsequent experimental validation of a low-voltage analog CMOS switch based on a gate-bootstrapped method. The main part of the proposed circuit is a new low-voltage and low-stress CMOS clock voltage doubler. Through the use of a dummy switch, the charge injection induced by the bootstrapped switch is greatly reduced resulting in improved sample-and-hold accuracy. An important attribute of the design is that the ON-resistance is nearly constant. A test chip has been designed and fabricated using a TSMC 0.18 µm CMOS process (single poly, n-well) to confirm the operation of the circuit for a supply voltage of down to 0.65 V.

A design of non-orthogonal 33 space-time block code (STBC) is proposed. The proposed design achieves full rate, full level diversity, and maximum coding gain by symbol rotation (SR) method. In addition, the proposed scheme has lower encoding complexity than the unitary constellation-rotation (CR) STBC, while two methods exhibit the same bit error rate (BER) performance in Rayleigh fading channel.

A hybrid evolutionary neuro-fuzzy system (HENFS) is proposed in this paper, where the weighted Gaussian function (WGF) is used as the membership function for improved premise construction. With the WGF, different types of the membership functions (MFs) can be accommodated in the rule base of HENFS. A new hybrid algorithm of random optimization (RO) algorithm incorporated with the least square estimation (LSE) is presented. Based on the hybridization of RO-LSE, the proposed soft-computing approach overcomes the disadvantages of other widely used algorithms. The proposed HENFS is applied to chaos time series identification and industrial process modeling to verify its feasibility. Through the illustrations and comparisons the impressive performances for unknown system identification can be observed.

Scenarios that describe concrete situations of software operation play an important role in software development, especially in requirements engineering. Since scenarios are informal, the correctness of scenarios is hard to be verified. The authors have developed a language for describing scenarios in which simple action traces are embellished. The purposes are to include typed frames based on a simple case grammar of actions and to describe the sequence among events. Based on this scenario language, this paper describes both (1) a correctness-checking method using rules to detect errors (lack of events, extra events, and wrong sequence among events) in a scenario and (2) a retrieval method of rules from rule DB that applicable to scenarios using pre and post- conditions.

In software development, comprehensive software reviews and testings are important activities to preserve high quality and to control maintenance cost. However it would be actually difficult to perform comprehensive software reviews and testings because of a lot of components, a lack of manpower and other realistic restrictions. To improve performances of reviews and testings in object-oriented software, this paper proposes a novel model for detecting cost-prone classes; the model is based on Mahalanobis-Taguchi method--an extended statistical discriminant method merging with a pattern recognition approach. Experimental results using a lot of Java software are provided to statistically demonstrate that the proposed model has a high ability for detecting cost-prone classes.

There is still much problem in sizing software despite the existence of well-known software sizing methods such as Function Point method. Many developers still continue to use ad-hoc methods or so called "expert" approaches. This is mainly due to the fact that the existing methods require much information that is difficult to identify or estimate in the early stage of a software project. The accuracy of ad-hoc and "expert" methods also has much problem. The entity-relationship (ER) model is widely used in conceptual modeling (requirements analysis) for data-intensive systems. The characteristic of a data-intensive system, and therefore the source code of its software, is actually well characterized by the ER diagram that models its data. This paper proposes a method for building software size model from extended ER diagram through the use of regression models. We have collected some real data from the industry to do a preliminary validation of the proposed method. The result of the validation is very encouraging.

Recently, various decoding algorithms with Low Density Parity Check (LDPC) codes have been proposed. Most algorithms can be divided into a hard decision algorithm and a soft decision algorithm. The Weighted Bit Flipping (WBF) algorithm that is between a hard decision and a soft decision algorithms has been proposed. The Bootstrapped WBF and Modified WBF algorithms have been proposed to improve the error rate performance and decoding complexity of the WBF algorithm. In this letter, we apply the Bootstrap step to the Modified WBF algorithm. We show that the Bootstrapped modified WBF algorithm outperforms the WBF, Bootstrapped WBF, and Modified WBF algorithms. Moreover, we show that the Bootstrapped modified WBF algorithm has the lowest decoding complexity.

In this paper, we propose a partially-parallel LDPC decoder which achieves a high-efficiency message-passing schedule. The proposed LDPC decoder is characterized as follows: (i) The column operations follow the row operations in a pipelined architecture to ensure that the row and column operations are performed concurrently. (ii) The proposed parallel pipelined bit functional unit enables the column operation module to compute every message in each bit node which is updated by the row operations. These column operations can be performed without extending the single iterative decoding delay when the row and column operations are performed concurrently. Therefore, the proposed decoder performs the column operations more frequently in a single iterative decoding, and achieves a high-efficiency message-passing schedule within the limited decoding delay time. Hardware implementation on an FPGA and simulation results show that the proposed partially-parallel LDPC decoder improves the decoding throughput and bit error performance with a small hardware overhead.

An automatic and efficient algorithm for removal of intensity flicker is proposed. The novel repair process is founded on the block-based estimation and restoration algorithm with regard to luminance variation. It is easily realized and controlled to remove most intensity flicker and preserve the wanted effects, like fade in and fade out.

The label placement problem is one of the most important problems in geographic information systems, cartography, graph drawing, and graphical interface design. In this paper, we considered the label size maximization problem for points with axes-parallel rectangular labels that correspond to character strings and have different widths based on the number of characters. We propose an algorithm for computing the optimum size for the label size maximization problem in the 2-position model and a polynomial time algorithm for the problem in the 4-position model. Our algorithm cannot obtain the maximum value in the 4-position model because the label size maximization problem in the 4-position model is NP-hard. However, our algorithm is efficient in practice, as shown by computational experiments. Further, computational results for JR trains, subways and major private railroads in Tokyo are presented.

We propose a likelihood detection scheme that utilizes ordering and decision of partial bits in MIMO spatial multiplexing systems. We compute BER performance of the proposed detection scheme under Rayleigh fading channels in a 33 MIMO spatial multiplexing system and compare it with BER performance using MLD only and detection utilizing ZF or MMSE only. In addition, the computational complexity of the proposed detection scheme is compared with that of MLD and detection utilizing ZF or MMSE. The results of our investigation show that the proposed detection is a scheme achieves both good BER performance and low computational complexity.

In iterative software development methodology, a version control system is used in order to record and manage modification histories of products such as source codes and models described in diagrams. However, conventional version control systems cannot manage the models as a logical unit because the systems mainly handle source codes. In this paper, we propose a version control technique for handling diagrammatical models as logical units. Then we illustrate the feasibility of our approach with the implementation of version control functions of a meta-CASE tool that is able to generate a modeling tool in order to deal with various diagrams.

This paper proposes a parallel coupled microstrip bandpass filter (BPF) with ring Electromagnetic Bandgap (EBG) cells on the middle layer for spurious suppression. The ring EBG cells of the middle layer add a good stopband-rejection mode to the second harmonics of the parallel coupled microstrip BPF with suppression of over -50 dB, without affecting the center frequency and insertion loss of the original designed BPF. The design of ring EBG cells is presented and verified by the experimented results.

This letter presents the characteristics of complex antenna factors of a resistor loaded dipole antenna with a balun consisting of two coaxial feeders (coaxial cable balun). The resistor loading is used to realize dipole antennas with higher fidelity than unloaded dipole equivalents. The complex antenna factor for a resistor loaded dipole antenna with coaxial cable balun is derived by extending the power loss concepts. The numerical results show that the series resistor loaded dipole antenna offers higher fidelity than the unloaded dipole. The result of the calculated complex antenna factors are in good agreement with that of the measured results.