It is well known that TCP does not fully utilize the available bandwidth in fast long-distance networks. To solve this scalability problem, several high speed transport protocols have been proposed. They include HighSpeed TCP (HS-TCP), Scalable TCP (S-TCP), Binary increase control TCP (BIC-TCP), and H-TCP. These protocols increase (decrease) their window size more aggressively (slowly) compared to standard TCP (STD-TCP). This paper aims at evaluating and comparing these high speed transport protocols through computer simulations. We select six metrics that are important for high speed protocols; scalability, buffer requirement, TCP friendliness, TCP compatibility, RTT fairness, and responsiveness. Simulation scenarios are carefully designed to investigate the performance of these protocols in terms of the metrics. Results clarify that each high speed protocol successfully solves the problem of STD-TCP. In terms of the buffer requirement, S-TCP and BIC-TCP have better performance. For TCP friendliness and compatibility, HS-TCP and H-TCP offer better performance. For RTT fairness, BIC-TCP and H-TCP are superior. For responsiveness, HS-TCP and H-TCP are preferred. However, H-TCP achieves a high degree of fairness at the expense of the link utilization. Thus, we understand that all the proposed high speed transport protocols have their own shortcomings. Thus, much more research is needed on high speed transport protocols.

This paper investigates the design curves of class E amplifier with nonlinear capacitance for any output Q and finite dc-feed inductance. The important results are; 1) the capacitance nonlinearity strongly affects the design parameters for low Q, 2) the value of dc-feed inductance is hardly affected by the capacitance nonlinearity, and 3) the input voltage is an important parameter to design class E amplifier with nonlinear capacitance. By carrying out PSpice simulations, we show that the simulated results agree with the desired ones quantitatively. It is expected that the design curves in this paper are useful guidelines for the design of class E amplifier with nonlinear capacitance.

In this study, we propose a robust approach for blind source separation (BSS) by using radial basis function networks (RBFNs) and higher-order statistics (HOS). The RBFN is employed to estimate the inverse of a hypothetical complicated mixing procedure. It transforms the observed signals into high-dimensional space, in which one can simply separate the transformed signals by using a cost function. Recently, Tan et al. proposed a nonlinear BSS method, in which higher-order moments between source signals and observations are matched in the cost function. However, it has a strict restriction that it requires the higher-order statistics of sources to be known. We propose a cost function that consists of higher-order cumulants and the second-order moment of signals to remove the constraint. The proposed approach has the capacity of not only recovering the complicated mixed signals, but also reducing noise from observed signals. Simulation results demonstrate the validity of the proposed approach. Moreover, a result of application to X-ray image separation also shows its practical applicability.

This paper presents fingerprint image enhancement and rotation schemes that improve the identification accuracy with the pixel-parallel processing of pixels. In the schemes, the range of the fingerprint sensor is adjusted to the finger state, the captured image is retouched to obtain the suitable image for identification, and the image is rotated to the correct angle on the pixel array. Sensor and pixel circuits that provide these operations were devised and a test chip was fabricated using 0.25-µm CMOS and the sensor process. It was confirmed in 150,000 identification tests that the schemes reduce the false rejection rate to 6.17% from 30.59%, when the false acceptance rate is 0.1%.

This paper proposes a continuous-time bandpass ΔΣAD modulator architecture which performs high-accuracy AD conversion of high frequency analog signals and can be used for next-generation radio systems. We use an RF DAC inside the modulator to enable subsampling and also to make the SNDR of the continuous-time modulator insensitive to DAC sampling clock jitter. We have confirmed that this is the case by MATLAB simulation. We have also extended our modulator to multi-bit structures and show that this alleviates excess loop delay problems.

With the increasing demand for SoCs to include rich functionality, SoCs are being designed with hundreds of small memories with different sizes and frequencies. If memory BIST logics were individually added to these various memories, the area overhead would be very high. To reduce the overhead, memory BIST logic must therefore be shared. This paper proposes a memory-grouping method for memory BIST logic sharing. A memory-grouping problem is formulated and an algorithm to solve the problem is proposed. Experimental results show that the proposed method reduced the area of the memory BIST wrapper by up to 40.55%. The results also show that the ability to select from two types of connection methods produced a greater reduction in area than using a single connection method.

In this paper, we propose a partially-parallel LDPC decoder which achieves a high-efficiency message-passing schedule. The proposed LDPC decoder is characterized as follows: (i) The column operations follow the row operations in a pipelined architecture to ensure that the row and column operations are performed concurrently. (ii) The proposed parallel pipelined bit functional unit enables the column operation module to compute every message in each bit node which is updated by the row operations. These column operations can be performed without extending the single iterative decoding delay when the row and column operations are performed concurrently. Therefore, the proposed decoder performs the column operations more frequently in a single iterative decoding, and achieves a high-efficiency message-passing schedule within the limited decoding delay time. Hardware implementation on an FPGA and simulation results show that the proposed partially-parallel LDPC decoder improves the decoding throughput and bit error performance with a small hardware overhead.

In recent years, digital watermarking has become a popular technique for labeling digital images by hiding secret information which can protect the copyright. The goal of this paper is to develop a DCT-based watermarking algorithm for low power and high performance. Our energy-efficient technique focuses on reducing computation required on block-based permutation. Instead of using spacial coefficients proposed by Hsu and Wu's algorithm [1], we use DCT coefficients to pair blocks directly. The approach is implemented by C language and estimated power dissipation using Wattch toolset. The experimental results show that our approach not only reduces 99% energy consumption of pairing mechanism, but also increase the PSNR by 0.414 db for the best case. Moreover, the proposed approach is robust to a variety of signal distortions, such as JPEG, image cropping, sharpening, blurring, and intensity adjusting.

There is still much problem in sizing software despite the existence of well-known software sizing methods such as Function Point method. Many developers still continue to use ad-hoc methods or so called "expert" approaches. This is mainly due to the fact that the existing methods require much information that is difficult to identify or estimate in the early stage of a software project. The accuracy of ad-hoc and "expert" methods also has much problem. The entity-relationship (ER) model is widely used in conceptual modeling (requirements analysis) for data-intensive systems. The characteristic of a data-intensive system, and therefore the source code of its software, is actually well characterized by the ER diagram that models its data. This paper proposes a method for building software size model from extended ER diagram through the use of regression models. We have collected some real data from the industry to do a preliminary validation of the proposed method. The result of the validation is very encouraging.

In this paper a newly designed internally-coupled asymmetric stepped-impedance resonator (SIR) bandpass filter (BPF) is proposed. The asymmetric SIR structure not only can effectively reduce the circuit size but also can provide two flexibly tunable transmission zeros near the lower and upper passband edges. The first transmission zero is due to the series resonance of the quarter-wavelength open stepped-impedance stub, and the second one is produced by anti-parallel coupling between adjacent SIRs. The proposed BPF was fabricated and simulated using the commercial software HFSS, and agreement between the measured and simulated results was observed. A 0.9-dB insertion loss and a shape factor of 3.6 were achieved in the passband, thus indicating that the proposed filter structure is of practical value.

The effect of the power/ground plane on the through-hole signal via is analyzed in a viewpoint of a band-stop filter. When the through-hole signal via passes through the power/ground plane, the return current path discontinuity of the through-hole signal via occurs due to the high impedance of the power/ground plane. Since the high impedance is produced by the power/ground plane resonance, it acts as a band-stop filter, which is connected to the signal trace in series. Therefore, the power/ground plane filters off its resonance frequency component by absorbing and reflecting from the signal on the through-hole signal via, and consequently the signal distortion, the power/ground plane noise voltage, and the consequent radiated emission occur. With S-parameter and TDR-TDT measurements, the band-stop effect of the power/ground plane on the through-hole signal via is confirmed. And then, this analysis is applied to the clock transmission through the through-hole signal via to obtain the clearer confirmation. The measurements of the distorted clock waveforms, the induced power/ground plane noise voltages, and the radiated emissions depending on the power/ground plane impedance around the through-hole signal via are shown.

A design of non-orthogonal 33 space-time block code (STBC) is proposed. The proposed design achieves full rate, full level diversity, and maximum coding gain by symbol rotation (SR) method. In addition, the proposed scheme has lower encoding complexity than the unitary constellation-rotation (CR) STBC, while two methods exhibit the same bit error rate (BER) performance in Rayleigh fading channel.

Scenarios that describe concrete situations of software operation play an important role in software development, especially in requirements engineering. Since scenarios are informal, the correctness of scenarios is hard to be verified. The authors have developed a language for describing scenarios in which simple action traces are embellished. The purposes are to include typed frames based on a simple case grammar of actions and to describe the sequence among events. Based on this scenario language, this paper describes both (1) a correctness-checking method using rules to detect errors (lack of events, extra events, and wrong sequence among events) in a scenario and (2) a retrieval method of rules from rule DB that applicable to scenarios using pre and post- conditions.

An RF adaptive array antenna (RF-AAA) configured with variable capacitors is proposed. This antenna system can control the power combining ratio and phase value of received signals. In this paper, we focus on the diversity effects of RF-AAA. First, we show the design methodology of the combiner circuit to realize the effective combining. Second, the perturbation method and the steepest gradient method are compared for the optimization algorithms to provide fast convergence and suboptimum solutions among the variable circuit constants. Finally, in simulation, we show the RF-AAA can achieve diversity antenna gains of 7.7 dB, 10.9 dB and 12.6 dB for 2-branch, 3-branch and 4-branch configuration, respectively, which have higher performance than the selection combining.

Recently, system level design languages (SLDL), which can describe both hardware and software aspects of the design, are receiving attention. Mixed-signal extensions of SLDL enable current discrete-oriented SLDLs to describe and simulate not only digital systems but also digital-analog mixed-signal systems. The synchronization between discrete and continuous behaviors is widely regarded as a critical part in the extensions. In this paper, we present an event-driven synchronization mechanism for both timed and untimed system level designs through which discrete and continuous behaviors are synchronized via AD events and DA events. We also demonstrate how the synchronization mechanism can be incorporated into the kernel of SLDL, such as SpecC. In the extended kernel, a new simulation cycle, the AMS cycle, is introduced. Three case studies show that the extended SpecC-based system level design environment using our synchronization mechanism works well with timed/untimed mixed-signal system level description.

Recently, various decoding algorithms with Low Density Parity Check (LDPC) codes have been proposed. Most algorithms can be divided into a hard decision algorithm and a soft decision algorithm. The Weighted Bit Flipping (WBF) algorithm that is between a hard decision and a soft decision algorithms has been proposed. The Bootstrapped WBF and Modified WBF algorithms have been proposed to improve the error rate performance and decoding complexity of the WBF algorithm. In this letter, we apply the Bootstrap step to the Modified WBF algorithm. We show that the Bootstrapped modified WBF algorithm outperforms the WBF, Bootstrapped WBF, and Modified WBF algorithms. Moreover, we show that the Bootstrapped modified WBF algorithm has the lowest decoding complexity.

This paper concerns the design, implementation and subsequent experimental validation of a low-voltage analog CMOS switch based on a gate-bootstrapped method. The main part of the proposed circuit is a new low-voltage and low-stress CMOS clock voltage doubler. Through the use of a dummy switch, the charge injection induced by the bootstrapped switch is greatly reduced resulting in improved sample-and-hold accuracy. An important attribute of the design is that the ON-resistance is nearly constant. A test chip has been designed and fabricated using a TSMC 0.18 µm CMOS process (single poly, n-well) to confirm the operation of the circuit for a supply voltage of down to 0.65 V.

A new small-signal model for fully depleted silicon-on-insulator (FD-SOI) MOSFETs operating at RF frequencies is presented. The model accounts for the non-quasi-static effect by determining model parameters using a curve fitting procedure to reproduce the frequency response of FD-SOI MOSFETs. The accuracy of the model is validated by comparison of S parameters with measured results in the range from 0.2 GHz to 20 GHz.

This paper proposes a new architecture for multibit complex bandpass ΔΣAD modulators with built-in Switched-Capacitor (SC) circuits for application to Low-IF receivers such as used for Bluetooth and WLAN. In the realization of complex bandpass ΔΣAD modulators, we face the following problems: (i) SNR of AD converter is deteriorated by mismatches between internal analog I and Q paths. (ii) Layout design becomes complicated because of signal lines crossing by complex filter and feedback from DAC for I and Q paths in the complex modulator, and this increases required chip area. We propose a new structure for a complex bandpass ΔΣAD modulator which can be completely divided into two paths without layout crossing, and solves the problems mentioned above. The two parts of signal paths and circuits in the modulator are changed for I and Q while CLK is changed for High/Low by adding multiplexers. Symmetric circuits are used for I and Q paths at a certain timing, and they are switched by multiplexers to those used for Q and I paths at another timing. Therefore the influence from mismatches between I and Q paths is reduced by dynamic matching. As a result, the modulator is divided into two separate parts without crossing signal lines between I and Q paths and its layout design can be greatly simplified compared with conventional modulators. We have conducted MATLAB simulations to confirm the effectiveness of the proposed structure.

Analyzing short-interval-traffic behaviors is important for network performance management to realize high quality multimedia applications. However, it is difficult to measure short-interval-traffic volumes because there are complications in collecting short-interval-traffic data from routers. An example is a heavy load on routers or inaccurate measurement by the short-polling interval; it even demands expensive measurement tools. To resolve these disadvantages, an estimating method of short-interval-traffic distribution (EMSIT) has been proposed. This method estimates short-interval-traffic distributions using MIB (Management Information Base) data, which collects traffic volumes in cycles of several minutes. In this paper, we propose a new estimation method (EMSIT-LD) based on EMSIT, which applies to the case of long-term-traffic dynamics. We evaluate it using computer simulations and actual traffic data.