Recently, spiral inductors have widely been used instead of resistors in the design of matching circuits to enhance the thermal noise performance of a wireless transceiver. However, such elements usually have low quality factor (Q) and may encounter the self-resonance in microwave-frequency band which permits its use in higher frequencies, and on the other hand, they occupy the large on-chip space. This paper presents a new design theory for the impedance-matching circuits for a single-chip SiGe BiCMOS receiver front-end for 2.4 GHz-band wireless LAN (IEEE 802.11b). The presented matching circuits are composed of conductor-backed coplanar waveguide (CPW) meander-line resonators and impedance (K) inverter. The prototype front-end receiver is designed, fabricated and tested. A few of the measured results to verify the design theory are presented.

A novel two-dimensional (2D) beam scanning antenna array using composite right/left-handed (CRLH) leaky-wave antennas (LWAs) is proposed. The antenna array consists of a set of CRLH LWAs and a Butler matrix (BM) feeding network. The direction of the beam can be scanned two-dimensionally in one plane by changing frequency and in the other plane by switching the input ports of the BM. A four-element antenna array in the microstrip line configuration operating at 10.5 GHz is designed with the assistance of full-wave simulations based on the method of moment (MoM) and the finite-element method (FEM). The antenna array is fabricated and radiation characteristics are measured. The wide range 2D beam scanning operation with the angle from -30 deg to +25 deg in one plane by sweeping frequency from 10.25 GHz to 10.7 GHz and with four discrete angles of -46 deg, -15 deg, +10 deg, and +35 deg in the other plane by switching the input port is achieved.

The I/Q unbalance which is generated by a non-ideal component is an inevitable physical phenomenon and leads to performance degradation when we implement a practical two-dimensional (2-D) modulation system. In this paper, we provide an exact and general expression involving the 2-D Gaussian Q-function for the SER/BER of arbitrary 2-D signaling with I/Q amplitude and phase unbalances over an additive white Gaussian noise (AWGN) channel by using the coordinate rotation and shifting technique. Through Monte Carlo simulations we verify our expression provided here for 16-star Quadrature Amplitude Modulation (QAM).

Paging extensions for Mobile Internet Protocol (P-MIP) decreases only the number of registration, but it does not much improve the method of registration, which still gives rise to a lot of lost packets and long handoff latency, and may also waste the data buffering and time during registration. In the active state, P-MIP behaves in the same way as Mobile Internet Protocol (MIP), thus, in this state, the packet loss rate of P-MIP is the same as that of MIP. However, the packet loss rate of P-MIP is lower than that of MIP, when changing from idle state to active state, because P-MIP buffers packets at the registered FA. We propose an improvement method for the registration delay, while the mobile node is entering the active state to decrease the mobile node waiting time for data packets. The proposed method can reduce the requirement of data buffering and also improve the method of registration to decrease lost packets and handoff latency when the mobile node moves across the cell in the same paging area during active state.

Radio frequency identification (RFID) technology is becoming increasingly attractive because of its high storage capacity and reprogrammability. There is a challenge to be overcome when a reader needs to read a number of tags within the reader's interrogation zone at the same time. In this paper, we present an anti-collision scheme in a RFID system. The scheme is based on the dynamic framed ALOHA protocol developed for radio networks. In our scheme, we propose two methods to estimate the number of tags. Simulation results indicate that the total number of time slots for reading all tags is about 4 times the number of tags that need to be read, including acknowledgement time slots. The main advantages of our scheme are the great performance of uplink throughput and its easy implementation for both readers and tags.

A new transmission line structure is presented in this work for advanced CMOS processes. This structure has a high quality factor and low attenuation. It allows slow-waves to propagate which results in low dispersion for a given characteristic impedance. It is also designed to satisfy the stringent density requirements of advanced CMOS processes. A model is developed to characterize this structure by analyzing the physical current flowing in the substrate and the shield structure. Test structures were fabricated using CMOS 90 nm process technology with measurements made up to 110 GHz using a transmission-reflection module on a network analyzer. The results correspond well to the proposed model.

In this letter, efficient two-dimensional (2-D) fast algorithms for realizations of 88 forward and inverse integer transforms in H.264/AVC fidelity range extensions (FRExt) are proposed. Based on matrix factorizations with Kronecker product and direct sum operations, efficient fast 2-D 88 forward and inverse integer transforms can be derived from the one-dimensional (1-D) fast 88 forward and inverse integer transforms through matrix operations. The proposed fast 2-D 88 forward and inverse integer transform designs don't require transpose memory in hardware realizations. The fast 2-D 88 integer transforms require fewer latency delays and provide a larger throughput rate than the row-column based method. With regular modularity, the proposed fast algorithms are suitable for VLSI implementations to achieve H.264/AVC FRExt high-profile signal processing.

Multiple-access interference (MAI) limits the bit error rate (BER) performance of CDMA uplink transmission. In this paper, we propose a generalized chip-interleaved CDMA with 2-dimensional (2D) spreading using orthogonal variable spreading factor (OVSF) codes to minimize the MAI effects and achieve the maximum available time- and frequency-domain diversity gains. We present the code assignment for 2D spreading to provide users with flexible multi-rate data transmission. A computer simulation shows that by the joint use of 2D OVSF spreading and chip-interleaving, MAI-free transmission is possible for the quasi-synchronous DS- or MC-CDMA uplink, and hence the single-user frequency-domain equalization based on the MMSE criterion can be applied for signal detection. The BER performance in a time- and frequency-selective fading multiuser channel is theoretically analyzed and evaluated by both numerical computation and computer simulation.

It has been shown that the maskless dye-diffusion technique is applicable to a conjugated polymer poly(9,9-dioctylfluorene). The introduction of Coumarin 6 and Nile red results in green and white emission, with the increased onset voltage for the both cases. It has also been confirmed that the heat treatment effect during the maskless dye diffusion technique results in not the increase but the decrease of the onset voltage, indicating that the dye plays a role of carrier trap in the polymer.

An even harmonic quadrature mixer (EH-QMIX) with a balanced configuration is proposed for a direct conversion receiver. The unit even harmonic mixer (EHMIX) used for I/Q paths consists of two anti parallel diode pairs (APDPs) and a pair of diplexers. When the second harmonic of LO (2LO) from the LO section is applied to the LO port as a spurious component, a conventional single-ended EHMIX using APDP converts the 2LO leakage from the LO section into the baseband and the d.c. offset and the self-detected LO noise arise at the baseband degrade the sensitivity. This proposed balanced EHMIX configuration can cancel out the 2LO leakage in itself. Therefore, the d.c. offset and the LO noise are significantly suppressed and the degradation of the sensitivity can be avoided. The suppression characteristic of the d.c. offset and the LO noise are verified by the simulation and the measurements. By using this balanced configuration, the fabricated EH-QMIX achieves wider frequency band characteristic than that of the single-ended EH-QMIX, and it shows 20% relative bandwidth at L-band.

We derived explicit formulas for evaluating the error vector magnitude (EVM) from the amplitude distortion (AM-AM) and phase distortion (AM-PM) of power amplifiers (PAs) in orthogonal frequency-division multiplexing (OFDM) systems, such as the IEEE 802.11a/g wireless local area networks (WLANs) standards. We demonstrated that the developed formulas allowed EVM simulation of a memoryless PA using only a single-tone response (i.e. without OFDM modulation and demodulation), thus enabling us to easily simulate the EVM using a harmonic-balance (HB) simulator. This HB simulation technique reduced the processing time required to simulate the EVM of a PA for the IEEE 802.11a standard by a factor of ten compared to a system-level (SL) simulation. We also demonstrated that the measured EVM of a PA module for the IEEE 802.11g could accurately be predicted by applying the measured static AM-AM and AM-PM characteristics to the derived formulas.

In real-time multimedia processing systems a very large part of the power consumption is due to the data storage and data transfer. Moreover, the area cost is often largely dominated by the memory modules. In deriving an optimized (for area and/or power) memory architecture, memory size computation is an important step in the exploration of the possible algorithmic specifications of multimedia applications. This paper presents a novel non-scalar approach for computing exactly the memory size in real-time multimedia algorithms. This methodology uses both algebraic techniques specific to the data-flow analysis used in modern compilers and, also, more recent advances in the theory of polyhedra. In contrast with all the previous works which are only estimation methods, this approach performs exact memory computations even for applications significantly large in terms of the code size, number of scalars, and number of array references.

We propose a scheme by which Broadcast Satellite/Communication Satellite- radio frequency (BS/CS-RF) converted TV signals are transmitted over optical fiber, and also propose a simultaneous Frequency Modulation (FM) converted CATV and BS/CS-RF converted TV optical transmission system as one of its applications. To confirm the proposals, we demonstrate the simultaneous transport of FM converted CATV signals and BS/CS-RF converted TV signals over a single optical fiber. In the experiments, 40 carriers of AM-VSB CATV channels, 30 carriers of 64-QAM digital TV channels, 8 carriers of FM/TC8PSK BS-TV channels, and 12 carriers of QPSK CS-TV channels are simultaneously transmitted. For optical access network application, the practical transmission length of 15 km over 1.3 µm-zero-dispersion optical fiber can be achieved by using dispersion compensation fiber (DCF).

Currently, multiband orthogonal frequency division multiplexing (MB-OFDM) is considered to be one of the modulation schemes of UWB and is being actively investigated. It is necessary to provide low-cost receivers for consumers to receive wide support for the MB-OFDM system. Such receivers can be achieved by utilizing direct-conversion architecture. Direct-conversion architecture suffers from IQ imbalance. IQ imbalance causes intercarrier interference (ICI) in the demodulated signals. In this paper, a new scheme of IQ imbalance compensation using transmit diversity is proposed. This scheme enables the system to achieve frequency diversity and simultaneously compensates for the influence of IQ imbalance. It is shown that the performance of the proposed scheme is better than that of the conventional IQ imbalance compensation scheme.

In this paper, a multiuser receiver based on a Gaussian Mixture Sigma Point Particle Filter (GMSPPF), which can be used for joint channel coefficient estimation and time delay tracking in CDMA communication systems, is introduced. The proposed algorithm has better improved estimation performance than either Extended Kalman Filter (EKF) or Particle Filter (PF). The Cramer-Rao Lower Bound (CRLB) is derived for the estimator, and the simulation result demonstrates that it is almost completely near-far resistant. For this reason, it is believed that the proposed estimator can replace well-known filters such as the EKF or PF.

Rapid eye motion, or so called saccade, is a very quick eye motion which always occurs regardless of our intention. Although the line of sight (LOS) with saccade tracking is expected to be used for a new type of computer-human interface, it is impossible to track it using the conventional video camera, because of its speed which is often up to 600 degrees per second. Vision Chip is an intelligent image sensor which has the photo receptor and the image processing circuitry on a single chip, which can process the acquired image information by keeping its spatial parallelism. It has also the ability of implementing the very compact integrated vision system. In this paper, we describe the vision chip architecture which has the capability of detecting the line of sight from infrared eye image, with the processing speed supporting the saccade tracking. The vision chip described here has the pixel parallel processing architecture, with the node automata for each pixel as image processing. The acquired image is digitized to two flags indicating the Purkinje's image and the pupil by comparators at first. The digitized images are then shrunk, followed by several steps of expanding by node automata located at each pixel. The shrinking process is kept executed until all the pixels disappear, and the pixel disappearing at last indicates the center of the Purkinje's image and the pupil. This disappearing step is detected by the projection circuitry in pixel circuit for fast operation, and the coordinates of the center of the Purkinje's image and the pupil are generated by the simple encoders. We describe the whole architecture of this vision chip, as well as the pixel architecture. We also describe the evaluation of proposed algorithm with numerical simulation, as well as processing speed using FPGA, and improvement in resolution using column parallel architecture.

In this letter, a blind frequency offset estimation algorithm is proposed for OFDM systems. The proposed method exploits the intrinsic phase shift between neighboring samples in a single OFDM symbol, incurred by a frequency offset. The proposed algorithm minimizes a novel cost function, which is the squared error of the candidate frequency offset compensated signals from two different observation windows. Also, the solution of the proposed algorithm is given by an explicit equation, which does not require any iterative calculation. It is shown that the performance of the proposed method is better than those of the conventional methods, especially in the presence of multipath channels. This is due to the fact that the proposed method is insensitive to inter-symbol interference (ISI).

This paper presents a methodology based on congruent transformation for distributed interconnects described by state-space time-delays system. The proposed approach is to obtain the passive reduced order of linear time-delays system. The unified formulations are used to satisfy the passive preservation. The details of the mathematical proof and a couple of validation examples are given in this paper.

For broadband wireless networks based on OFDM (Orthogonal Frequency Division Multiplexing), an FRF (Frequency Reuse Factor) of 1 has been highly desirable for more improved channel throughput. However, due to the limited power budget of MSs (Mobile Stations) or the increase in ICI (Inter-Cell Interference), a required QoS (Quality of Service) may not be maintained. This paper addresses an optimal LCRTD (Loading Control based on Region-Time Division) over multi-cell environments for an efficient uplink QoS control. In the LCRTD scheme, a cell is divided into several regions by utilizing an optimization approach under QoS constraints, and users in each region are allowed to send their data at the allocated time slots. In the simulation, it is demonstrated that a decrease of 26% in the transmit power can be obtained.

This paper outlines the method of constructing single-electron logic circuits based on the binary decision diagram (BDD), a graphical representation of digital functions. The circuit consists of many unit devices, BDD devices, cascaded to build the tree of a BDD graph. Each BDD device corresponds to a node of the BDD graph and operates as a two-way switch for the transport of a single electron. Any combinatorial logic can be implemented using BDD circuits. Several subsystems for a single-electron processor have been constructed using semiconductor nano-process technology.