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[Keyword] Stability(309hit)

101-120hit(309hit)

  • A Selective Scan Chain Activation Technique for Minimizing Average and Peak Power Consumption

    Yongjoon KIM  Jaeseok PARK  Sungho KANG  

     
    LETTER-Dependable Computing

      Vol:
    E93-D No:1
      Page(s):
    193-196

    In this paper, we present an efficient low power scan test technique which simultaneously reduces both average and peak power consumption. The selective scan chain activation scheme removes unnecessary scan chain utilization during the scan shift and capture operations. Statistical scan cell reordering enables efficient scan chain removal. The experimental results demonstrated that the proposed method constantly reduces the average and peak power consumption during scan testing.

  • A Scan-Based Attack Based on Discriminators for AES Cryptosystems

    Ryuta NARA  Nozomu TOGAWA  Masao YANAGISAWA  Tatsuo OHTSUKI  

     
    PAPER-Embedded, Real-Time and Reconfigurable Systems

      Vol:
    E92-A No:12
      Page(s):
    3229-3237

    A scan chain is one of the most important testing techniques, but it can be used as side-channel attacks against a cryptography LSI. We focus on scan-based attacks, in which scan chains are targeted for side-channel attacks. The conventional scan-based attacks only consider the scan chain composed of only the registers in a cryptography circuit. However, a cryptography LSI usually uses many circuits such as memories, micro processors and other circuits. This means that the conventional attacks cannot be applied to the practical scan chain composed of various types of registers. In this paper, a scan-based attack which enables to decipher the secret key in an AES cryptography LSI composed of an AES circuit and other circuits is proposed. By focusing on bit pattern of the specific register and monitoring its change, our scan-based attack eliminates the influence of registers included in other circuits than AES. Our attack does not depend on scan chain architecture, and it can decipher practical AES cryptography LSIs.

  • Stability Analysis of XCP (eXplicit Control Protocol) with Heterogeneous Flows

    Yusuke SAKUMOTO  Hiroyuki OHSAKI  Makoto IMASE  

     
    PAPER-Internet

      Vol:
    E92-B No:10
      Page(s):
    3174-3182

    In this paper, we analyze the stability of XCP (eXplicit Control Protocol) in a network with heterogeneous XCP flows (i.e., XCP flows with different propagation delays). Specifically, we model a network with heterogeneous XCP flows using fluid-flow approximation. We then derive the conditions that XCP control parameters should satisfy for stable XCP operation. Furthermore, through several numerical examples and simulation results, we quantitatively investigate effect of system parameters and XCP control parameters on stability of the XCP protocol. Our findings include: (1) when XCP flows are heterogeneous, XCP operates more stably than the case when XCP flows are homogeneous, (2) conversely, when variation in propagation delays of XCP flows is large, operation of XCP becomes unstable, and (3) the output link bandwidth of an XCP router is independent of stability of the XCP protocol.

  • Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits

    Kazuteru NAMBA  Hideo ITO  

     
    PAPER-VLSI Design Technology and CAD

      Vol:
    E92-A No:9
      Page(s):
    2295-2303

    The importance of redundant technologies for improving dependability and delay fault testability are growing. This paper presents properties of a class of redundant technologies, namely two-rail logic, and analyzes testability of path delay faults occurring on two-rail logic circuits. The paper reveals the following characteristics of two-rail logic circuits: While the number of paths in two-rail logic circuits is twice that in ordinary single-rail logic circuits, the number of robust testable path delay faults in two-rail logic circuits is twice or more that in the single-rail logic circuits. This suggests two-rail logic circuits are more testable than ordinary single-rail logic circuits. On two-rail logic circuits, there may be some robust testable path delay faults that are functional un-sensitizable for any input vectors consisting of codewords of two-rail codes, i.e. for any input vectors that can occur during fault-free operation. Even if such faults occur, the circuits are still strongly fault secure for unidirectional stuck-at faults as well as they work correctly.

  • A 0.18 µm Stability-Enhanced CMOS LDO with Robust Compensation Scheme

    Hsuan-I PAN  Chern-Lin CHEN  

     
    PAPER-Electronic Circuits

      Vol:
    E92-C No:8
      Page(s):
    1080-1086

    A 0.18 µm 1.5 V/50 mA stability-enhanced low dropout regulator (LDO) is presented. A multi-path error amplifier and a split pass device structure are utilized for pole-zero pair compensation. The proposed LDO can be stable without a load capacitor and also stable with different combinations of load capacitors and equivalent series resistance.

  • The Absolute Stability Analysis in Fuzzy Control Systems with Parametric Uncertainties and Reference Inputs

    Bing-Fei WU  Li-Shan MA  Jau-Woei PERNG  

     
    PAPER-Systems and Control

      Vol:
    E92-A No:8
      Page(s):
    2017-2035

    This study analyzes the absolute stability in P and PD type fuzzy logic control systems with both certain and uncertain linear plants. Stability analysis includes the reference input, actuator gain and interval plant parameters. For certain linear plants, the stability (i.e. the stable equilibriums of error) in P and PD types is analyzed with the Popov or linearization methods under various reference inputs and actuator gains. The steady state errors of fuzzy control systems are also addressed in the parameter plane. The parametric robust Popov criterion for parametric absolute stability based on Lur'e systems is also applied to the stability analysis of P type fuzzy control systems with uncertain plants. The PD type fuzzy logic controller in our approach is a single-input fuzzy logic controller and is transformed into the P type for analysis. In our work, the absolute stability analysis of fuzzy control systems is given with respect to a non-zero reference input and an uncertain linear plant with the parametric robust Popov criterion unlike previous works. Moreover, a fuzzy current controlled RC circuit is designed with PSPICE models. Both numerical and PSPICE simulations are provided to verify the analytical results. Furthermore, the oscillation mechanism in fuzzy control systems is specified with various equilibrium points of view in the simulation example. Finally, the comparisons are also given to show the effectiveness of the analysis method.

  • 10-Gb/s Optical Buffer Memory Using a Polarization Bistable VCSEL

    Takashi MORI  Yuuki SATO  Hitoshi KAWAGUCHI  

     
    PAPER-Lasers, Quantum Electronics

      Vol:
    E92-C No:7
      Page(s):
    957-963

    Optical buffer memory for 10-Gb/s data signal is demonstrated experimentally using a polarization bistable vertical-cavity surface-emitting laser (VCSEL). The optical buffer memory is based on an optical AND gate function and the polarization bistability of the VCSEL. Fast AND gate operation responsive to 50-ps-width optical pulses is achieved experimentally by increasing the detuning frequency between an injection light into the VCSEL and a lasing light from the VCSEL. A specified bit is extracted from the 10-Gb/s data signal by the fast AND gate operation and is stored as the polarization state of the VCSEL by the polarization bistability. The corresponding numerical simulations are also performed using two-mode rate equations taking into account the detuning frequency. The simulation results confirm the fast AND gate operation by increasing the detuning frequency as well as the experimental results.

  • Grouped Scan Slice Repetition Method for Reducing Test Data Volume and Test Application Time

    Yongjoon KIM  Myung-Hoon YANG  Jaeseok PARK  Eunsei PARK  Sungho KANG  

     
    LETTER-VLSI Systems

      Vol:
    E92-D No:7
      Page(s):
    1462-1465

    This paper presents a grouped scan slice encoding technique using scan slice repetition to simultaneously reduce test data volume and test application time. Using this method, many scan slices that would be incompatible with the conventional selective scan slice method can be encoded as compatible scan slices. Experiments were performed with ISCAS'89 and ITC'99 benchmark circuits, and results show the effectiveness of the proposed method.

  • Temperature-Aware NBTI Modeling Techniques in Digital Circuits

    Hong LUO  Yu WANG  Rong LUO  Huazhong YANG  Yuan XIE  

     
    PAPER-Integrated Electronics

      Vol:
    E92-C No:6
      Page(s):
    875-886

    Negative bias temperature instability (NBTI) has become a critical reliability phenomena in advanced CMOS technology. In this paper, we propose an analytical temperature-aware dynamic NBTI model, which can be used in two circuit operation cases: executing tasks with different temperatures, and switching between active and standby mode. A PMOS Vth degradation model and a digital circuits' temporal performance degradation estimation method are developed based on our NBTI model. The simulation results show that: 1) the execution of a low temperature task can decrease ΔVth due to NBTI by 24.5%; 2) switching to standby mode can decrease ΔVth by 52.3%; 3) for ISCAS85 benchmark circuits, the delay degradation can decrease significantly if the circuit execute low temperature task or switch to standby mode; 4) we have also observed the execution time's ratio of different tasks and the ratio of active to standby time both have a considerable impact on NBTI effect.

  • An Interference Cancellation Scheme for Mobile Communication Radio Repeaters

    Moohong LEE  Byungjik KEUM  Young Serk SHIM  Hwang Soo LEE  

     
    PAPER

      Vol:
    E92-B No:5
      Page(s):
    1778-1785

    An interference cancellation (ICAN) scheme for mobile communication radio repeaters is presented. When a radio repeater has a gain that is larger than the isolation between its transmit and receive antennas, it oscillates due to feedback interference signals. To prevent feedback oscillation of a radio repeater, we first formulate a feedback oscillation model of the radio repeater and then derive an ICAN model from that model. From the derived ICAN model, we show that the stability and the signal quality of the repeater depend on the repeater's gain and delay, the propagation delay on feedback paths, feedback channel characteristics, and the capability of the feedback channel estimation algorithm. It is also shown that the stability condition of the repeater does not guarantee the quality of the repeater's output signal. To guarantee repeater's stability and signal quality, an ICAN scheme based on an iterative algorithm is subsequently proposed. The simulation results confirm the relationship between the stability and signal quality of the repeater and the impact of the aforementioned factors. Using the proposed ICAN scheme, a mean error vector magnitude (quality indicator) of about 6.3% for the repeater's output signal was achieved.

  • Searchable Encryption with Keyword-Recoverability

    Ik Rae JEONG  Jeong Ok KWON  Dowon HONG  Dong Hoon LEE  

     
    LETTER-Application Information Security

      Vol:
    E92-D No:5
      Page(s):
    1200-1203

    Searchable encryption has many applications including e-mail systems and storage systems. The usefulness of searchable encryption derives from its support of keyword-testability. Keyword-testability means that a receiver of a ciphertext can test whether the ciphertext contains a specific keyword. Recently, Bellare et al. suggested an efficiently-searchable encryption scheme with keyword-recoverability as well as keyword-testability. Keyword-recoverability means that a receiver can extract the keyword from a ciphertext. All of the previous searchable encryption schemes have provided only keyword-testability. However, as explained by Bellare et al., no efficiently-searchable encryption scheme can provide even security against chosen keyword attacks. That is, Bellare et al.'s scheme assumes that no useful partial information about the keyword is known to the adversaries. In this paper, we suggest an SEKR (searchable encryption with keyword-recoverability) scheme which is secure even if the adversaries have any useful partial information about the keyword. Our scheme provides security against chosen ciphertext attacks which are stronger attacks than chosen keyword attacks. We also suggest an SEKR scheme for multi-keywords.

  • Computation of Floquet Multipliers Using an Iterative Method for Variational Equations

    Yu NUREKI  Sunao MURASHIGE  

     
    PAPER-Numerical Analysis and Optimization

      Vol:
    E92-A No:5
      Page(s):
    1331-1338

    This paper proposes a new method to numerically obtain Floquet multipliers which characterize stability of periodic orbits of ordinary differential equations. For sufficiently smooth periodic orbits, we can compute Floquet multipliers using some standard numerical methods with enough accuracy. However, it has been reported that these methods may produce incorrect results under some conditions. In this work, we propose a new iterative method to compute Floquet multipliers using eigenvectors of matrix solutions of the variational equations. Numerical examples show effectiveness of the proposed method.

  • Delay-Dependent Stability Criteria for Systems with Time-Varying Delays: State Discretization Approach

    Jeong-Wan KO  PooGyeon PARK  

     
    PAPER-Systems and Control

      Vol:
    E92-A No:4
      Page(s):
    1136-1141

    A state-discretization approach [11], which was introduced for stability of constant delayed systems, will be extended to time-varying delayed systems. The states not only in constructing the Lyapunov-Krasovskii functional but also in designing the integral inequality technique [12] will be discretized. Based on the discretized-state, [9],[17] 's piecewise analysis method will be applied to confirm the system stability in whole delay bound. Numerical examples show that the results obtained by this criterion improve the allowable delay bounds over the existing results in the literature.

  • Design for Delay Fault Testability of 2-Rail Logic Circuits

    Kentaroh KATOH  Kazuteru NAMBA  Hideo ITO  

     
    LETTER-Dependable Computing

      Vol:
    E92-D No:2
      Page(s):
    336-341

    This paper presents a scan design for delay fault testability of 2-rail logic circuits. The flip flops used in the scan design are based on master-slave ones. The proposed scan design provides complete fault coverage in delay fault testing of 2-rail logic circuits. In two-pattern testing with the proposed scan design, initial vectors are set using the set-reset operation, and the scan-in operation for initial vectors is not required. Hence, the test application time is reduced to about half that of the enhanced scan design. Because the additional function is only the set-reset operation of the slave latch, the area overhead is small. The evaluation shows that the differences in the area overhead of the proposed scan design from those of the standard scan design and the enhanced scan design are 2.1 and -14.5 percent on average, respectively.

  • Dynamic Characteristics Analysis of Analogue Networks Design Process

    Alexander M. ZEMLIAK  

     
    LETTER-VLSI Design Technology and CAD

      Vol:
    E92-A No:2
      Page(s):
    652-657

    The process of designing analogue circuits is formulated as a controlled dynamic system. For analysis of such system's properties it is suggested to use the concept of Lyapunov's function for a dynamic system. Various forms of Lyapunov's function are suggested. Analyzing the behavior of Lyapunov's function and its first derivative allowed us to determine significant correlation between this function's properties and processor time used to design the circuit. Numerical results prove the possibility of forecasting the behavior of various designing strategies and processor time based on the properties of Lyapunov's function for the process of designing the circuit.

  • Nonlinear Stability Analysis of Microwave Oscillators Using Circuit Envelope Technique

    Hamid VAHDATI  Abdolali ABDIPOUR  

     
    LETTER-Microwaves, Millimeter-Waves

      Vol:
    E92-C No:2
      Page(s):
    275-277

    In this paper, a criterion for nonlinear stability analysis of microwave oscillator has been devised. The circuit envelope method has been used for analyzing the perturbed circuit. The proposed approach is evaluated by analyzing the nonlinear stability of a practical FET oscillator.

  • A New Robust Bandpass Sampling Scheme for Multiple RF Signals in SDR System

    Chen CHI  Yu ZHANG  Zhixing YANG  

     
    LETTER-Wireless Communication Technologies

      Vol:
    E92-B No:1
      Page(s):
    326-329

    Software defined radio (SDR) technology has been widely applied for its powerful universality and flexibility in the past decade. To address the issue of bandpass sampling of multiband signals, a novel and efficient method of finding the minimum valid sampling frequency is proposed. Since there are frequency deviations due to the channel effect and hardware instability in actual systems, we also consider the guard-bands between downconverted signal spectra in determining the minimum sampling frequency. In addition, the case that the spectra within the sampled bandwidth are located in inverse placement can be avoided by our proposed method, which will reduce the complexity of the succeeding digital signal process significantly. Simulation results illustrate that the proper minimum sampling frequency can be determined rapidly and accurately.

  • A Design Method for Separable-Denominator 2D IIR Filters with a Necessary and Sufficient Stability Check

    Toma MIYATA  Naoyuki AIKAWA  Yasunori SUGITA  Toshinori YOSHIKAWA  

     
    LETTER-Digital Signal Processing

      Vol:
    E92-A No:1
      Page(s):
    307-310

    In this paper, we propose designing method for separable-denominator two-dimensional Infinite Impulse Response (IIR) filters (separable 2D IIR filters) by Successive Projection (SP) methods using the stability criteria based on the system matrix. It is generally known that separable 2D IIR filters are stable if and only if each of the denominators is stable. Therefore, the stability criteria of 1D IIR filters can be used for separable 2D IIR filters. The stability criteria based on the system matrix are a necessary and sufficient condition to guarantee stability in 1D IIR filters. Therefore, separable 2D IIR filters obtained by the proposed design method have a smaller error ripple than those obtained by the conventional design method using the stability criterion of Rouche's theorem.

  • Traveling Wave Amplification within a Waveguide

    Yoshihiko MIZUSHIMA  

     
    PAPER-Electron Tubes, Vacuum and Beam Technology

      Vol:
    E91-C No:11
      Page(s):
    1816-1819

    A novel amplification mechanism of traveling TM wave on an electron beam within a waveguide structure is proposed. Under boundary constraint of the waveguide, a hybrid coupling of longitudinal plasma wave and transverse guided one occurs to result in traveling instability. The instability refers to a backward traveling amplification. The new amplification in the waveguide due to the interactive coupling between the space charge mode and the waveguide one is firstly pointed out. The analysis is extended to the relativistic energy range to get a large gain. The features and properties are discussed for a wide frequency range as well as a high gain-bandwidth product.

  • A New Built-in Self Test Scheme for Phase-Locked Loops Using Internal Digital Signals

    Youbean KIM  Kicheol KIM  Incheol KIM  Sungho KANG  

     
    LETTER-Integrated Electronics

      Vol:
    E91-C No:10
      Page(s):
    1713-1716

    Testing PLLs (phase-locked loops) is becoming an important issue that affects both time-to-market and production cost of electronic systems. Though a PLL is the most common mixed-signal building block, it is very difficult to test due to internal analog blocks and signals. In this paper, we propose a new PLL BIST (built-in self test) using the distorted frequency detector that uses only internal digital signals. The proposed BIST does not need to load any analog nodes of the PLL. Therefore, it provides an efficient defect-oriented structural test scheme, reduced area overhead, and improved test quality compared with previous approaches.

101-120hit(309hit)