Block-wise shutdown of idle functional blocks in VLSI systems is a promising approach to reduce power consumption. Especially, multi-threshold voltage CMOS (MTCMOS) is widely accepted to save leakage power during idle time. As operating frequency increases, it requires short wake-up time to use the shutdown block in time. However, short wake-up time of a large block causes large current surge during wake-up process. This often leads to system malfunction due to severe power line noise. This is one of the serious problems for practical implementation of MTCMOS block-wise shutdown. This letter proposes an effective wake-up scheme for block-wise shutdown of low-power VLSI systems. It exploits pipelined wake-up strategy that reduces current surge during wake-up process. In this letter, the proposed scheme was analyzed and simulated from the viewpoint of power distribution network. To verify its validity, it was applied to a multiplier block in Compact Flash controller chip on a test board. According to the simulation results of equivalent R, L, and C modeling, the proposed scheme achieved significant improvement over conventional concurrent shutdown schemes.

This paper presents a Quiet-Noisy scan technique for low power delay fault testing. The novel scan cell design provides both the quiet and noisy scan modes. The toggling of scan cell outputs is suppressed in the quiet scan mode so the power is saved. Two-pattern tests are applied in the noisy scan mode so the delay fault testing is possible. The experimental data shows that the Quiet-Noisy scan technique effectively reduces the test power to 56% of that of the regular scan. The transition fault coverage is improved by 19.7% compared to an existing toggle suppression low power technique. The presented technique requires very minimal changes in the existing MUX-scan Design For Testability (DFT) methodology and needs virtually no computation. The penalties are area overhead, speed degradation, and one extra control in test mode.

The matrix inequality condition has been considered as the main condition for the stability of RHC. But it is difficult to apply the matrix inequality condition for guaranteeing the stability of any physical system because of the high gain problem brought about the high value of the final state weighting matrix. Therefore, in this study, a new stability condition for RHC is proposed and it extends the range of the final state weighting matrix guaranteeing the stability of RHC in comparison with the case of the matrix inequality condition. The proposed stability condition is based not only on a final state weighting matrix but also on a horizon size and guarantees the stability for other forms of model predictive control just like the matrix inequality condition.

The characteristics of HfO2 gate stacks, which consisted of the SiN layer deposited between the HfO2 and poly-Si gate electrode and the SiON interfacial layer were investigated. The SiN layer played important role to reduce the leakage current caused by the defect of the crystallized HfO2. The SiN layer was also effective to achieve the prevention of the interfacial reaction, the suppression of dopant penetration. Furthermore, that stack structure indicated excellent TDDB reliability fabricated by conventional high temperature processes.

Because most link-state routing protocols, such as OSPF and IS-IS, calculate routes using the Dijkstra algorithm, which poses scalability problems, implementors often introduce an artificial delay to reduce the number of route calculations. Although this delay directly affects IP packet forwarding, it can be acceptable when the network topology does not change often. However, when the topology of a network changes frequently, this delay can lead to a complete loss of IP reachability for the affected network prefixes during the unstable period. In this paper, we propose the Cached Shortest-path Tree (CST) approach, which speeds up intra-domain routing convergence without extra execution of the Dijkstra algorithm, even if the routing for a network is quite unstable. The basic idea of CST is to cache shortest-path trees (SPTs) of network topologies that appear frequently, and use these SPTs to instantly generate a routing table when the topology after a change matches one in the caches. CST depends on a characteristic that we found from an investigation of routing instability conducted on the WIDE Internet in Japan. That is, under unstable routing conditions, both frequently changing Link State Advertisements (LSAs) and their instances tend to be limited. At the end of this paper, we show CST's effectiveness by a trace-driven simulation.

This paper presents a distinct approach to the robustness stability analysis and design of linear uncertain systems. Based on the extension version of the projection method, the specific stability issue, which ensures the poles within a specific region, can be efficiently analyzed. Furthermore, we derive a simple design scheme for a class of uncertain systems. By the proposed numerical algorithm, some examples are given to demonstrate the validity and effectiveness.

A two stage non-scan design for testability method is proposed. The first stage selects test points based on an earlier testability measure conflict. A new design for testability algorithm is proposed to select test points by a fault-oriented testability measure conflict+ in the second stage. Test points are selected in the second stage based on the hard faults after the initial ATPG run of the design for testability circuit in the preliminary stage. The new testability measure conflict+ based on conflict analysis of hard-faults in the process of test generation is introduced, which emulates most general features of sequential ATPG. The new testability measure reduces testability of a fault to the minimum D or controllability of the primary outputs, and therefore, does not need observability measure any more. Effective approximate schemes are adopted to get reasonable estimation of the testability measure. A couple of effective techniques are also adopted to accelerate the process of the proposed design for testability algorithm. Experimental results show that the proposed method gets even better results than two of the recent non-scan design for testability methods nscan and lcdft.

High-temperature stability of copper (Cu) gate AlGaN/GaN high electron mobility transistors (HEMTs) was investigated. Samples were annealed at various temperatures to monitor the changes on device performances. Current-voltage performance such as drain-source current, transconductance, threshold voltage and gate leakage current has no obvious degradation up to annealing temperature of 500 and time of 5 minutes. Also up to this temperature, no copper diffusion was found at the Cu and AlGaN interface by secondary ion mass spectrometry determination. At annealing temperature of 700 and time of 5 minutes, device performance was found to have degraded. Gate voltage swing increased and threshold voltage shifted due to Cu diffusion into AlGaN. These results indicate that the Schottky contact and device performance of Cu-gate AlGaN/GaN HEMT is stable up to annealing temperature of 500. Cu is a promising candidate as gate metallization for high-performance power AlGaN/GaN HEMTs.

This paper investigates the stability problem of singular systems with saturation actuators. A Lyapunov method is employed to give the sufficient conditions for stability of closed-loop systems with saturation actuators. The controller is designed to satisfy the requirement for stability under the nonlinear saturation. In addition, a method is presented for estimating the domain of attraction of the origin.

As head-disk spacing is reduced, the effects caused by inter-molecular level interactions between head-slider and disk media are becoming a severe stability concern of head-slider's positioning in both flying height and track following directions. Therefore, there is a need to explore simple but effective methods for characterizing two dimensional (2D) stability. Ideally methods should be easy to implement in both the laboratory and in the quality control of disk drive and component manufacturing. A reading process based in-situ method is explored in this work. The method is simple and can effectively reveal the 2D stability of the head-slider in both laboratory and manufacturing environments. The results obtained also suggest that the observable sway mode vibration of the suspension can be excited earlier than the air-bearing vibration mode, when the flying height is reduced.

An IP (Internet Protocol) over WDM network is expected to be an infrastructure for the next-generation Internet by directly carrying IP packets on the WDM-based network. Among several architectures for IP over WDM networks, one promising way is to overlay a logical topology consisting of lightpaths over the physical WDM network so that IP packets are carried on the lightpaths. The conventional methods for designing the logical topology have been focusing on maximizing throughput of the traffic. However, when the WDM network is applied to IP, the end-to-end path provided by the logical topology of the WDM network is not suitable to IP since IP has its own metrics for route selection. In this paper, we propose a new heuristic algorithm to design a logical topology by considering the delay between nodes as an objective metric. This algorithm uses a non-bifurcated flow deviation to obtain a set of routes that IP packets are expected to traverse. Our proposal is then compared with conventional methods in terms of the average packet delays and throughput. It is shown that our method becomes effective when the number of wavelengths is a limited resource.

This paper introduces a design for testability (DFT) scheme for delay faults of a controller-data path circuit. The scheme makes use of both scan and non-scan techniques. First, the data path is transformed into a hierarchically two-pattern testable (HTPT) data path based on a non-scan approach. Then an enhanced scan (ES) chain is inserted on the control lines and the status lines. The ES chain is extended via the state register of the controller. If necessary, the data path is further modified. Then a test controller is designed and integrated to the circuit. Our approach is mostly based on path delay fault model. However the multiplexer (MUX) select lines and register load lines are tested as register transfer level (RTL) segments. For a given circuit, the area overhead incurred by our scheme decreases substantially with the increase in bit-width of the data path of the circuit. The proposed scheme supports hierarchical test generation and can achieve fault coverage similar to that of the ES approach.

To sample a band-limited analog signal directly from the high frequency down to the baseband for the digital signal processing with significantly reduced computation, several concepts of the bandpass sampling are introduced. In this paper, a robust bandpass sampling scheme when there exist frequency deviations due to the channel effect and hardware instability is proposed for practical use, and the effects of the frequency deviations are discussed to select a proper sampling frequency.

As an enhancement mechanism for the end-to-end congestion control, AQM (Active Queue Management) can keep smaller queuing delay and higher throughput by purposefully dropping the packets at the intermediate nodes. Comparing with RED algorithm, although the PI (Proportional-Integral) controller for AQM designed by C. Hollot improves the stability, it seems unscientific to tune the controller parameters through trial-error, moreover the transient performance of the PI controller is not perfect, such as the regulating time is too long. In order to overcome this drawback, in this paper, the PID (Proportional-Integral-Differential) controller is proposed to speed up the responsiveness of AQM system. The controller parameters are tuned based on the determined gain and phase margins. The simulation results show that the integrated performance of the PID controller is obviously superior to that of the PI controller.

We introduce a PLL (Phase Locked Loop) for low-power and a low supply voltage applications. Because the PLL is a key device of the system LSIs used in mobile terminals, it is very important that PLLs operate under a low supply voltage to reduce power consumption. We investigate the limitations of the conventional VCO that we proposed in Ref.[5] and propose a modified VCO that uses common load transistors. Furthermore, we propose a charge pump that uses a dynamic output stage op-amp and a stability technique for the CMOS process, and it does not contain any special resistors. The results of an evaluation of a device fabricated using a standard logic 0.18-µm CMOS process demonstrated that the proposed PLL operated above 1.0 GHz with a 1.2-V supply voltage and it produced only a small amount of jitter that was lower than 78 psp-p.

A blind equalizer which uses the differential constant modulus algorithm (DCMA) is introduced. An anchored FIR equalizer applied to a first-order autoregressive channel and updated according to the DCMA is shown to converge to the inverse of that channel regardless of the initial tap-weights and the gain along the direct path.

The purpose of a testability analysis program is to estimate the difficulty of testing a fault. A good measurement can give an early warning about the testing problem so as to provide guidance in improving the testability of a circuit. There have been researches attempting to efficiently compute the testability analysis. Among those, the Controllability and Observability Procedure COP can calculate the testability value of a stuck-at fault efficiently in a tree-structured circuit but may be very inaccurate for a general circuit. The inaccuracy in COP is due to the ignorance of signal correlations. Recently, the algorithm of TAIR in [5] proposes a testability analysis algorithm, which starts from the result of COP and then gradually improves the result by applying a set of rules. The set of rules in TAIR can capture some signal correlations and therefore the results of TAIR are more accurate than COP. In this paper, we first prove that the rules in TAIR can be replaced by a closed-form formulation. Then, based on the closed-form formulation, we proposed two novel techniques to further improve the testability analysis results. Our experimental results have shown improvement over the results of TAIR.

We present the effects of N2O plasma treatment for hot carrier reliability and gate oxide stability in excimer-laser annealed poly-Si TFTs. N2O plasma treatment between SiO2 and poly-Si suppresses both the reduction in mobility caused by hot carrier stress and the Vth shift caused by gate bias stress. The results of XPS spectra and the energy distribution of the trap state density of stressed TFTs show that the introduction of Si-N bonds plays an important role in poly-Si TFT reliability.

A procedure to remove redundancies in sequential circuits is proposed using strongly unreachable states, which are the states with no incoming transitions. Test generation is used to find undetectable faults related to two or more strongly unreachable states. Experimental results show the new procedure can find more redundancies of sequential circuits.

In this paper we analyze an asymptotic stability of nonlinear singularly perturbed systems and propose a composite control with gain scheduling where the fast controller is the gain scheduled controller and the slow state plays a role of slowly varying parameters in gain scheduling. Specifically, the slow controller is designed by the slow manifold to stabilize the reduced slow system. As a result, the slow manifold of the system is the same as the designed manifold.