The effect of the hidden terminal (HT) over multi-hop cascaded wireless networks with the omni-directional full-duplex relays will cause data collision. We allocate the frequency band among different hops in an orthogonal way based on link grouping strategy to avoid this HT problem. In order to maximize the achievable rate, an optimal frequency allocation scheme is proposed by boundary alignment. Performance analyses are provided and further validated by the simulation results.

In this paper, we propose a construction of non-binary WOM (Write-Once-Memory) codes for WOM storages such as flash memories. The WOM codes discussed in this paper are fixed rate WOM codes where messages in a fixed alphabet of size M can be sequentially written in the WOM storage at least t*-times. In this paper, a WOM storage is modeled by a state transition graph. The proposed construction has the following two features. First, it includes a systematic method to determine the encoding regions in the state transition graph. Second, the proposed construction includes a labeling method for states by using integer programming. Several novel WOM codes for q level flash memories with 2 cells are constructed by the proposed construction. They achieve the worst numbers of writes t* that meet the known upper bound in the range 4≤q≤8, M=8. In addition, we constructed fixed rate non-binary WOM codes with the capability to reduce ICI (inter cell interference) of flash cells. One of the advantages of the proposed construction is its flexibility. It can be applied to various storage devices, to various dimensions (i.e, number of cells), and various kind of additional constraints.

The purpose of this study is to investigate the effects of device size on non-visual icon search using a touch interface with voice output. We conducted an experiment in which twelve participants searched for the target icons with four different-sized touchscreen devices. We analyzed the search time, search strategies and subjective evaluations. As a result, mobile devices with a screen size of 4.7 inches had the shortest search time and obtained the highest subjective evaluation among the four devices.

In this letter, we investigate the computation offloading problem in cloud based multi-robot systems, in which user weights, communication interference and cloud resource limitation are jointly considered. To minimize the system cost, two offloading selection and resource allocation algorithms are proposed. Numerical results show that the proposed algorithms both can greatly reduce the overall system cost, and the greedy selection based algorithm even achieves near-optimal performance.

Multi-hypothesis prediction technique, which exploits inter-frame correlation efficiently, is widely used in block-based distributed compressive video sensing. To solve the problem of inaccurate prediction in multi-hypothesis prediction technique at a low sampling rate and enhance the reconstruction quality of non-key frames, we present a resample-based hybrid multi-hypothesis scheme for block-based distributed compressive video sensing. The innovations in this paper include: (1) multi-hypothesis reconstruction based on measurements reorganization (MR-MH) which integrates side information into the original measurements; (2) hybrid multi-hypothesis (H-MH) reconstruction which mixes multiple multi-hypothesis reconstructions adaptively by resampling each reconstruction. Experimental results show that the proposed scheme outperforms the state-of-the-art technique at the same low sampling rate.

In this paper, the Voronoi region of the transmitted codeword is employed to improve the sphere bound on the maximum-likelihood decoding (MLD) performance of binary linear block codes over additive white Gaussian noise (AWGN) channels. We obtain the improved sphere bounds both on the frame-error probability and the bit-error probability. With the framework of the sphere bound proposed by Kasami et al., we derive the conditional decoding error probability on the spheres by defining a subset of the Voronoi region of the transmitted codeword, since the Voronoi regions of a binary linear block code govern the decoding error probability analysis over AWGN channels. The proposed bound improves the sphere bound by Kasami et al. and the sphere bound by Herzberg and Poltyrev. The computational complexity of the proposed bound is similar to that of the sphere bound by Kasami et al.

A 197mW 70ms-latency Full-HD 12-channel video-processing SoC for in-vehicle information systems has been implemented in 16nm CMOS. The SoC integrates 17 video processors of 6 types to operate video processing independently of other processing in CPU/GPU. The synchronous scheme between the video processors achieves 70ms low-latency for driver assistance. The optimized implementation of lossy and lossless video-data compression reduces memory access data by half and power consumption by 20%.

A fully integrated CMOS pulse transceiver with digital beam-formability for mm-wave active imaging is presented. The on-chip pulse transmitter of the transceiver includes an eight-element antenna array connected to eight pulse transmitters and a built-in relative pulse delay calibration system. The receiver employs a non-coherent detection method by using a FET direct-power detection circuit integrated with an antenna. The receiver dipole-patch antenna derives from the transmitter antenna but is modified with an on-chip DC-bias tail by shorting two arms of the dipole. The bandwidth of the receiver antenna with the DC-bias tail is designed to achieve 50.4-GHz in simulation and to cover the bandwidth of transmitter antennas. The output of the receiver antenna is connected to a resistive self-mixer followed by an on-chip low pass filter and then an amplifier stage. The built-in relative pulse delay calibration system is used to align the pulse delays of each transmitter array elements for the purpose of controlling the beam steering towards imaging objects. Both transmitter and receiver chips are fabricated in a 65-nm CMOS technology process. Measured pulse waveform of the receiver after relatively aligning all Tx's pulses is 0.91 mV (peak-peak) and 3-ns duration with a distance of 25mm between Rx and Tx. Beam steering angles are achieved in measurement by changing the digital delay code of antenna elements. Experimental results show that the proposed on-chip transceiver has an ability of digital transmitted-pulse calibration, controlling of beam-steeting, and pulse detection for active imaging applications.

It has been reported that malicious third-party IC vendors often insert hardware Trojans into their IC products. How to detect them is a critical concern in IC design process. Machine-learning-based hardware-Trojan detection gives a strong solution to tackle this problem. Hardware-Trojan infected nets (or Trojan nets) in ICs must have particular Trojan-net features, which differ from those of normal nets. In order to classify all the nets in a netlist designed by third-party vendors into Trojan nets and normal ones by machine learning, we have to extract effective Trojan-net features from Trojan nets. In this paper, we first propose 51 Trojan-net features which describe well Trojan nets. After that, we pick up random forest as one of the best candidates for machine learning and optimize it to apply to hardware-Trojan detection. Based on the importance values obtained from the optimized random forest classifier, we extract the best set of 11 Trojan-net features out of the 51 features which can effectively classify the nets into Trojan ones and normal ones, maximizing the F-measures. By using the 11 Trojan-net features extracted, our optimized random forest classifier has achieved at most 100% true positive rate as well as 100% true negative rate in several Trust-HUB benchmarks and obtained the average F-measure of 79.3% and the accuracy of 99.2%, which realize the best values among existing machine-learning-based hardware-Trojan detection methods.

Hotspots occur frequently in 3D multi-core processors (3D-MCPs), and they may adversely impact both the reliability and lifetime of a system. We present a new thermally constrained task scheduler based on a thermal-pattern-aware voltage assignment (TPAVA) to reduce hotspots in and optimize the performance of 3D-MCPs. By analyzing temperature profiles of different voltage assignments, TPAVA pre-emptively assigns different initial operating-voltage levels to cores for reducing temperature increase in 3D-MCPs. The proposed task scheduler consists of an on-line allocation strategy and a new voltage-scaling strategy. In particular, the proposed on-line allocation strategy uses the temperature-variation rates of the cores and takes into two important thermal behaviors of 3D-MCPs that can effectively minimize occurrences of hotspots in both thermally homogeneous and heterogeneous 3D-MCPs. Furthermore, a new vertical-grouping voltage scaling (VGVS) strategy that considers thermal correlation in 3D-MCPs is used to handle thermal emergencies. Experimental results indicate that, when compared to a previous online thermally constrained task scheduler, the proposed task scheduler can reduce hotspot occurrences by approximately 66% (71%) and improve throughput by approximately 8% (2%) in thermally homogeneous (heterogeneous) 3D-MCPs. These results indicate that the proposed task scheduler is an effective technique for suppressing hotspot occurrences and optimizing throughput for 3D-MCPs subject to thermal constraints.

The extraction of micro-motion parameters is deeply influenced by the precision of estimation on translational motion parameters. Based on the periodicity of micro-motion, the quadratic polynomial fitting is carried out among range delays to align envelope. The micro-motion component of phase information is eliminated by conjugate multiplication after which the translational motion parameters are estimated. Then the translational motion is precisely compensated through the third order polynomial fitting. Results of simulation demonstrate that the algorithm put forward here can realize the precise compensation for translational motion parameters even under an environment with low signal noise ratio (SNR).

Sponsored search is a mechanism that shows the appropriate advertisements (ads) according to search queries. The orders and payments of ads are determined by the auction. However, the externalities which give effects to CTR and haven't been considered in some existing works because the mechanism with externalities has high computational cost. In addition, some algorithms which can calculate the approximated solution considering the externalities within the polynomial-time are proposed, however, it assumed that one bidder can propose only a single ad. In this paper, we propose the approximation allocation algorithm that one bidder can offer many ads considering externalities. The proposed algorithm employs the concept of the combinatorial auction in order to consider the combinational bids. In addition, the proposed algorithm can find the approximated allocation by the dynamic programming. Moreover, we prove the computational complexity and the monotonicity of the proposed mechanism, and demonstrate computational costs and efficiency ratios by changing the number of ads, slots and maximum bids. The experimental results show that the proposed algorithm can calculate 0.7-approximation solution even though the full search can't find solutions in the limited times.

In this paper, we treat (k, L, n) ramp secret sharing schemes (SSSs) that can detect impersonation attacks and/or substitution attacks. First, we derive lower bounds on the sizes of the shares and random number used in encoding for given correlation levels, which are measured by the mutual information of shares. We also derive lower bounds on the success probabilities of attacks for given correlation levels and given sizes of shares. Next we propose a strong (k, L, n) ramp SSS against substitution attacks. As far as we know, the proposed scheme is the first strong (k, L, n) ramp SSSs that can detect substitution attacks of at most k-1 shares. Our scheme can be applied to a secret SL uniformly distributed over GF(pm)L, where p is a prime number with p≥L+2. We show that for a certain type of correlation levels, the proposed scheme can achieve the lower bounds on the sizes of the shares and random number, and can reduce the success probability of substitution attacks within nearly L times the lower bound when the number of forged shares is less than k. We also evaluate the success probability of impersonation attack for our schemes. In addition, we give some examples of insecure ramp SSSs to clarify why each component of our scheme is essential to realize the required security.

A pseudorandom number generator is widely used in cryptography. A cryptographic pseudorandom number generator is required to generate pseudorandom numbers which have good statistical properties as well as unpredictability. An m-sequence is a linear feedback shift register sequence with maximal period over a finite field. M-sequences have good statistical properties, however we must nonlinearize m-sequences for cryptographic purposes. A geometric sequence is a binary sequence given by applying a nonlinear feedforward function to an m-sequence. Nogami, Tada and Uehara proposed a geometric sequence whose nonlinear feedforward function is given by the Legendre symbol. They showed the geometric sequences have good properties for the period, periodic autocorrelation and linear complexity. However, the geometric sequences do not have the balance property. In this paper, we introduce geometric sequences of two types and show some properties of interleaved sequences of the geometric sequences of two types. These interleaved sequences have the balance property and double the period of the geometric sequences by the interleaved structure. Moreover, we show correlation properties and linear complexity of the interleaved sequences. A key of our observation is that the second type geometric sequence is the complement of the left shift of the first type geometric sequence by half-period positions.

As application hardware designs and implementations in a short term are required, high-level synthesis is more and more essential EDA technique nowadays. In deep-submicron era, interconnection delays are not negligible even in high-level synthesis thus distributed-register and -controller architectures (DR architectures) have been proposed in order to cope with this problem. It is also profitable to take data-bitwidth into account in high-level synthesis. In this paper, we propose a bitwidth-aware high-level synthesis algorithm using operation chainings targeting Tiled-DR architectures. Our proposed algorithm optimizes bitwidths of functional units and utilizes the vacant tiles by adding some extra functional units to realize effective operation chainings to generate high performance circuits without increasing the total area. Experimental results show that our proposed algorithm reduces the overall latency by up to 47% compared to the conventional approach without area overheads by eliminating unnecessary bitwidths and adding efficient extra FUs for Tiled-DR architectures.

In this correspondence, two types of multiple binary zero correlation zone (ZCZ) sequence sets with inter-set zero cross-correlation zone (ZCCZ) are constructed. Based on orthogonal matrices with order N×N, multiple binary ZCZ sequence sets with inter-set even and odd ZCCZ lengthes are constructed, each set is an optimal ZCZ sequence set with parameters (2N2, N, N+1)-ZCZ, among these ZCZ sequence sets, sequences possess ideal cross-correlation property within a zone of length 2Z or 2Z+1. These resultant multiple ZCZ sequence sets can be used in quasi-synchronous CDMA systems to remove the inter-cell interference (ICI).

In this paper, a weighted multiple bit flipping (WMBF) algorithman for decoding low-density parity-check (LDPC) codes is proposed first. Then the improved WMBF algorithm which we call the efficient weighted bit-flipping (EWBF) algorithm is developed. The EWBF algorithm can dynamically choose either multiple bit-flipping or single bit-flipping in each iteration according to the log-likelihood ratio of the error probability of the received bits. Thus, it can efficiently increase the convergence speed of decoding and prevent the decoding process from falling into loop traps. Compared with the parallel weighted bit-flipping (PWBF) algorithm, the EWBF algorithm can achieve significantly lower computational complexity without performance degradation when the Euclidean geometry (EG)-LDPC codes are decoded. Furthermore, the flipping criterion does not require any parameter adjustment.

A relay assignment scheme is proposed in this paper that minimizes the mean delay of transmission for energy harvesting (EH) cooperative communication systems, whose source node and relay nodes are all equipped with energy harvesters. We jointly consider the long-term channel side information (CSI) and energy side information (ESI) of all nodes, and formulate the delay minimization problem as an integer programming problem. To solve this problem, a refined cyclic coordinate method (RCCM) is proposed that considers the cases of fixed-packet-length (FPL) and variable-packet-length (VPL) transmission. Simulation results show that the proposed scheme achieves performance close to that of the real-time relay selection (RRS) scheme with instantaneous CSI and ESI, which gives upper bound of the performance. Moreover, compared with the simple relay rotation (SRR) scheme where each relay has equal service time, the performance of the proposed scheme is significantly improved.

Coordinated checkpointing is a widely-used checkpoint/restart protocol for fault-tolerance in large-scale HPC systems. However, this protocol will involve massive amounts of I/O concentration, resulting in considerably high checkpoint overhead and high energy consumption. This paper focuses on speculative checkpointing, a CPR mechanism that allows for temporal distribution of checkpointings to avoid I/O concentration. We propose execution time and energy models for speculative checkpointing, and investigate energy-performance characteristics when speculative checkpointing is adopted in exascale systems. Using these models, we study the benefit of speculative checkpointing over coordinated checkpointing under various realistic scenarios for exascale HPC systems. We show that, compared to coordinated checkpointing, speculative checkpointing can achieve up to a 11% energy reduction at the cost of a relatively-small increase in the execution time. In addition, a significant energy-performance trade-off is expected when the system scale exceeds 1.2 million nodes.

This letter describes the development and implementation of the lane detection system accelerated by the neuromorphic hardware. Because the neuromorphic hardware has inherently parallel nature and has constant output latency regardless the size of the knowledge, the proposed lane detection system can recognize various types of lanes quickly and efficiently. Experimental results using the road images obtained in the actual driving environments showed that white and yellow lanes could be detected with an accuracy of more than 94 percent.