In classical routing protocols, geographical distances/locations are typically used as the metric to select the best route, under the assumption that shorter distances exhibit lower energy consumption and nodes within the communication range of the sender can receive packets with a certain success probability. However, in underwater acoustic sensor networks (UASNs), sound propagation in the ocean medium is more complex than that in the air due to many factors, including sound speed variations and the interaction of sound waves with the sea surface and floor, causing the sound rays to bend. Therefore, propagation of sound is anisotropic in water, and may cause a phenomenon called shadow zone where nodes in the communication range of the sender cannot hear any signal. This renders conventional routing protocols no longer energy-efficient. In this paper, we make use of the ray-model to account for the environment-dependent behavior of the underwater channel, re-define nodes' one-hop neighbors based on signal attenuation rather than geographical distance, and design a distributed energy-efficient routing protocol for UASNs. Results show that our ray-model-based routing policy consistently outperforms the shortest path policy, and performs very close to the optimal one in several scenarios.

Apriori-based mining algorithms enumerate frequent patterns efficiently, but the resulting large number of patterns makes it difficult to directly apply subsequent learning tasks. Recently, efficient iterative methods are proposed for mining discriminative patterns for classification and regression. These methods iteratively execute discriminative pattern mining algorithm and update example weights to emphasize on examples which received large errors in the previous iteration. In this paper, we study a family of loss functions that induces sparsity on example weights. Most of the resulting example weights become zeros, so we can eliminate those examples from discriminative pattern mining, leading to a significant decrease in search space and time. In computational experiments we compare and evaluate various loss functions in terms of the amount of sparsity induced and resulting speed-up obtained.

Ternary content addressable memory (TCAM) is popular LSI for use in high-throughput forwarding engines on routers. However, the unique structure applied in TCAM consume huge amounts of power, therefore it restricts the ability to handle large lookup table capacity in IP routers. In this paper, we propose a commodity-memory based hardware architecture for the forwarding information base (FIB) application that solves the substantial problems of power and density. The proposed architecture is examined by a fabricated test chip with 40 nm embedded DRAM (eDRAM) technology, and the effect of power reduction verified is greatly lower than conventional TCAM based and the energy metric achieve 0.01 fJ/bit/search. The power consumption is almost 0.5 W at 250 Msps and 8M entries.

Many successful methods for recognizing human action are spatio-temporal interest point (STIP) based methods. Given a test video sequence, for a matching-based method using a voting mechanism, each test STIP casts a vote for each action class based on its mutual information with respect to the respective class, which is measured in terms of class likelihood probability. Therefore, two issues should be addressed to improve the accuracy of action recognition. First, effective STIPs in the training set must be selected as references for accurately estimating probability. Second, discriminative STIPs in the test set must be selected for voting. This work uses ε-nearest neighbors as effective STIPs for estimating the class probability and uses a variance filter for selecting discriminative STIPs. Experimental results verify that the proposed method is more accurate than existing action recognition methods.

Content addressable memory is widely used for fast lookup table data searching, but it often consumes considerable power. Moreover, designing the suitable content addressable memory architecture for a specific application also consumes lots of time, since the behavioral simulation is often done in the transistor level. SystemC is a system-level modeling language and simulation platform, providing high simulation efficiency for hardware software co-design. Unfortunately, SystemC does not provide the function for estimating power dissipation of a structure design. In this paper, a SystemC-based fast content addressable memory power estimation method is presented for estimating the power dissipation of the match-line circuit, the search-line circuit, and the storage cell array of content addressable memory in the early design stage. The mathematical equations and behavioral patterns are used as the inputs of power estimation model. The simulation results based on 10 Mibench benchmarks show that the simulation time of the proposed method is in average 1233 times faster than that of HSPICE simulator with only 3.51% error rate.

In this paper, we further study linear network error correction code on a multicast network and attempt to establish a connection between linear network error correction codes and representable matroids. We propose a similar but more accurate definition of matroidal error correction network which has been introduced by K. Prasad et al. Moreover, we extend this concept to a more general situation when the given linear network error correction codes have different error correcting capacity at different sinks. More importantly, using a different method, we show that a multicast error correction network is scalar-linearly solvable if and only if it is a matroidal error correction network.

This paper proposes a novel high-temperature superconducting dual-band bandpass filter (HTS-DBPF), that employs a broadside coupling structure, in which quarter-wavelength resonators are formed on opposite sides of each substrate. This structure provides a dual-band operation of the BPF and flexibility, in the sense of having a wide range in selecting two center passband frequencies of the HTS-DBPF. This paper employs the ratio of the lower and higher center passband frequencies, α, as a criterion for evaluating the flexibility. The obtained α ranges are from 1 to 4.7, which are the widest for DBPFs for mobile communications applications, to the best knowledge of the authors. This paper presents a 2.4-/2.9-GHz band HTS-DBPF, as an experimental example, using a YBCO film deposited on an MgO substrate. The measured frequency responses of the HTS-DBPF agree with the electromagnetic simulated results. Measurement and simulation results confirm that the proposed filter architecture is effective in configuring a DBPF that can set each center passband frequency widely.

We have proposed a method of identifying superspreaders by flow sampling and a method of filtering legitimate hosts from the identified superspreaders using a white list. However, the problem of how to optimally set parameters of φ, the measurement period length, m*, the identification threshold of the flow count m within φ, and H*, the identification probability for hosts with m=m*, remained unsolved. These three parameters seriously impact the ability to identify the spread of infection. Our contributions in this work are two-fold: (1) we propose a method of optimally designing these three parameters to satisfy the condition that the ratio of the number of active worm-infected hosts divided by the number of all vulnerable hosts is bound by a given upper-limit during the time T required to develop a patch or an anti-worm vaccine, and (2) the proposed method can optimize the identification accuracy of worm-infected hosts by maximally using a limited amount of memory resource of monitors.

A complete 4-level pulse amplitude modulation (4-PAM) serial link transceiver including a wide frequency range clock generator and clock data recovery (CDR) is proposed in this paper. A dual-loop architecture, consisting of a frequency locked loop (FLL) and a phase locked loop (PLL), is employed for the wide frequency range clocks. The generated clocks from the FLL (clock generator) and the PLL (CDR) are utilized for a transmitter clock and a receiver clock, respectively. Both FLL and PLL employ the identical voltage controlled oscillators consisting of ring-type delay-cells. To improve the frequency tuning range of the VCO, deep triode PMOS loads are utilized for each delay-cell, since the turn-on resistance of the deep triode PMOS varies substantially by the gate-voltage. As a result, fabricated in a 0.13-µm CMOS process, the proposed 4-PAM transceiver operates from 1.5 Gb/s to 9.7 Gb/s with a bit error rate of 10-12. At the maximum data-rate, the entire power dissipation of the transceiver is 254 mW, and the measured jitter of the recovered clock is 1.61 psrms.

Petri nets are a kind of formal language that are widely applied in concurrent systems associated with resource allocation due to their abilities of the natural description on resource allocation and the precise characterization on deadlock. Weighted System of Simple Sequential Processes with Resources (WS3PR) is an important subclass of Petri nets that can model many resource allocation systems in which 1) multiple processes may run in parallel and 2) each execution step of each process may use multiple units from a single resource type but cannot use multiple resource types. We first prove that the liveness problem of WS3PR is co-NP-hard on the basis of the partition problem. Furthermore, we present a necessary and sufficient condition for the liveness of WS3PR based on two new concepts called Structurally Circular Wait (SCW) and Blocking Marking (BM), i.e., a WS3PR is live iff each SCW has no BM. A sufficient condition is also proposed to guarantee that an SCW has no BM. Additionally, we show some advantages of using SCW to analyze the deadlock problem compared to other siphon-based ones, and discuss the relation between SCW and siphon. These results are valuable to the further research on the deadlock prevention or avoidance for WS3PR.

In order to execute coherent Doppler processing in a high range-rate scenario, whether it is for detection, estimation or imaging, range walk embedded in target return should be compensated first. In case of a bistatic radar geometry where a transmitter, a receiver and a target can be all moving, the extent of range walk depends on their relative positions and velocities. This paper presents a coherent Doppler processing algorithm to achieve target detection and Doppler frequency estimation of a target under a bistatic radar geometry. This algorithm is based on the assumption that a target has constant Doppler frequency during a coherent processing interval (CPI). Thus, we first show under what condition the assumption could be valid. We next develop an algorithm, along with its implementation procedures where the region of range walk, called a window, is manipulated. Finally, the performance of a proposed algorithm is examined through simulations.

This paper proposes a method for evaluating visual differences caused by decimation. In many applications it is important to evaluate visual differences of two different images. There exist many image assessment methods that utilize the model of the human visual system (HVS), such as the visual difference predictor (VDP) and the Sarnoff visual discrimination model. In this paper, we extend and elaborate on the conventional image assessment method for the purpose of evaluating the visual difference caused by the image decimation. Our method matches actual human evaluation more and requires less computational complexity than the conventional method.

This paper shows a virus scanning engine using two-stage matching. In the first stage, a binary CAM emulator quickly detects a part of the virus pattern, while in the second stage, the MPU detects the full length of the virus pattern. The binary CAM emulator is realized by an index generation unit (IGU) based on row-shift decomposition. The proposed system uses two off-chip SRAMs and a small FPGA. Thus, the cost and the power consumption are lower than the TCAM-based system. The system loaded 1,290,617 ClamAV virus patterns. As for the area and throughput, this system outperforms existing two-stage matching systems using FPGAs.

The mining problem over data streams has recently been attracting considerable attention thanks to the usefulness of data mining in various application fields of information science, and sequence data streams are so common in daily life. Therefore, a study on mining sequential patterns over sequence data streams can give valuable results for wide use in various application fields. This paper proposes a new framework for mining novel interesting sequential patterns over a sequence data stream and a mining method based on the framework. Assuming that a sequence with small time-intervals between its data elements is more valuable than others with large time-intervals, the novel interesting sequential pattern is defined and found by analyzing the time-intervals of data elements in a sequence as well as their orders. The proposed framework is capable of obtaining more interesting sequential patterns over sequence data streams whose data elements are highly correlated in terms of generation time.

This paper presents a fine-grain bit-serial reconfigurable VLSI architecture using multiple-valued switch blocks and binary logic modules. Multiple-valued signaling is utilized to implement a compact switch block. A binary-controlled current-steering technique is introduced, utilizing a programmable three-level differential-pair circuit to implement a high-performance low-power arbitrary two-variable binary function, and increase the noise margins in comparison with the quaternary-controlled differential-pair circuit. A current-source sharing technique between a series-gating differential-pair circuit and a current-mode D-latch is proposed to reduce the current source count and improve the speed. It is demonstrated that the power consumption and the delay of the proposed multiple-valued cell based on the binary-controlled current-steering technique and the current-source-sharing technique are reduced to 63% and 72%, respectively, in comparison with those of a previous multiple-valued cell.

In this paper, we propose a new class of two dimensional (2D) M-channel (M-ch) non-separable filter banks (FBs) based on cosine modulated filter banks (CMFBs) via a new diagonally modulation scheme. Until now, many researchers have proposed 2D non-separable CMFBs. Nevertheless, efficient direction-selective CMFBs have not been yet. Thanks to our new modulations with diagonal shifts, proposed CMFBs have several frequency supports including direction-selective ones which cannot be realized by conventional ones. In a simulation, we show design examples of proposed CMFBs and their various directional frequency supports.

This study investigated the test-retest reliability and the criterion-related validity of the Implicit Association Test (IAT [1]) that was developed for measuring shyness among Japanese people. The IAT has been used to measure implicit stereotypes, as well as self-concepts, such as implicit shyness and implicit self-esteem. We administered the shyness IAT and the self-esteem IAT to participants (N = 59) on two occasions over a one-week interval (Time 1 and Time 2) and examined the test-retest reliability by correlating shyness IATs between the two time points. We also assessed the criterion-related validity by calculating the correlation between implicit shyness and implicit self-esteem. The results indicated a sufficient positive correlation coefficient between the scores of implicit shyness over the one-week interval (r = .67, p < .01). Moreover, a strong negative correlation coefficient was indicated between implicit shyness and implicit self-esteem (r = -.72, p < .01). These results confirmed the test-retest reliability and the criterion-related validity of the Japanese version of the shyness IAT, which is indicative of the validity of the test for assessing implicit shyness.

In this paper, we propose a new online authoring tool for e-Learning system to meet the social demands for internationalized higher education. The tool includes two functions – an authoring function for creating video-based content by the instructor, and a viewing function for self-learning by students. In the authoring function, an instructor creates key markings onto the raw video stream to produce virtual video clips related to each slide. With key markings, some parts of the raw video stream can be easily skipped. The virtual video clips form an aggregated video stream that is used to synchronize with the slide presentation to create learning content. The synchronized content can be previewed immediately at the client computer prior to saving at the server. The aggregated video becomes the baseline for the viewing function. Based on aggregated video stream methodology, content editing requires only the changing of key markings without editing the raw video file. Furthermore, video and pointer synchronization is also proposed for enhancing the students' learning efficiency. In viewing function, video quality control and an adaptive video buffering method are implemented to support usage in various network environments. The total system is optimized to support cross-platform and cloud computing to break the limitation of various usages. The proposed method can provide simple authoring processes with clear user interface design for instructors, and help students utilize learning contents effectively and efficiently. In the user acceptance evaluation, most respondents agree with the usefulness, ease-of-use, and user satisfaction of the proposed system. The overall results show that the proposed authoring and viewing tools have higher user acceptance as a tool for e-Learning.

The 60GHz millimeter-wave (mmWave) wireless technology is a focus of increasing attention, since its ability to transmit more than Gbps PHY data rate makes it suitable for high-speed, short-range applications such as peer-to-peer synchronization and kiosk terminals. In the case of short-range communication with a range of several tens of centimeters, only terminals present in this communication range will be affect and communication is considered to be on a one-to-one basis. In one-to-one communication, a simpler and more efficient access mechanism is preferable. The ability of current CSMA/CA based MAC, for example MAC of IEEE 802.11 WLAN systems, to achieve high throughput is limited by the low MAC efficiency caused by high signal exchange overhead, such as interframe space (IFS) and acknowledgement. This paper proposes an ACK/NACK mechanism that enhances the throughput in short-range one-to-one communication. The ACK/NACK mechanism uses Negative ACK (NACK) as the acknowledgement policy to reduce the overhead of ACK and the transmitter switches the required acknowledgement policy to ACK based on a switchover threshold. It solves a problem arising from NACK, namely, that NACK has no mechanism for keeping alive. We evaluate the throughput of the ACK/NACK mechanism by both theoretical analysis and computer simulation. The proposed ACK/NACK mechanism is implemented in 65 nm CMOS process (BBIC); we connect this BBIC to a 60 GHz RFIC and exchange frames wirelessly. In this experiment, it is verified that the ACK/NACK mechanism enhances throughput.

This letter studies a digital return map that is a mapping from a set of lattice points to itself. The digital map can exhibit various periodic orbits. As a typical example, we present the digital logistic map based on the logistic map. Two fundamental results are shown. When the logistic map has a unique periodic orbit, the digital map can have plural periodic orbits. When the logistic map has an unstable period-3 orbit that causes chaos, the digital map can have a stable period-3 orbit with various domain of attractions.