Hua FAN Quanyuan WU Jianfeng ZHANG
Despite the improvement of the accuracy of RFID readers, there are still erroneous readings such as missed reads and ghost reads. In this letter, we propose two effective models, a Bayesian inference-based decision model and a path-based detection model, to increase the accuracy of RFID data cleaning in RFID based supply chain management. In addition, the maximum entropy model is introduced for determining the value of sliding window size. Experiment results validate the performance of the proposed method and show that it is able to clean raw RFID data with a higher accuracy.
Xianling WANG Xin ZHANG Hongwen YANG Dacheng YANG
This paper investigates the transmission capacity of open-loop spatial multiplexing with zero-forcing receivers in overlaid ad hoc networks. We first derive asymptotic closed-form expressions for the transmission capacity of two coexisting networks (a primary network vs. a secondary network). We then address a special case with equal numbers of transmit and receive antennas through exact analysis. Numerical results validate the accuracy of our expressions. Our findings show that the overall transmission capacity of coexisting networks will improve significantly over that of a single network if the primary network can tolerate a slight outage probability increase. This improvement can be further boosted if more streams are configured in the spatial multiplexing scheme; less improvement is achieved by placing more antennas at the receive side than the transmit side. However, when the stream number exceeds a certain limit, spatial multiplexing will produce negative effect for the overlaid network.
Young-Woong KO Ho-Min JUNG Wan-Yeon LEE Min-Ja KIM Chuck YOO
In this paper, we propose a stride static chunking deduplication algorithm using a hybrid approach that exploits the advantages of static chunking and byte-shift chunking algorithm. The key contribution of our approach is to reduce the computation time and enhance deduplication performance. We assume that duplicated data blocks are generally gathered into groups; thus, if we find one duplicated data block using byte-shift, then we can find subsequent data blocks with the static chunking approach. Experimental results show that stride static chunking algorithm gives significant benefits over static chunking, byte-shift chunking and variable-length chunking algorithm, particularly for reducing processing time and storage space.
Keita MOCHIZUKI Hiroshi ARUGA Hiromitsu ITAMOTO Keitaro YAMAGISHI Yuichiro HORIGUCHI Satoshi NISHIKAWA Ryota TAKEMURA Masaharu NAKAJI Atsushi SUGITATSU
We have succeeded in demonstrating high-performance four-channel 25 Gb/s integrated receiver for 100 Gb/s Ethernet with a built-in spatial Demux optics and an integrated PD array. All components which configure to the Demux optics adhered to a prism. Because of the shaping accuracy for prism, the insertion loss was able to suppress to 0.8 dB with small size. The connection point of the package for high speed electrical signals was improved to decrease the transmission loss. The small size of 12 mm 17 mm 7 mm compact package with a side-wall electrical connector has been achieved, which is compatible with the assembly in CFP2 form-factor. We observed the sensitivity at average power of -12.1 dBm and the power penalty of sensitivity due to the crosstalk of less than 0.1 dB.
Takeshi USUI Kiyohide NAKAUCHI Yozo SHOJI Yoshinori KITATSUJI Hidetoshi YOKOTA Nozomu NISHINAGA
This paper proposes a session state migration architecture for flexible server consolidation. One of technical challenges is how to split a session state from a connection and bind the session state to another connection in any servers. A conventional server and client application assumes that a session state is statically bound to a connection once the connection has been established. The proposed architecture reduces the migration latency, compared to an existing study by splitting the session state from the connection. This paper classifies common procedures of session state migration for various services. The session state migration architecture enables service providers to conduct server maintenance at their own convenience, and to conserve energy consumption at servers by consolidating them. A simulation to evaluate server consolidation reveals that the session state migration reduces the number of servers for accommdating users, compared to virtual machine migration. This paper also shows implementation of the session state migration architecture. Experimental results reveal that the impact caused by the proposed architecture on real-time applications is small.
In this letter, we present a low-complexity residual symbol timing offset (STO) estimation scheme in a long term evolution (LTE) downlink system. The proposed scheme is designed to estimate STO without a priori knowledge of cell-specific reference signals, which reduces the arithmetic complexity while maintaining a similar performance to the conventional algorithm.
Eunji PAK Sang-Hoon KIM Jaehyuk HUH Seungryoul MAENG
Although shared caches allow the dynamic allocation of limited cache capacity among cores, traditional LRU replacement policies often cannot prevent negative interference among cores. To address the contention problem in shared caches, cache partitioning and application scheduling techniques have been extensively studied. Partitioning explicitly determines cache capacity for each core to maximize the overall throughput. On the other hand, application scheduling by operating systems groups the least interfering applications for each shared cache, when multiple shared caches exist in systems. Although application scheduling can mitigate the contention problem without any extra hardware support, its effect can be limited for some severe contentions. This paper proposes a low cost solution, based on application scheduling with a simple cache insertion control. Instead of using a full hardware-based cache partitioning mechanism, the proposed technique mostly relies on application scheduling. It selectively uses LRU insertion to the shared caches, which can be added with negligible hardware changes from the current commercial processor designs. For the completeness of cache interference evaluation, this paper examines all possible mixes from a set of applications, instead of using a just few selected mixes. The evaluation shows that the proposed technique can mitigate the cache contention problem effectively, close to the ideal scheduling and partitioning.
We propose a computing method for linear convolution and linear correlation between sequences using discrete cosine transform (DCT). Zero-padding is considered as well as linear convolution using discrete Fourier transform (DFT). Analyzing the circular convolution between symmetrically extended sequences, we derive the condition for zero-padding before and after the sequences. The proposed method can calculate linear convolution for any filter and also calculate linear correlation without reversing one of the input sequences. The computational complexity of the proposed method is lower than that of linear convolution using DFT.
George PARISIS Dirk TROSSEN Hitoshi ASAEDA
Information-centric networking has been touted as an alternative to the current Internet architecture. Our work addresses a crucial part of such a proposal, namely the design of a network node within an information-centric networking architecture. Special attention is given in providing a platform for development and experimentation in an emerging network research area; an area that questions many starting points of the current Internet. In this paper, we describe the service model exposed to applications and provide background on the operation of the platform. For illustration, we present current efforts in deployment and experimentation with demo applications presented, too.
Discrete structures are foundational material for computer science and mathematics, which are related to set theory, symbolic logic, inductive proof, graph theory, combinatorics, probability theory, etc. Many problems solved by computers can be decomposed into discrete structures using simple primitive algebraic operations. It is very important to represent discrete structures compactly and to execute efficiently tasks such as equivalency/validity checking, analysis of models, and optimization. Recently, BDDs (Binary Decision Diagrams) and ZDDs (Zero-suppressed BDDs) have attracted a great deal of attention, because they efficiently represent and manipulate large-scale combinational logic data, which are the basic discrete structures in various fields of application. Although a quarter of a century has passed since Bryant's first idea, there are still a lot of interesting and exciting research topics related to BDD and ZDD. BDD/ZDD is based on in-memory data processing techniques, and it enjoys the advantage of using random access memory. Recent commodity PCs are equipped with gigabytes of main memory, and we can now solve large-scale problems which used to be impossible due to memory shortage. Thus, especially since 2000, the scope of BDD/ZDD methods has increased. This survey paper describes the history of, and recent research activity pertaining to, techniques related to BDD and ZDD.
In this letter, we present a fast image/video super resolution framework using edge and nonlocal constraint. The proposed method has three steps. First, we improve the initial estimation using content-adaptive bilateral filtering to strengthen edge. Second, the high resolution image is estimated by using classical back projection method. Third, we use joint content-adaptive nonlocal means filtering to get the final result, and self-similarity structures are obtained by the low resolution image. Furthermore, content-adaptive filtering and fast self-similarity search strategy can effectively reduce computation complexity. The experimental results show the proposed method has good performance with low complexity and can be used for real-time environment.
Tingting ZHANG Qinyu ZHANG Hongguang XU Hong ZHANG Bo ZHOU
Practical, low complexity time of arrival (TOA) estimation method with high accuracy are attractive in ultra wideband (UWB) ranging and localization. In this paper, a generalized maximum likelihood energy detection (GML-ED) ranging method is proposed and implemented. It offers low complexity and can be applied in various environments. An error model is first introduced for TOA accuracy evaluation, by which the optimal integration interval can be determined. Aiming to suppress the significant error created by the false alarm events, multiple pulses are utilized for accuracy promotion at the cost of extra energy consumption. For this reason, an energy efficiency model is also proposed based on the transmitted pulse number. The performance of the analytical research is evaluated and verified through practical experiments in a typical indoor environment.
Motoharu SASAKI Wataru YAMADA Naoki KITA Takatoshi SUGIYAMA
A new path loss model of interference between mobile terminals in a residential area is proposed. The model uses invertible formulas and considers the effects on path loss characteristics produced by paths having many corners or corners with various angles. Angular profile and height pattern measurements clarify three paths that are dominant in terms of their effect on the accurate modeling of path loss characteristics in residential areas: paths along a road, paths between houses, and over-roof propagation paths. Measurements taken in a residential area to verify the model's validity show that the model is able to predict path loss with greater accuracy than conventional models.
Sha SHEN Weiwei SHEN Yibo FAN Xiaoyang ZENG
This paper describes a unified VLSI architecture which can be applied to various types of transforms used in MPEG-2/4, H.264, VC-1, AVS and the emerging new video coding standard named HEVC (High Efficiency Video Coding). A novel design named configurable butterfly array (CBA) is also proposed to support both the forward transform and the inverse transform in this unified architecture. Hadamard transform or 4/8-point DCT/IDCT are used in traditional video coding standards while 16/32-point DCT/IDCT are newly introduced in HEVC. The proposed architecture can support all these transform types in a unified architecture. Two levels (architecture level and block level) of hardware sharing are adopted in this design. In the architecture level, the forward transform can share the hardware resource with the inverse transform. In the block level, the hardware for smaller size transform can be recursively reused by larger size transform. The multiplications of 4 or 8-point transform are implemented with Multiplierless MCM (Multiple Constant Multiplication). In order to reduce the hardware overhead, the multiplications of 16/32 point DCT are implemented with ICM (input-muxed constant multipliers) instead of MCM or regular multipliers. The proposed design is 51% more area efficient than previous work. To the author's knowledge, this is the first published work to support both forward and inverse 4/8/16/32-point integer transform for HEVC standard in a unified architecture.
Masayuki KAKIDA Yosuke TANIGAWA Hideki TODE
Lately, access loads on servers are increasing due to larger content size and higher request frequency in content distribution networks. Breadcrumbs (BC), an architecture with guidance information for locating a content cache, is designed to reduce the server load and to form content-oriented network autonomously in cooperation with cached contents over IP network. We also proposed Breadcrumbs+ which solves BC's endless routing loop problem. However, Breadcrumbs takes only a passive approach; BC entries are created only when a content is downloaded and only at routers on the download path but not at any other routers. We expect that active and adaptive control of guidance information with simple complexity improves its performance with keeping scalability. In this paper, we propose Active Breadcrumbs which achieves efficient content retrieval and load-balancing through active and adaptive control of guidance information by cache-nodes themselves. In addition, we show the effectiveness of Active Breadcrumbs through the extensive computer simulation.
Zan-Kai CHONG Bok-Min GOI Hiroyuki OHSAKI Bryan Cheng-Kuan NG Hong-Tat EWE
Rateless erasure code is an error correction code that is able to encode a message of k uncoded symbols into an infinite number of coded symbols. One may reconstruct the original message from any k(1+ε) coded symbols, where ε denotes the decoding inefficiency. This paper proposes a hybrid code that combines the stepping code and random code and name it as Stepping-Random (SR) code. The Part I (first k) coded symbols of SR code are generated with stepping code. The rest of the coded symbols are generated with random code and denoted as Part II coded symbols. The numerical results show that the new hybrid code is able to achieve a complete decoding with no extra coded symbol (ε=0) if all the Part I coded symbols are received without loss. However, if only a portion of Part I coded symbols are received, a high probability of complete decoding is still achievable with k+10 coded symbols from the combination of Part I and II. SR code has a decoding complexity of O(k) in the former and O((βk)3) in the latter, where β ∈ R for 0 ≤ β ≤ 1, is the fraction of uncoded symbols that fails to be reconstructed from Part I coded symbols.
Weiqiang LIU Xiaohui CHEN Weidong WANG
This work investigates the cell range expansion (CRE) possible with time-domain multiplexing inter-cell interference coordination (TDM ICIC) in heterogeneous cellular networks (HCN). CRE is proposed to enable a user to connect to a picocell even when it is not the cell with the strongest received power. However, the users in the expanded region suffer severe interference from the macrocells. To alleviate the cross-tier interference, TDM ICIC is proposed to improve the SIR of pico users. In contrast to previous studies on CRE with TDM ICIC, which rely mostly on simulations, we give theoretical analysis results for different types of users in HCN with CRE and TDM ICIC under the Poisson Point Process (PPP) model, especially for the users in the expanded region of picocells. We analyze the outage probability and average ergodic rate based on the connect probability and statistical distance we obtain in advance. Furthermore, we analyze the optimal ratio of almost blank subframes (ABS) and bias factor of picocells in terms of the network fairness, which is useful in the parameter design of a two-tier HCN.
Ryohei NAKADA Yutaka HASEGAWA Shigeki HIROBAYASHI Toshio YOSHIZAWA Tadanobu MISAWA Junya SUZUKI
We propose a sound field control system to control the sound over a wide area within a room by reducing the influence of the reproduction space using power envelope inverse filtering (PEIF). Envelopes of the impulse response within the room have approximately the same shape at all observation points. Therefore, the proposed sound field control system can control with a small number of loudspeakers a wider area by reducing reverberation in the room through envelope processing. We present experimental data demonstrating that the proposed PEIF system can provide better control than a system that uses minimum phase inverse filtering (MPIF), which is conventionally used for reducing reverberation. Improvement was observed across the frequency band, especially above 1 kHz. Additionally, our PEIF system is more effective over the high-frequency range.
We investigate the utilization of vector registers (VRs) on reducing memory references for single instruction multiple data fast Fourier transform calculation. We propose to group the butterfly computations in several consecutive stages to maximize utilization of the available VRs and take the advantage of the symmetries in twiddle factors. All the butterflies sharing identical twiddle factors are clustered and computed together to further improve performance. The relationship between the number of fused stages and the number of available VRs is then examined. Experimental results on different platforms show that the proposed method is effective.
NAND multi-level cell (MLC) flash memories are widely used due to low cost and high capacity. However, the increased number of levels in MLC results in larger interference and errors. The errors in MLC flash memories tend to be directional and limited-magnitude. Many related works focus on asymmetric errors, but bidirectional errors also occur because of the bidirectional interference and the adjustment of the hard-decision reference voltages. To take advantage of the characteristics, we propose t bidirectional (lu,ld) limited-magnitude error correction codes, which can reduce errors more effectively. The proposed code is systematic, and can correct t bidirectional errors with upward and downward magnitude of lu and ld, respectively. The proposed method is advantageous in that the parity size is reduced, and it has lower bit error rate than conventional error correction codes with the same code rate.