In this paper, a high accuracy, high efficiency, and wide current-sensing range current-mode PWM buck converter with on-chip current-sensing technique is presented. The proposed current-sensing circuit uses simple switch technique to achieve high accuracy, high power efficiency, and high line regulation. The test chip is fabricated using TSMC 0.18 µm 1P6M 3.3 V CMOS process. The measurement results show that the buck converter with on-chip current-sensing circuit can operate from 700 kHz to 3 MHz with a supply voltage of 1.5-5 V and the output voltage of 0.5-4.5 V for lithium ion battery applications. The accuracy of the proposed current-sensing circuit is exceeds 89.8% for load current from 50 mA to 500 mA and for temperature from 0C to 100C. The peak power efficiency of the buck converter is up to 95.5%.

This paper proposes a method of improving reception of digital satellite broadcasting in a moving vehicle. According to some studies, the antennas used for mobile reception will be smaller in the next generation and reception will be more difficult because of a fading multipath channel with delays in a low carrier-to-noise ratio. Commonly used approaches to reduce the inter symbol interference caused by a fading multipath channel with delays are pilot sequences and diversity reception. Digital satellite broadcasting, however, does not transmit pilot sequences for channel estimation and it is not possible to install multiple antennas in a vehicle. This paper does not propose any change to the broadcasting standards but discusses how to process currently available digital satellite signals to obtain better results. Our method does not rely on the pilot sequences or diversity reception, but consists of channel estimation and stochastic inference methods. For each task, two methods are proposed. The maximum likelihood estimation and higher order statistics matching methods are proposed for the estimation, and the marginal with the joint probability inference methods are proposed for the stochastic inference. The improvements were confirmed through experiments with numerical simulations and real data. The computational costs are also discussed for future implementation.

Proofs written in algebraic specification languages are called proof scores. The proof score approach to design verification is attractive because it provides a flexible way to prove that designs for systems satisfy properties. Thus far, however, the approach has focused on safety properties. In this paper, we describe a way to verify that designs for systems satisfy liveness properties with the approach. A mutual exclusion protocol using a queue is used as an example. We describe the design verification and explain how it is verified that the protocol satisfies the lockout freedom property.

A new online, unsupervised voice activity detection (VAD) method is proposed. The method is based on a feature derived from high-order statistics (HOS), enhanced by a second metric based on normalized autocorrelation peaks to improve its robustness to non-Gaussian noises. This feature is also oriented for discriminating between close-talk and far-field speech, thus providing a VAD method in the context of human-to-human interaction independent of the energy level. The classification is done by an online variation of the Expectation-Maximization (EM) algorithm, to track and adapt to noise variations in the speech signal. Performance of the proposed method is evaluated on an in-house data and on CENSREC-1-C, a publicly available database used for VAD in the context of automatic speech recognition (ASR). On both test sets, the proposed method outperforms a simple energy-based algorithm and is shown to be more robust against the change in speech sparsity, SNR variability and the noise type.

Threshold Inverter Quantization (TIQ) technique has been gaining its importance in high speed flash A/D converters due to its fast data conversion speed. It eliminates the need of resistor ladders for reference voltages generation which requires substantial power consumption. The key to TIQ comparators design is to generate 2n - 1 different sized TIQ comparators for an n-bit A/D converter. This paper presents a highly efficient TIQ comparator design methodology based on an analytical model as well as SPICE simulation experimental model. One can find any sets of TIQ comparators efficiently using the proposed method. A 6-bit TIQ A/D converter has been designed in a 0.18 µm standard CMOS technology using the proposed method, and compared to the previous measured results in order to verify the proposed methodology.

This letter analyzes the outage probability of limited feedback beamforming systems with receive antenna selection. Tight analytical closed-form expressions of outage performance are derived for both cases, with and without spatial fading correlation, which allow for evaluation of the performance as a function of the codebook size, the level of fading correlation, and the number of transmit and receive antennas. Simulation results are also provided to verify the analysis.

In this paper, based on interleaved technique, we present a new method of constructing zero correlation zone (ZCZ) sequence sets. For any perfect sequence of length m(2k+1) with m > 2, k ≥ 0 and an arbitrary Hadamard matrix of order T > 2, the proposed construction can generate new optimal ZCZ sequence sets in which all the sequences are cyclically distinct.

In this letter, we derive a very accurate closed-form approximate formula for the average achievable rate of stacked orthogonal space-time block code (OSTBC) in Rayleigh fading channels. Some simulations are performed to demonstrate that the derived formula shows better agreement with Monte-Carlo simulation results than the existing closed-form approximate expressions.

With the development of digital TV system, how to display the NTSC signal in digital TV system is a problem. De-interlacing is an algorithm to solve it. In previous papers, using motion compensation (MC) method for de-interlacing needs lots of computation complexity and it is not easy to implement in hardware. In this paper, a content adaptive de-interlacing algorithm is proposed. Our algorithm is based on the motion adaptive (MA) method which combines the advantages of intra-field and inter-field method. We propose a block type decision mechanism to predict the video content instead of a blind processing with MC method throughout the entire frame. Additionally, in intra-field method, we propose the edge-base adaptive weight average (EAWA) method to achieve a better performance and smooth the edge and stripe. In order to demonstrate our algorithm, we implement the de-interlacing system on the DSP platform with thorough complexity analysis. Compared to MC method, we not only achieve higher video quality in objective and subjective view, but also consume lower computation power. From the profiling on CPU run-time analysis, the proposed algorithm is only one-fifth of MC method. At the DSP demonstration board, the saving ratio is about 54% to 96%.

In situ observation of electrochemical activity and time dependent characteristics of cytochrome c (cyt c) was carried out in 0.01 M phosphate buffered saline (PBS, pH 7.4) containing 20 µM cyt c solutions at bare indium-tin-oxide (ITO) electrodes by using a cyclic voltammetry (CV) and a slab optical waveguide (SOWG) spectroscopy. The bare ITO electrodes could retain the electrochemical activity of cyt c in the PBS solutions, indicating the great advantage of using ITO electrodes against other electrode materials, such as gold (Au). The CV curves and simultaneously observed the time-resolved SOWG absorption spectra in the consecutive cycles implied that the cyt c molecules could retain its own electrochemical function for a long time.

An adaptive per-survivor processing maximum likelihood sequence estimation (PSP-MLSE) using state-space based recursive least-squares (RLS) is proposed for rapidly time varying multi-path fading channels. Unlike PSP-MLSE using Kalman filtering, it does not require the knowledge of model statistics, and with an aid of state-space modeling, it has a robust performance to the fade rate, compared to PSP-MLSE using conventional RLS.

Task preemption is a critical mechanism for building an effective multi-tasking environment on dynamically reconfigurable processors. When a task is preempted, its necessary state information must be correctly preserved in order for the task to be resumed later. Not only do coarse-grained Dynamically Reconfigurable Processing Array (DRPAs) devices have different architectures using a variety of development tools, but the great amount of state data of hardware tasks executing on such devices are usually distributed on many different storage elements. To address these difficulties, this paper aims at studying a general method for capturing the state data of hardware tasks targeting coarse-grained DRPAs. Based on resource usage, algorithms for identifying preemption points and inserting preemption states subject to user-specified preemption latency are proposed. Moreover, a modification to automatically incorporate proposed steps into the system design flow is also discussed. The performance degradation caused by additional preemption states is minimized by allowing preemption only at predefined points where demanded resources are small. The evaluation result using a model based on NEC Electronics' DRP-1 shows that the proposed method can produce preemption points satisfying a given preemption latency with reasonable hardware overhead (from 6% to 15%).

A fast time-domain simulation technique of plane circuits via two-layer Cellular Neural Network (CNN)-based modeling, which is necessary for power/signal integrity evaluation in VLSIs, printed circuit boards, and packages, is presented. Using the new notation expressed by the two-layer CNN, 1,553 times faster simulation is achieved, compared with Berkeley SPICE (ngspice). In CNN community, CNNs are generally simulated by explicit numerical integration such as the forward Euler and Runge-Kutta methods. However, since the two-layer CNN is a stiff circuit, we cannot analyze it by using an explicit numerical integration method. Hence, to analyze the two-layer CNN and reduce the computational cost, the leapfrog method is introduced. This procedure would open an application of CNN to electronic design automation area.

We define a new quaternary cyclotomic sequences of length 2p, where p is an odd prime. We compute the autocorrelation of these sequences. In terms of magnitude, these sequences have the autocorrelations with at most 4 values.

Intra coding in H.264/AVC has significantly enhanced video compression efficiency. However, computation complexity increases by the rate-distortion (RD) based mode decision. This paper proposes a novel fast mode decision algorithm in H.264/AVC intra prediction and its VLSI architecture. A novel edge-detection pattern is proposed and both edge-detection technique and spatial mode prediction technique are combined together to reduce the number of intra 44 candidate modes from 9 to an average of 2.50. VLSI architecture of intra mode decision module is designed with TSMC 0.18 µm CMOS technology. The maximum frequency of 285 MHz is achieved and 13.1k NAND gates are required. High frequency, efficient processing cycle reduction and small area make this design to be an excellent accelerator for HDTV 1080p@30 fps real time encoder.

This paper presents a high-level synthesis approach to minimize the total power consumption in behavioral synthesis under time and area constraints. The proposed method has two stages, functional unit (FU) energy optimization and interconnect energy optimization. In the first stage, active and inactive energies of the FUs are optimized using a multiple supply and threshold voltage scheme. Genetic algorithm (GA) based simultaneous assignment of supply and threshold voltages and module selection is proposed. The proposed GA based searching method can be used in large size problems to find a near-optimal solution in a reasonable time. In the second stage, interconnects are simplified by increasing their sharing. This is done by exploiting similar data transfer patterns among FUs. The proposed method is evaluated for several benchmarks under 90 nm CMOS technology. The experimental results show that more than 40% of energy savings can be achieved by our proposed method.

In this paper, an alternative approach is presented, to design equalizers (or matching networks) with commensurate (or equal length) transmission lines. The new method automatically yields the matching network topology with characteristic impedances of the commensurate lines. In the implementation process of the new technique first, the driving point impedance data of the matching network is generated by tracing a pre-selected transducer power gain shape, without optimization. Then, it is modelled as a realizable bounded-real input reflection coefficient in Richard domain, which in turn yields the desired equalizer topology with line characteristic impedances. This process results in an excellent initial design for the commercially available computer aided design (CAD) packages to generate final circuit layout for fabrication. An example is given to illustrate the utilization of the new method. It is expected that the proposed design technique is employed as a front-end, to commercially available computer aided design (CAD) packages which generate the actual equalizer circuit layout with physical dimensions for mass production.

We fabricated both thin film transistors (TFTs) and diodes using zinc oxide (ZnO) and pentacene, and investigated their basic characteristics. We found that field-effect mobility is influenced by the interface state between the semiconductor and dielectric layers. Furthermore, the complementary metal oxide semiconductor (CMOS) inverter using a p-channel pentacene field-effect transistor (FET) and an n-channel ZnO FET showed a relatively high voltage gain (8-12) by optimizing the device structure. The hybrid complementary inverters described here are expected for application in flexible displays, radio frequency identification cards (RFID) tags, and others.

Efficient use of information technology (IT) is considered a major determinant of an end-user's business performance and an enterprise's competitiveness. A 16-item tool that can efficiently measure end-user information competency is presented with the measures. The validity and reliability of the tool is confirmed, and the tool's theoretical and practical applications are discussed.

This letter presents a novel approach for traffic light detection in a video frame captured by an in-vehicle camera. The algorithm consists of rotated principal component analysis (RPCA), modified amplitude thresholding with respect to the histograms of the PC planes and final filtering with a neural network. The proposed algorithm achieves an average detection rate of 96% and is very robust to variations in the image quality.