Physical defects that are not covered by stuck-at fault or bridging fault model are increasing in LSI circuits designed and manufactured in modern Deep Sub-Micron (DSM) technologies. Therefore, it is necessary to target non-stuck-at and non-bridging faults. A stuck-open is one such fault model that captures transistor level defects. This paper presents two methods for maximizing stuck-open fault coverage using stuck-at test vectors. In this paper we assume that a test set to detect stuck-at faults is given and we consider two formulations for maximizing stuck-open coverage using the given test set as follows. The first problem is to form a test sequence by using each test vector multiple times, if needed, as long as the stuck-open coverage is increased. In this case the target is to make the resultant test sequence as short as possible under the constraint that the maximum stuck-open coverage is achieved using the given test set. The second problem is to form a test sequence by using each test vector exactly once only. Thus in this case the length of the test sequence is maintained as the number of given test vectors. In both formulations the stuck-at fault coverage does not change. The effectiveness of the proposed methods is established by experimental results for benchmark circuits.

In this paper, a high accuracy, high efficiency, and wide current-sensing range current-mode PWM buck converter with on-chip current-sensing technique is presented. The proposed current-sensing circuit uses simple switch technique to achieve high accuracy, high power efficiency, and high line regulation. The test chip is fabricated using TSMC 0.18 µm 1P6M 3.3 V CMOS process. The measurement results show that the buck converter with on-chip current-sensing circuit can operate from 700 kHz to 3 MHz with a supply voltage of 1.5-5 V and the output voltage of 0.5-4.5 V for lithium ion battery applications. The accuracy of the proposed current-sensing circuit is exceeds 89.8% for load current from 50 mA to 500 mA and for temperature from 0C to 100C. The peak power efficiency of the buck converter is up to 95.5%.

Leakage power consumption of logic elements has become a serious problem, especially in the sub-100-nanometer process. In this paper, a novel power gating approach by using the controlling value of logic elements is proposed. In the proposed method, sleep signals of the power-gated blocks are extracted completely from the original circuits without any extra logic element. A basic algorithm and a probability-based heuristic algorithm have been developed to implement the basic idea. The steady maximum delay constraint has also been introduced to handle the delay issues. Experiments on the ISCAS'85 benchmarks show that averagely 15-36% of logic elements could be power gated at a time for random input patterns, and 3-31% of elements could be stopped under the steady maximum delay constraints. We also show a power optimization method for AND/OR tree circuits, in which more than 80% of gates can be power-gated.

It has been known that testing of reversible circuits is relatively easier than conventional irreversible circuits in the sense that few test vectors are needed to cover all stuck-at faults. This paper shows, however, that it is NP-hard to generate a minimum complete test set for stuck-at faults on the wires of a reversible circuit using a polynomial time reduction from 3SAT to the problem. We also show non-trivial lower bounds for the size of a minimum complete test set.

A new formulation of equal-length asymmetric parallel coupled line (APCLs) having zero at z=-1 (θ = π) is employed to study band-stop filters. Such representations offer additional flexibility in the design of filter circuits through two extra variables. An optimization algorithm is used to tune the characteristic impedances of APCLs so that the transfer function of the signal line is close to the system function of an ideal prototype filter. Two band-stop filters are realized in the form of microstrip lines and their frequency responses are measured to validate this new formulation.

We propose Adaptive Resource Allocation for the Partial Block MC-CDMA (ARA-PB/MC-CDMA) system. The ARA-PB/MC-CDMA system aims to improve total throughput performance and frequency efficiency across various channel conditions. It adaptively changes the number of blocks to improve the throughput performance and frequency efficiency according to the Signal to Interference Ratio (SIR). Therefore, the proposed system supports various Quality of Service (QoS) requirements for various SIR values.

The characteristics of violet-sensitive organic photodetectors (OPDs) utilizing polyalkylfluorene and triplet materials have been studied as a host and a dopant material, respectively. For the photo absorption layer, poly(9,9-dioctylfluorene) [PFO] and a phosphorescent iridium complex (Iridium (III) bis(2-(4,6-difluorophenyl)pyridinato-N,C2) [FIrpic] or Iridium (III) bis(2-(2'-benzothienyl)pyridinato-N,C3')(acetyl-acetonate) [(btp)2Ir(acac)]) were used as a host and a dopant material, respectively. PFO: (btp)2Ir(acac) device showed less photocurrent than PFO device because (btp)2Ir(acac) enhances recombination of the photo generated carriers in the photo absorption layer. On the other hand, PFO : FIrpic device showed larger photocurrent than PFO device due to triplet energy transfer from FIrpic to PFO. A cutoff frequency of 20 MHz was observed using a sinusoidal modulated violet laser light illumination under the reverse bias of 8 V.

We introduce the Rank M-type L (RM L)-filter to remove impulsive and speckle noise from corrupted images by means of use of DSP TMS320C6701.

The weakness of implementation for LDPC encoder is that conventional binary Matrix Vector Multiplier has many clock cycles which lead to limited throughput. In this letter in order to construct efficient architecture, we target on IEEE 802.16e LDPC encoders. Over the standard H matrices with Circulant Permutation Matrices, we propose semi-parallel architecture by using cyclic right shift registers and exclusive-OR instead of complex Matrix Vector Multipliers. Proposed efficient encoder for IEEE 802.16e LDPC satisfies compact size and high throughput.

In the context of multiple constant multiplication (MCM) design, we propose a novel common sub-expression elimination (CSE) algorithm that models the optimal synthesis of coefficients into a 0-1 mixed-integer linear programming (MILP) problem with a user-defined generic logic depth constraint. We also propose an efficient solution space, which combines all minimal signed digit (MSD) representations and the shifted sum (difference) of coefficients. In the examples we demonstrate, the combination of the proposed algorithm and solution space gives a better solution comparing to existing algorithms.

This paper proposes a closed-form eye-diagram model for on-chip distortionless transmission lines with intentionally inserted shunt conductance. We derive expressions of eye-opening both in voltage and time, by assuming a piece-wise linear waveform model. The model is experimentally verified with various length, shunt conductance and resistive termination. We also apply the proposed model to design space exploration, and demonstrate that the proposed model helps estimate the optimal shunt conductance and resistive termination according to required signaling length and throughput.

Abdalla et al. proposed a gateway-oriented password-based authenticated key exchange (GPAKE) protocol among a client, a gateway, and an authentication server, where a password is only shared between the client and the authentication server. The goal of their scheme is to securely establish a session key between the client and the gateway by the help of the authentication server without revealing any information on the password to the gateway. Recently, Byun et al. showed that Abdalla et al.'s GPAKE is insecure against undetectable on-line password guessing attacks. They also proposed a modified version to overcome the attacks. In this letter, we point out that Byun et al.'s modified GPAKE protocol is still insecure against the same attacks. We then make a suggestion for improvement.

This letter proposes an identity-based authenticated key agreement protocol. Different from available comparable ones, the new protocol realizes implicit authentication without bilinear pairings which makes it more efficient. The security of proposed protocol can be reduced to the standard Computational Diffie-Hellman problem. Two variants of the protocol are also given, with one achieving the security-efficiency trade-off and the other providing authenticated key agreement between users of different domains.

In this letter, a two channel frequency domain speech enhancement algorithm is proposed. The algorithm is designed to achieve better overall performance with relatively small array size. An improved version of adaptive null-forming is used, in which noise cancelation is implemented in auditory subbands. And an OM-LSA based postfiltering stage further purifies the output. The algorithm also features interaction between the array processing and the postfilter to make the filter adaptation more robust. This approach achieves considerable improvement on signal-to-noise ratio (SNR) and subjective quality of the desired speech. Experiments confirm the effectiveness of the proposed system.

As the semiconductor feature size decreases, the crosstalk due to the capacitive coupling of interconnects influences signal propagation delay more seriously. Moreover, the increase of the operating frequency further emphasizes the necessity of more accurate timing analysis. In this paper, we propose new gate models to calculate gate output waveforms under crosstalk effects, which can be used for gate-level delay estimation. We classify the operation modes of metal-oxide-semiconductor (MOS) devices of a gate into 3 regions, and then develop simple linear models for each region. In addition, we present a non-iterative gate modeling method that is more efficient than previous iterative methods. In the experiments, the proposed method exhibits a maximum error of 10.70% and an average error of 2.63% when it computes the 50% delays of two or three complementary MOS (CMOS) inverters driving parallel wires. In comparison, the existing method has a maximum error of 25.94% and an average error of 3.62% under these conditions.

In approximately synchronous CDMA (AS-CDMA) systems, zero correlation zone (ZCZ) sequences are known as the sequences to eliminate co-channel and multi-path interferences. Therefore, numerous constructions of zero correlation zone (ZCZ) sequences have been introduced e.g. based on perfect sequences and complete complementary codes etc. However, the previous construction method which based on complete complementary code is lacking for merit figures when none of whose elements are zero. In this paper, a new construction method of ZCZ sequences based on complete complementary codes is proposed. By proposed method, non zero elements ZCZ sequences whose merit figure is greater than 1/2 are constructable.

In this paper we introduce new M-ary sequences of length pq, called generalized M-ary related-prime sequences, where p and q are distinct odd primes, and M is a common divisor of p-1 and q-1. We show that their out-of-phase autocorrelation values are upper bounded by the maximum between q-p+1 and 5. We also construct a family of generalized M-ary related-prime sequences and show that the maximum correlation of the proposed sequence family is upper bounded by p+q-1.

Threshold Inverter Quantization (TIQ) technique has been gaining its importance in high speed flash A/D converters due to its fast data conversion speed. It eliminates the need of resistor ladders for reference voltages generation which requires substantial power consumption. The key to TIQ comparators design is to generate 2n - 1 different sized TIQ comparators for an n-bit A/D converter. This paper presents a highly efficient TIQ comparator design methodology based on an analytical model as well as SPICE simulation experimental model. One can find any sets of TIQ comparators efficiently using the proposed method. A 6-bit TIQ A/D converter has been designed in a 0.18 µm standard CMOS technology using the proposed method, and compared to the previous measured results in order to verify the proposed methodology.

This paper presents the analysis of in-band interference caused by pulse-based ultra-wideband (UWB) systems. The analysis contains both plain Impulse Radio UWB (IR-UWB) and Transmitted Reference UWB (TR-UWB) systems as a source of interference. The supposed victim is a narrowband BPSK system with a band-pass filter. The effect of pulse-based UWB systems is analyzed in terms of bit error rate. The analysis is given in terms of the specific combinations of pulse repetition frequency and center frequency of the narrowband bandpass filter. In those situations, the UWB interference cannot be modeled as a Gaussian noise. It also manifests situations in which the victim is under the severest or the slightest interference from TR-UWB. According to its result, the analysis is validated via simulation.

In block transmission systems, blind channel shortening methods are known to be effective to reduce the influence of interblock interference which degrades the performance when the length of a channel impulse response is extremely long. Conventional methods assume that the transmitted signal is uncorrelated; however, this assumption is invalid in practical systems such as OFDM with null carriers and MC-CDMA. In this paper, we consider blind channel shortening methods for block transmissions when the transmitted samples within a block are correlated. First, the channel shortening ability of a conventional method is clarified. Next, a new method which exploits the fact that the transmitted samples in different blocks are uncorrelated is introduced. It is shown that the proposed method can shorten the channel properly under certain conditions. Finally, simulation results of OFDM and MC-CDMA systems are shown to verify the effectiveness of the proposed method compared with a conventional one.