In this paper, we introduce a high-speed and low-power Phase-Frequency Detector (PFD) that is designed using a modified TSPC (True Single-Phase Clock) positive edge triggered D flip-flop . The proposed PFD has a simple structure with using only 19 transistors. The operation range of this PFD is over 1.4 GHz without using additional prescaler circuits. Furthermore, the PFD has a dead zone less than 0.01ns in the phase characteristics and has low phase sensitivity errors. The phase and frequency error detection range is not limited as in the case of the pt-type and nc-type PFDs. Also, the PFD is independent of the duty cycle of input signals. Also, a new charge-pump circuit is presented that is based on a charge-amplifier. A stand-by current of the proposed charge-pump circuit enhances the speed of charge-pump and removes the charge sharing which causes a phase noise in the charge pump PLL. Furthermore, the effect of clock feedthrough is reduced by separating the output stage from up and down signal. The simulation results base on a third order PLL are presented to verify the lock in process with the proposed PFD and charge pump circuits. The proposed PFD and charge-pump circuits are designed using 0.8 µm CMOS technology with 5 V supply voltage.

This paper describes a new millimeter-wave hybrid integrated circuit (HIC) technology which applies a thin film multi-layered dielectric substrate and flip-chip bonding technology employing stud bump bonding (SBB). We have previously proposed and demonstrated a novel HIC structure, named millimeter-wave flip-chip IC, (MFIC), applying an excellent dielectric material of benzocyclobutene (BCB) thin film and flip-chip bonding. In this paper, an advanced thin film multi-layer process using non-photosensitive BCB was newly developed. Characteristics of the transmission lines and the built-in MIM capacitor within the multi-layered structure were discussed. Furthermore, stud bump bonding was newly adapted to the MFIC as a flip-chip method, and the millimeter-wave characteristics of the bumps were examined. Using these technologies, we demonstrate characteristics of a miniaturized 25 GHz down converter MFIC. Our newly proposed HIC structure enabled us to bring down chip size to less than 1/3 of our conventional structure. Finally, we discuss future possibilities for high performance multi-chip-modules (MCMs) using SBB technology as a further improved HIC for compact millimeter-wave radio equipment.

The flip-chip structure for millimeter-wave MMICs has been investigated to obtain high performance and high reliability. In our approach, an air gap between the MMIC and the alumina substrate was determined so as not to change electrical characteristics from those of the unflipped MMIC. We calculated the proximity effect between the MMIC and the substrate by using 3D-electromagnetic simulator, and found that the air gap should be controlled to be greater than 20 µm. Since the discontinuity of transmission lines at bump interconnects is not negligible above 60 GHz, we constructed the LCR-equivalent circuit for the bump interconnect and confirmed its validity by comparing measurement with calculation. Based on these investigations, the 60- and 76-GHz-band CPW three-stage low noise amplifiers were successfully mounted on the alumina substrate using a thermal compression bonding process. The gain of the flipped 60- and 76-GHz-band MMICs are greater than 18 dB at around 60 GHz and 17 dB at around 76 GHz, respectively. The noise figures are 3.6 dB and 3.9 dB, respectively. The gain and noise performances showed little degradation compared to those of the unflipped MMICs when appropriate bonding conditions are given. We confirmed that the flip-chip structure has high reliability under a thermal cycle test. From these results, flip-chip technology is promising for millimeter-wave applications.

Miniaturized opto and microwave receiver module using DCCPWs (Double Conductor Coplanar Waveguides) have been developed for active phased array antennas. The module comprised by a microstrip-to-slot transition, two chips of low-noise MMIC amplifiers, and a laser diode module is fabricated on an ultra-thin package with 10301.5 mm3 in size and 2 g in weight to achieve an ultra-thin structure of active phased array antenna panels. The ultra-thin structure is attributed to the design of low-noise MMIC amplifiers using DCCPWs and laser diode modules using silicon V-groove technology and fiber alignment method.

In this paper, an effective method of system modeling and dynamic scheduling to improve operation and control for the Back-End process of semiconductor manufacturing is developed by using Colored Timed Petri-Nets (CTPNs). The simulator of a CTPNs model was utilized to generate a new heuristic scheduling method with genetic algorithm(GA) which enables us to obtain the optimal values of the weighted delay time and standard deviation of lead time.

In a real-time system, it is required to reduce the response time to an interrupt signal, as well as the execution time of a Real-Time Operating System (RTOS). In order to satisfy this requirement, we have proposed a method of implementing some of the functionalities of an RTOS using hardware. Based on this idea, we have implemented a VLSI chip, called STRON (silicon TRON: The Realtime Operating system Nucleus), to enhance the performance of an RTOS, where the STRON chip works as a peripheral unit of any MPU. In this paper we describe the hardware architecture of the STRON chip and the performance evaluation results of the RTOS using the STRON chip. The following results were obtained. (1) The STRON chip is implemented in only about 10,000 gates when the number of each object (task, event flag, semaphore, and interrupt) is 7. (2) The task scheduler can execute within 8 clocks in a fixed period using the hardware algorithm when the number of tasks is 7. (3) Most of the basic µITRON system calls using the STRON chip can be executed in a fixed period of a few microseconds. (4) The execution time of a system call, measured by a multitask application program model, can be reduced to about one-fifth that in the case of the conventional software RTOS. (5) The total performance, including context switching, is about 2.2 times faster than that of the software RTOS. We conclude that the execution time of the part of the system call implemented by the STRON chip can almost be ignored, but the part of the interface software and context switching related to the architecture of a MPU strongly influence the total performance of an RTOS.

Weighted summation (W-SUM) operation of multi-input signals plays an important role in signal processing, image compression and communication systems. Conventional digital LSI implementation for the massive high-speed W-SUM operations usually consumes a lot of power, and the power dissipation linearly increases with the operational frequencies. Analog or digital-analog mixed technology may provide a solution to this problem, but the large scale integration for analog circuits especially for digital-analog mixed circuits faces some difficulties in terms of circuit design, mixed-simulation, physical layout and anti-noises. To practically integrate large scale analog or digital-analog mixed circuits, the simplicity of the analog circuits are usually required. In this paper, we present a solution to realize the parallel W-SUM operations of multi-input analog signals based on our developed digital-controlled analog operational circuits. The major features of the proposed circuits include the simplicity in the circuitry architecture and the advantage in the dissipation power, which make it easy to be designed and to be integrated in large scale. To improve the design efficiency, a Top-Down design approach for mixed LSI implementation is proposed. The proposed W-SUM circuits and the Top-Down design approach have been practically used in the LSI implementation for a series of programmable finite impulse response (FIR) filters and matched filters applied in adaptive signal processing and the mobile communication systems based on the wideband code division multiple access (W-CDMA) technology.

A high gain AlGaAs/InGaAs HJFET has been developed with Embedded gate technology for Microwave and Millimeter-wave IC's using EB lithography (EMMIE). EMMIE consists of a direct SiO2 opening by two-step dry-etching with a chemically amplified resist mask. 0.14 µm gate patterns delineated on 4-inch wafers exhibited a small deviation of 10 nm in Lg and a Vth standard deviation of 55 mV. The optimum distance between the top of the gate and the recess surface (hg) was determined using a two-dimensional device simulator in order to investigate the effect of fringing gate to drain capacitance on the RF gain performance. The fabricated one-stage HJFET MMIC amplifier exhibited extremely high gain performance of 12.4 dB at 76 GHz.

Reducing code size is crucial in embedded systems as well as in high-performance systems to overcome the communication bottleneck between memory and CPU, especially with VLIW (Very Long Instruction Word) processors that require a high-bandwidth instruction prefetching. This paper presents a new approach for dictionary-based code compression in VLIW processor-based systems using isomorphism among instruction words. After we divide instruction words into two groups, one for opcode group and the other for operand group, the proposed compression algorithm is applied to each group for maximal code compression. Frequently-used instruction words are extracted from the original code to be mapped into two dictionaries, an opcode dictionary and an operand dictionary. According to the SPEC95 benchmarks, the proposed technique has achieved an average code compression ratio of 63%, 69%, and 71% in a 4-issue, 8-issue, and 12-issue VLIW architecture, respectively.

Simple approximate formulas are obtained for the mutual impedance and admittance by using a product of radiation patterns of antennas. The formulas come from a stationary expression of the reaction integral between two antennas where far-field approximations are employed. The theory deals with antennas in free space as well as under the presence of a wedge. Two applications are given for microstrip antennas with experimental verifications.

Millimeter-wave systems increasingly are entering into commercial systems, both for communication and sensors for traffic or industrial applications. In many cases, circuit technology of the involved front-ends includes monolithic and hybrid integrated circuits and even waveguide components like filters or antenna feeds. In addition to the standard technical and environmental requirements, these front-ends have to be fabricated in large quantities at very low cost. After a short review of the problems and some general interconnect and packaging techniques for mm-wave front-ends, achievements of a research program will be presented at the example of components for a 28 GHz communication front-end. Emphasis is put on a novel feed-through structure using multilayer carrier substrates for mm-wave circuits, some advances in electromagnetic field coupling for interconnects to mm-wave MMICs, and the realization of packages including waveguide components by plastic injection molding and electroplating. Results of filters and a diplexer produced in this way are shown, including pretuning of the filters to compensate the shrinking of the plastic parts during cooling.

A new feature parameter based on a discrete wavelet transform is proposed for word boundary detection of isolated utterances. The sum of standard deviation of wavelet coefficients in the third coarse and weighted first detailed scale is defined as a new feature parameter for endpoint detection. Experimental results demonstrate the superiority of the proposed feature to the conventional ones in capturing word boundaries even in noisy speech.

In this paper, a novel application specific power optimization technique utilizing small instruction ROM which is placed between an instruction cache or a main program memory and CPU core is proposed. Our optimization technique targets embedded systems which assume the following: (i) instruction memories are organized by two on-chip memories, a main program memory and a subprogram memory, (ii) these two memories can be independently powered-up or powered-down by a special instruction of a core processor, and (iii) a compiler optimizes an allocation of object code into these two memories so as to minimize average of read energy consumption. In many application programs, only a few basic blocks are frequently executed. Therefore, allocating these frequently executed basic blocks into low power subprogram memory leads significant energy reduction. Our experiments with actual ROM (Read Only Memory) modules created with 0.5 µm CMOS process technology, and MPEG2 codec program demonstrate significant energy reductions up to more than 50% at best case over the previous approach that applies only divided bit and word lines structure.

In general, when many functions and services are added to a system, verification and validation become difficult. In design and development in telecommunication services, conflicts that arise from combined telecommunication services have been discussed from various viewpoints. However, correctly and efficiently detecting all conflicts is still not possible and the resolution of conflicts primarily depends on expert designers, who are finding that these problems are beyond their ability. Thus, the burden on the designer must also be alleviated at the design stage. Service interference, which is discussed in this paper, is a kind of conflict. A problem of service interference is that during service, other services interfere with the ongoing service behavior. That is to say, a strange state arises, or an input event doesn't work, or a strange transition occurs, etc. The detection of service interference by only comparing states among services is not enough since the state transition must be considered in the service interference. This paper proposes how to automatically detect the service interference with a rule-based system and an extended adjacency matrix. The proposed method uses and combines features of both the adjacency matrix and rule-based system. The method first generates the extended adjacency matrix by the rule application, then extracts sequences of the state, the event, and the rule applications, and then detects the service interference with the extracted sequences.

In this paper, we describe the PS3 load distribution scheme. A target service is a transaction service consisting of multiple processes that communicate with each other. A target system consists of workstations connected by a LAN. PS3 determines the process allocation by estimating response times and throughputs. It allows us to set an upper limit of a response time, and to set lower and upper limits for the throughput of each service. PS3 tries to find a process allocation that provides the minimum response time under conditions set by the user in advance. We measured the response times and throughputs and compared the values with the estimated ones. The results show that PS3 provides an appropriate process allocation, and that calculated results agree well with the measured ones.

Inter-vehicle communication has aroused much interest because of its goal of reducing traffic accidents. In a non-platooning situation, where vehicles travel freely, multiple hop (MH) inter-vehicle communication has not yet been examined. In this paper a simple MH broadcast protocol is proposed, and shown to be effective. The effect of several parameters important to a MH network, such as maximum number of hops and data rate, are investigated. Multiple hop is shown to be superior to the conventional single hop (SH) system using non-platoon inter-vehicle communication.

Systolic array implementations of modified Gaussian eliminations for the decoding of an (n, n-2t) RS code, including the Hong-Vetterli algorithm and the FIA proposed by Feng and Tzeng, are designed in this paper. These modified Gaussian eliminations are more easily understanding than the classical Berlekamp-Massey algorithm and, in addition, are efficient to decode RS codes for small e or e <

One of the limitation factors on the achievable distance for long-haul nonlinear Return-to-Zero (RZ)-Gaussian pulse transmission on optical fiber links is timing jitter. Although it is well known that the dispersion management technique is very effective to reduce the timing jitter, comparisons among some dispersion management methods based on the timing jitter reduction have not been reported yet. In this paper, timing jitter reduction by some dispersion management methods in nonlinear RZ-Gaussian pulse transmission systems are discussed. Moreover, we will report that the amount of timing jitter at the receiver side drastically changes depending on the configuration of dispersion managed optical fiber transmission line.

Multimedia communications over mobile networks suffer from fluctuating channel degradation. Conventional error handling schemes consist of the first stage error correction decoding in wireless interface and the second stage error correction decoding in multimedia demultiplexer, where the second stage decoding result is not used to improve the first stage decoding performance. To meet the requirements of more powerful error protection, we propose iterative soft-input/soft-output error correction decoding in multimedia communications, where the likelihood output generated by the error correction decoding in multimedia demultiplexer is fed back to the decoding in wireless interface and the decoding procedure is iterated. The performances were evaluated by MPEG-4 video transmission simulation over mobile channels.

The novel method for automatic pattern recognition is presented. This method is based on Segment and Neighbors Matching algorithm which can be applied for recognizing of distinct well-known alphabets, complex glyphs, and Arabic scripts. In this work some different reported methods have been evaluated on Latin, Chinese characters, and Mayan glyphs with the principle objective to select those with the highest processing speed and recognition grade. The case of Mayan glyphs is more complicated due to a big number of elements in any glyph, significant variations of their representation or writing, there are more than 800 classes of glyphs and many of them with similar components and locations. The proposed method of Segments and Neighbors Matching has been developed on base of fuzzy sets and membership functions concept which can be defined during manipulation with the glyph skeleton. Next, levels of matching with predefined patterns are used for segments recognition and interpretation of whole glyph. The main characteristics of recognizing process are matching level, time of processing, grade of membership, and efficiency of interpretation that is important for incomplete glyphs images. On base of proposed method the special software RECGLYM (Mayan Glyphs Recognition) has been designed for the SUN and Intel PC computers platforms. The advantages of the proposed Segments and Neighbors Matching method are quick image processing and high probability of complex glyphs interpretation. The proposed method could be used in different applications, for example, for selection and diagnose of certain anomalies by means of processing of X-ray images or for Internet navigation and searching information searching by image similarity analysis with predefined pattern.