A procedure for quickly developing highly integrated multifunctional MMICs by using the three-dimensional masterslice MMIC technology has been developed. The structures and advanced features of this technology, such as miniature transmission lines, a broadside coupler, and miniature function block circuits, enable multifunctional MMICs to be quickly and easily developed. These unique features and basic concept of the masterslice technology are discussed and reviewed to examine the advantages of this technology. As an example of quick MMIC development, an amplifier, a mixer, and a down-converter are fabricated on a newly designed master array.

A description for high-speed communication networks for the 21st century is roughly sketched, and the technical development trends in high-frequency and high-speed devices are briefly forecasted. Four examples of devices under development are reported: 76-GHz flip-chip MMIC's for car-radar systems, a cost-effective RF module for millimeter-wave wireless systems, a 10-Gbps demultiplexer for optical fiber communication systems, and a GaAs microwave signal processor for active phased-array systems. Considering as technological trends evolve further, this paper also introduces the software radio concept and the fusion of wireless and optical technologies for cost-effective wireless communication equipment and end-user services.

Weighted summation (W-SUM) operation of multi-input signals plays an important role in signal processing, image compression and communication systems. Conventional digital LSI implementation for the massive high-speed W-SUM operations usually consumes a lot of power, and the power dissipation linearly increases with the operational frequencies. Analog or digital-analog mixed technology may provide a solution to this problem, but the large scale integration for analog circuits especially for digital-analog mixed circuits faces some difficulties in terms of circuit design, mixed-simulation, physical layout and anti-noises. To practically integrate large scale analog or digital-analog mixed circuits, the simplicity of the analog circuits are usually required. In this paper, we present a solution to realize the parallel W-SUM operations of multi-input analog signals based on our developed digital-controlled analog operational circuits. The major features of the proposed circuits include the simplicity in the circuitry architecture and the advantage in the dissipation power, which make it easy to be designed and to be integrated in large scale. To improve the design efficiency, a Top-Down design approach for mixed LSI implementation is proposed. The proposed W-SUM circuits and the Top-Down design approach have been practically used in the LSI implementation for a series of programmable finite impulse response (FIR) filters and matched filters applied in adaptive signal processing and the mobile communication systems based on the wideband code division multiple access (W-CDMA) technology.

This paper presents an algorithm for the scan-chain optimization problem in multiple-scan design methodology. The proposed algorithm, which consists of four phases, first determines pairs of scan-in and scan-out pins (Phase 1), and then assigns flip-flops to scan-paths by using a graph theoretical method (Phase 2). Next the algorithm decides connection-order of flip-flops in each scan-path by using TSP (Traveling Salesman Problem) heuristics (Phase 3), and finally exchanges flip-flops among scan-paths in order to reduce total scan-path length (Phase 4). Experiments using actual design data show that, for ten scan-paths, our algorithm achieved a 90% reduction in scan-test time at the expense of a 7% total scan-path length increase as compared with the length of a single optimized scan-path. Also, our algorithm produced less total scan-path length than other three possible algorithms in a reasonable computing time.

Miniaturized opto and microwave receiver module using DCCPWs (Double Conductor Coplanar Waveguides) have been developed for active phased array antennas. The module comprised by a microstrip-to-slot transition, two chips of low-noise MMIC amplifiers, and a laser diode module is fabricated on an ultra-thin package with 10301.5 mm3 in size and 2 g in weight to achieve an ultra-thin structure of active phased array antenna panels. The ultra-thin structure is attributed to the design of low-noise MMIC amplifiers using DCCPWs and laser diode modules using silicon V-groove technology and fiber alignment method.

The flip-chip structure for millimeter-wave MMICs has been investigated to obtain high performance and high reliability. In our approach, an air gap between the MMIC and the alumina substrate was determined so as not to change electrical characteristics from those of the unflipped MMIC. We calculated the proximity effect between the MMIC and the substrate by using 3D-electromagnetic simulator, and found that the air gap should be controlled to be greater than 20 µm. Since the discontinuity of transmission lines at bump interconnects is not negligible above 60 GHz, we constructed the LCR-equivalent circuit for the bump interconnect and confirmed its validity by comparing measurement with calculation. Based on these investigations, the 60- and 76-GHz-band CPW three-stage low noise amplifiers were successfully mounted on the alumina substrate using a thermal compression bonding process. The gain of the flipped 60- and 76-GHz-band MMICs are greater than 18 dB at around 60 GHz and 17 dB at around 76 GHz, respectively. The noise figures are 3.6 dB and 3.9 dB, respectively. The gain and noise performances showed little degradation compared to those of the unflipped MMICs when appropriate bonding conditions are given. We confirmed that the flip-chip structure has high reliability under a thermal cycle test. From these results, flip-chip technology is promising for millimeter-wave applications.

This paper describes a new millimeter-wave hybrid integrated circuit (HIC) technology which applies a thin film multi-layered dielectric substrate and flip-chip bonding technology employing stud bump bonding (SBB). We have previously proposed and demonstrated a novel HIC structure, named millimeter-wave flip-chip IC, (MFIC), applying an excellent dielectric material of benzocyclobutene (BCB) thin film and flip-chip bonding. In this paper, an advanced thin film multi-layer process using non-photosensitive BCB was newly developed. Characteristics of the transmission lines and the built-in MIM capacitor within the multi-layered structure were discussed. Furthermore, stud bump bonding was newly adapted to the MFIC as a flip-chip method, and the millimeter-wave characteristics of the bumps were examined. Using these technologies, we demonstrate characteristics of a miniaturized 25 GHz down converter MFIC. Our newly proposed HIC structure enabled us to bring down chip size to less than 1/3 of our conventional structure. Finally, we discuss future possibilities for high performance multi-chip-modules (MCMs) using SBB technology as a further improved HIC for compact millimeter-wave radio equipment.

In this paper, we introduce a high-speed and low-power Phase-Frequency Detector (PFD) that is designed using a modified TSPC (True Single-Phase Clock) positive edge triggered D flip-flop . The proposed PFD has a simple structure with using only 19 transistors. The operation range of this PFD is over 1.4 GHz without using additional prescaler circuits. Furthermore, the PFD has a dead zone less than 0.01ns in the phase characteristics and has low phase sensitivity errors. The phase and frequency error detection range is not limited as in the case of the pt-type and nc-type PFDs. Also, the PFD is independent of the duty cycle of input signals. Also, a new charge-pump circuit is presented that is based on a charge-amplifier. A stand-by current of the proposed charge-pump circuit enhances the speed of charge-pump and removes the charge sharing which causes a phase noise in the charge pump PLL. Furthermore, the effect of clock feedthrough is reduced by separating the output stage from up and down signal. The simulation results base on a third order PLL are presented to verify the lock in process with the proposed PFD and charge pump circuits. The proposed PFD and charge-pump circuits are designed using 0.8 µm CMOS technology with 5 V supply voltage.

There are two approaches for formal verification of sequential designs or finite state machines: language containment checking and symbolic model checking. To verify designs of practical size, in these two approaches, designs are represented symbolically, in practice, by ordered binary decision diagrams. In the conventional algorithm for language containment checking, finite automata given as specifications are also represented symbolically. This paper proposes a new method, called partially explicit method for checking language containment. By representing states of finite automata given as specifications explicitly, this method can remove redundant computations, and as a result, provide better performance than the conventional method which uses the product machines of designs and specifications. The experimental results show that this approach is effective in checking language containment symbolically.

In a real-time system, it is required to reduce the response time to an interrupt signal, as well as the execution time of a Real-Time Operating System (RTOS). In order to satisfy this requirement, we have proposed a method of implementing some of the functionalities of an RTOS using hardware. Based on this idea, we have implemented a VLSI chip, called STRON (silicon TRON: The Realtime Operating system Nucleus), to enhance the performance of an RTOS, where the STRON chip works as a peripheral unit of any MPU. In this paper we describe the hardware architecture of the STRON chip and the performance evaluation results of the RTOS using the STRON chip. The following results were obtained. (1) The STRON chip is implemented in only about 10,000 gates when the number of each object (task, event flag, semaphore, and interrupt) is 7. (2) The task scheduler can execute within 8 clocks in a fixed period using the hardware algorithm when the number of tasks is 7. (3) Most of the basic µITRON system calls using the STRON chip can be executed in a fixed period of a few microseconds. (4) The execution time of a system call, measured by a multitask application program model, can be reduced to about one-fifth that in the case of the conventional software RTOS. (5) The total performance, including context switching, is about 2.2 times faster than that of the software RTOS. We conclude that the execution time of the part of the system call implemented by the STRON chip can almost be ignored, but the part of the interface software and context switching related to the architecture of a MPU strongly influence the total performance of an RTOS.

The complexity of designing communication protocols has lead researchers to develop various techniques for designing and verifying protocols. One of the most important techniques is a compositional technique. Using a compositional technique, a large and complex protocol is designed and verified by composing small and simple protocols which are easy to handle, design and verify. Unlike the other compositional approaches, we propose compositional techniques for simultaneously composing service specifications and protocol specifications based on Formal Description Techniques (FDTs) called LOTOS. The proposed techniques consider alternative, sequential, interrupt and parallel composition of service specifications and protocol specifications. The composite service specification and the composite protocol specification preserve the original behaviour and the correctness properties of individual service specifications and protocol specifications. We use the weak bisimulation equivalence (), to represent the correctness properties between the service specification and the protocol specification. When a protocol specification is weak bisimulation equivalent to a service specification, the protocol satisfies all the logical properties of a communication protocol as well as provides the services that are specified in the service specification.

Internet communication is increasingly becoming an important element in daily life. Keeping this network safe from malicious elements is an urgent task for network management. To maintain the security level networks are generally, monitored for indications of usage with ill-intentions. Such indications are events which need to be collated, correlated and analyzed in real-time to be effective. However, on an average medium to large size network the number of such events are very large. This makes it practically impossible to analyze the information in real-time and provide the necessary security measures. In this paper, we propose a mechanism that keeps the number of events, to be analyzed, low thereby making it possible to provide ample security measures. We discuss a real-time Intrusion Detection System (IDS) for detecting network attacks. The system looks out for TCP ACK/RST packets, which are generally caused by network scans. The system can extract the tendency of network flows in real-time, based on the newly developed time-based clustering and Dynamic Access Tree creation techniques. The algorithm, implemented and deployed on a medium size backbone network using RMON (Remote MONitoring) technology, successfully detected 195 intrusion attempts during a one month period. The results of the pilot deployment are discussed. In this paper, the proposal, implementation and evaluation will be described.

Miniaturized millimeter-wave HMIC amplifiers have been developed by using capacitively-coupled matching circuits (CCMC) and FETs with resistive source-stubs. CCMC includes FET's parasitic reactances, and is able to reduce the size of a matching circuit in a HMIC amplifier to about 1/3 of a conventional matching circuit using an open-circuited stub for matching and a quarter-wavelength coupled-line for d. c. blocking. The resistive source-stubs, which consist of two open-circuited stubs and a resistor, can improve the gain and stability of FETs at millimeter-wave frequencies. In this paper, design procedures of CCMC and the resistive source-stubs are described, and their usefulness has been confirmed experimentally through measurements of prototype V-band high-power HMIC amplifiers.

In general, when many functions and services are added to a system, verification and validation become difficult. In design and development in telecommunication services, conflicts that arise from combined telecommunication services have been discussed from various viewpoints. However, correctly and efficiently detecting all conflicts is still not possible and the resolution of conflicts primarily depends on expert designers, who are finding that these problems are beyond their ability. Thus, the burden on the designer must also be alleviated at the design stage. Service interference, which is discussed in this paper, is a kind of conflict. A problem of service interference is that during service, other services interfere with the ongoing service behavior. That is to say, a strange state arises, or an input event doesn't work, or a strange transition occurs, etc. The detection of service interference by only comparing states among services is not enough since the state transition must be considered in the service interference. This paper proposes how to automatically detect the service interference with a rule-based system and an extended adjacency matrix. The proposed method uses and combines features of both the adjacency matrix and rule-based system. The method first generates the extended adjacency matrix by the rule application, then extracts sequences of the state, the event, and the rule applications, and then detects the service interference with the extracted sequences.

This paper describes the effectiveness of compact semiconductor optical amplifiers (SOAs) in the photonic transport system (PTS). Such amplifiers are small enough to permit high-density packaging. SOAs, having unsaturated signal gain of 10 dB and saturation output power of 10 dBm, can improve the Q-value by 3 over the SOA input power range of 10 dB. Within this range, the signal transport distance can be expanded from 360 km to 600 km by placing SOAs on individual optical channels in a PTS even though the amplified spontaneous emission (ASE) generated by individual SOAs is combined with the optical signals and delivered to the same output fiber. This result indicates that it is useful to employ compact SOAs in the PTS for enlarging the distances between nodes.

A parallel detailed router based on the area division is one of important tools to overcome the increase of CPU time required for routing of a very large multilayer SOG. In order to conduct routing in each divided area independently, fictitious terminals are introduced on the border of each divided area, and routes connected to the fictitious terminals are concatenated to complete the final detailed routes. In this paper, we consider a problem how to position such fictitious terminals on borders, so as to make each detailed routing in a divided area easy. We formulate this problem as a minimum cost assignment problem, and propose an iterative improvement algorithm. We also give some experimental results which indicate the effectiveness of the algorithm.

Given a Petri net N=(P, T, E), a siphon is a set S of places such that the set of input transitions to S is included in the set of output transitions from S. Concerning extraction of one or more minimal siphons containing a given specified set Q of places, the paper shows several results on polynomial time solvability and NP-completeness, mainly for the case |Q| 1.

A new feature parameter based on a discrete wavelet transform is proposed for word boundary detection of isolated utterances. The sum of standard deviation of wavelet coefficients in the third coarse and weighted first detailed scale is defined as a new feature parameter for endpoint detection. Experimental results demonstrate the superiority of the proposed feature to the conventional ones in capturing word boundaries even in noisy speech.

A high gain AlGaAs/InGaAs HJFET has been developed with Embedded gate technology for Microwave and Millimeter-wave IC's using EB lithography (EMMIE). EMMIE consists of a direct SiO2 opening by two-step dry-etching with a chemically amplified resist mask. 0.14 µm gate patterns delineated on 4-inch wafers exhibited a small deviation of 10 nm in Lg and a Vth standard deviation of 55 mV. The optimum distance between the top of the gate and the recess surface (hg) was determined using a two-dimensional device simulator in order to investigate the effect of fringing gate to drain capacitance on the RF gain performance. The fabricated one-stage HJFET MMIC amplifier exhibited extremely high gain performance of 12.4 dB at 76 GHz.

Up to now, a lot of efforts have been made for the management of telecommunication networks and equipment, but less effort has been made for the realization of higher-layer service and business management. Common Object Request Broker Architecture (CORBA) provides the infrastructure for interoperability of various object-oriented management applications in a distributed environment, and being widely used to develop distributed systems in many areas of information processing technologies. There are recently worldwide growing interests for applying CORBA technology for the realization of higher layer Telecommunication Management Network (TMN) management functions. In this paper, we propose a platform architecture for the efficient integration of CORBA technology within TMN framework, where CORBA-based management functions as well as TMN-based management functions can be realized efficiently. GDMO/ASN. 1 to IDL translator has been designed and implemented for translating TMN management information into OMG CORBA IDL interface. The CORBA/CMIP gateway has also been designed for realization of the interaction translation specification of JIDM task force with some additional extensions. Finally, we evaluate the performance of the CORBA-based network management system, and analyze the code reusability for the construction of the CORBA-based management system, in order to show the efficiency of the architecture.