SpecC language is designated to handle the design of entire system from specification to implementation and of hardware/software co-design. Concurrency is one of the features of SpecC which expresses the parallel execution of processes. Describing the systems which contain concurrent behaviors would have some data exchanging or transferring among them. Therefore, the synchronization semantics (notify/wait) of events should be incorporated. The actual design, which is usually sophisticated by its characteristic and functionalities, may contain a bunch of event synchronization codes. This will make the design difficult and time-consuming to verify. In this paper, we introduce a technique which helps verifying the synchronization of events in SpecC. The original SpecC code containing synchronization semantics is parsed and translated into a Boolean SpecC code. The difference decision diagrams (DDDs) is used to verify for event synchronization on Boolean SpecC code. The counter examples for tracing back to the original source are given when the verification results turn out to be unsatisfied. Here we also introduce idea on automatically refinement when the results are unsatisfied and preset some preliminary results.

Suppose that we need to design a controller for the system x(t) = A x(t) + B u, u = -K x(t), y(t) = C x(t), where matrices A, B and C are given and K is the matrix to to determine. It is required to determine K so that y(t) should not exceed prescribed value (i.e., the peak of output y(t) is limited). This kind of specification, in general, difficult to satisfy, since the peak ymax of y(t) (we define ymax to be max0 t |y(t)|) is a non-trivial function of design parameter K, which can not be expressed explicitly generally. Therefore, a controller design with such specifications often requires try and error process. In this paper, we approximate ymax in the form of formal power series and give an efficient algorithm to compute the series. We also give a design example of a control system as an application of the algorithm.

This paper presents a transmit diversity scheme that uses space-time block codes (STBC) in space-spreading code dimensions for time-direction spreading or two-dimensional spreading orthogonal frequency-division multiplexing code-division multiplexing (OFDM-CDM) downlink transmission. The STBC output symbols in two adjacent time slots are spread by two distinctive spreading codes and multiplexed in the same spreading segment. At a receiver, the received subcarrier signals are despread with the two spreading codes in the direction of time, space-time decoded, and then combined in the direction of frequency. Simulation results demonstrated that the proposed scheme provided high tolerance to Doppler spread and outperformed space-time transmit diversity (STTD) for high-mobility users.

Recently, millimeter-wave energy has attracted much attention as a new and novel energy source for materials processing. In the present paper, several unique features of millimeter-wave heating in materials processing are reviewed briefly and development of materials processing machines by mm-wave radiation is also described. In the application of mm-wave heating, sintering of high quality alumina ceramics having a high bending strength of about 800 MPa are first demonstrated and followed by preparation of aluminum nitride with a high thermal conductivity over 200 W/(mK) at a sintering temperature lower by 473-573 K than the conventional method, by which this processing can be expected to be one of the environment-conscious energy saving processes. A newly developed post-annealing process with mm-wave radiation is described, in which crystallization of amorphous perovskite oxide films prepared by plasma sputtering was attained at temperatures lower than that by the conventional heating and the dielectric constant of post-annealed SrTiO3 (STO) films by mm-wave radiation were drastically improved.

A new method for computing precise estimates of the motion vectors of moving objects in a sequence of images is proposed. The proposed method is based on dynamic programming matching applied along chain-coded binary contours of images. This significantly reduces the computational complexity of the correspondence matching applied to the 2-D optimization problem. Computer simulation and experimental results demonstrate a good performance of the method in terms of dynamic motion analysis.

A systematic and efficient approach is presented to generating simple yet accurate symbolic expressions for transfer functions and characteristics of large linear analog circuits. The approach is based on a compact determinant decision diagram (DDD) representation of exact transfer functions and characteristics. Several key tasks of generating interpretable symbolic expressions--DDD graph simplification, term de-cancellation, and dominant-term generation--are shown to be able to perform linearly by means of DDD graph operations. An efficient algorithm for generating dominant terms is presented based on the concepts of finding the k-shortest paths in a DDD graph. Experimental results show that our approach outperforms other start-of-the-art approaches, and is capable of generating interpretable expressions for typical analog blocks in minutes on modern computer workstations.

Solution space smoothing allows a local search heuristic to escape from a poor, local minimum. In this paper, we propose a technique that can smooth the rugged terrain surface of the solution space of a placement problem. We test the smoothing heuristics for MCNC benchmarks, and for VLSI placement with pre-placed modules and placement with consideration of congestion. Experiment results demonstrated that solution space smoothing is very efficient for VLSI module placement, and it can be applied to all floorplanning representations proposed so far.

This paper addresses bitwidth optimization focusing on leakage power reduction for system-level low-power design. By means of tuning the design parameter, bitwidth tailored to a given application requirements, the datapath width of processors and size of memories are optimized resulting in significant leakage power reduction besides dynamic power reduction. Experimental results for several real embedded applications, show power reduction without performance penalty range from about 21.5% to 66.2% of leakage power, and 14.5% to 59.2% of dynamic power.

One of the important topics of watermarking technique is a robustness against geometrical transformations. In the previous schemes, a template matching is performed or an additional signal is embedded for the recovery of a synchronization loss. However, the former requires the original template, and the latter degrades the quality of image because both a watermark and a synchronization signal must be embedded. In the proposed scheme only a synchronization signal is embedded for the recovery of both a watermark and a synchronization loss. Then the embedded information depends on the distance between two embedded signal positions. The distance is not changed seriously by random geometrical transformations like StirMark attack unless the embedded signal is disturbed. Therefore, a watermark can be extracted correctly from such geometrically transformed image if the synchronization signal can be recovered.

We propose a mathematical model to analyze the performance of TD-CDMA/TDD systems in terms of call blocking probability and then find the optimum time-slot switching-point at the smallest call blocking probability considering asymmetrical traffic load distribution for various kinds of service applications.

Large-scale integration (LSI) microchips are widely used in many types of modern electronic products including electric appliances, cellular phones, toys, electronic games, and automobiles. The electromagnetic interference (EMI) noise produced by these micro devices can cause significant operational problems in other devices in the system. Some methods that have been proposed for such analysis estimates the EMI noise characteristic through transistor-level power simulation. However, in these methods, transistor-level circuit simulation is performed by combining the power-supply impedance model and the power-supply source model. In general, transistor-level simulators are too slow for practical application-specific integrated circuit (ASIC) design. In this paper, a total solution for reducing EMI noise in LSI microchips was presented. The proposed design methodology integrates fast and accurate estimation, reduction, and verification. The method was successfully applied to the design of a 32-bit microprocessor, achieving a 2-dB noise reduction in the FM frequency band and 10-dB reduction at 1 GHz. The proposed design methodology is a powerful solution for LSI designers as a tool for minimizing EMI noise and achieve higher levels of reliability for the microelectronic products.

In this paper, we propose a fault-tolerance mechanism for microprocessors, which detects transient faults and recovers from them. The investigation of fault-tolerance techniques for microprocessors is driven by two issues: One regards deep submicron fabrication technologies. Future semiconductor technologies could become more susceptible to alpha particles and other cosmic radiation. The other is the increasing popularity of mobile platforms. Cellular telephones are currently used for applications which are critical to our financial security, such as mobile banking, mobile trading, and making airline ticket reservations. Such applications demand that computer systems work correctly. In light of this, we propose a mechanism which is based on an instruction reissue technique for incorrect data speculation recovery and utilizes time redundancy, and evaluate our proposal using a timing simulator.

The deployment of server replicas of a service across an asynchronous distributed system (e.g., Internet) is a real practical challenge. This target cannot be indeed achieved by classical software replication techniques (e.g., passive and active replication) as these techniques usually rely on group communication toolkits that require server replicas to run over a partially synchronous distributed system to solve the underlying agreement problem. This paper proposes a three-tier architecture for software replication that encapsulates the need of partial synchrony in a specific software component of a mid-tier to free replicas and clients from the need of underlying partial synchrony assumptions. Then we propose how to specialize the mid-tier in order to manage active replication of server replicas.

In this paper, we propose an alternative method that does not generate a test for each path delay fault directly to generate tests for path delay faults. The proposed method generates an N-propagation test-pair set by using an Ni-detection test set for single stuck-at faults. The N-propagation test-pair set is a set of vector pairs which contains N distinct vector pairs for every transition faults at a check point. Check points consist of primary inputs and fanout branches in a circuit. We do not target the path delay faults for test generation, instead, the N-propagation test-pair set is generated for the transition (both rising and falling) faults of check points in the circuit. After generating tests, tests are simulated to determine their effectiveness for singly testable path delay faults and robust path delay faults. Results of experiments on the ISCAS'85 benchmark circuits show that the N-propagation test-pair sets obtained by our method are effective in testing path delay faults.

Since a logic circuit often has too many paths to test delay of all paths, it is necessary for path delay testing to limit the number of paths to be tested. The paths to be tested should have large delay because such paths more likely cause a fault. Additionally, a test set for the paths are required to detect other models of faults as many as possible. In this paper, we investigate two typical criteria of path selection for path delay testing. From our experiments, we observe that test patterns for the longest paths cannot cover many local delay defects such as transition faults.

We succeeded in detoxification of hexachloro-benzene adsorbed on artificially produced fly ash in air by irradiating microwave (2.45 GHz) in the presence of activated carbon powder. Hexachlorobenzene was decomposed by 50-90% at 200-300 by MW irradiation of 1-1.5 min when the ash contained activated carbon by 12 wt% and water by 10 wt%. Chlorinated benzene derivatives are dechlorinated through substitution of chloride anion with hydroxylation produced by basic CaO in the co-presence of activated carbon effectively heated by MW. This method using microwave irradiation enables us to treat the contaminated fly ash in a shorter time and decompose hexachlorobenzene more efficiently than the conventional heating.

We propose an estimation method of crosstalk noise for generic RC trees. The proposed method derives an analytic waveform of crosstalk noise in a 2-π equivalent circuit. The peak voltage is calculated from the closed-form expression. We also develop a transformation method from generic RC trees with branches into the 2-π model circuit. The proposed method can hence estimate crosstalk noise for any RC trees. Our estimation method is evaluated in a 0.13 µm technology. The peak noise of two partially-coupled interconnects is estimated with the average error of 11%. Our method transforms generic RC interconnects with branches into the 2-π model with 14% error on average.

By adding an auxiliary transformer to a single-stage single-switch power-factor-corrected converter (S4PFCC), the storage capacitor voltage and its range of voltage change against line voltage change are reduced. In addition, this transformer provides a direct power transfer path for input line to output load to increase the conversion efficiency. High power factor is maintained due to the elimination of dead angle of the input current. This paper presents detailed analysis and optimal design of a discontinuous conduction mode (DCM) boost-flyback S4PFCC with the auxiliary transformer. Experimental results for a 15 V/60 W prototype and with comparison to a S4PFCC without the auxiliary transformer are given to show the proposed approach effective.

We analyze the timing design methodology for testing chips using a multiple-clock domain scheme. We especially focus on the layout design of the design-for-test (DFT) circuits and the clock network. First, we demonstrate the built-in-self-testing (BIST) scheme for multiple-clock domains. Then, we discuss the layout method that achieves a low clock-skew between different clock domains with a small modification of the original user logic layout. Finally, we evaluate the fault coverage of our large ASIC chips designed using our new methodology. The short design period and high fault coverage of our methodology are confirmed using actual industrial designs. We introduce a viable approach for industrial designs because designers don't have to pay much attention to DFT. Our approach also provides designers with an easy method for LSI debugging and diagnostics.

In the paper we evaluate program susceptibility to hardware faults using fault injector. The performed experiments cover many applications with different features. The effectiveness of software techniques improving system dependability is analyzed. Practical aspects of embedding these techniques in real programs are discussed. They have significant impact on the final fault robustness.