This paper presents the approximate error rates of M-ary phase shift keying (MPSK) for optimum combining (OC) with multiple interferers in a flat Rayleigh fading channel. The approximations, which have been used to evaluate the performance of binary PSK for OC, are extended to the performance analysis of MPSK for OC in the presence of arbitrary numbers of antennas and interferers. The mean eigenvalues of interference-plus-noise covariance matrix are analyzed to compare the approximation techniques, i.e., first-order approximation and the orthongal approximation. Using the moment generating function (MGF)-based method, the approximate error rates of MPSK for OC are derived as the closed-form expressions in terms of the exact error rates of MPSK for MRC. The approximate analytical results show the simple and accurate way to assess the average symbol error rate of MPSK for OC with arbitrary numbers of antennas and interferers.

This paper presents a variable pipeline depth processor, which can dynamically adjust its pipeline depth and operating voltage at run-time, we call dynamic pipeline and voltage scaling (DPVS), depending on the workload characteristics under timing constraints. The advantage of adjusting pipeline depth is that it can eliminate the useless energy dissipation of the additional stalls, or NOPs and wrong-path instructions which would increase as the pipeline depth grow deeper in excess of the inherent parallelism. Although dynamic voltage scaling (DVS) is a very effective technique in itself for reducing energy dissipation, lowering supply voltage also causes performance degradation. By combining with dynamic pipeline scaling (DPS), it would be possible to retain performance at required level while reducing energy dissipation much further. Experimental results show the effectiveness of our DPVS approach for a variety of benchmarks, reducing total energy dissipation by up to 64.90% with an average of 27.42% without any effect on performance, compared with a processor using only DVS.

Computers are increasingly used for implementing control algorithms in safety-critical embedded applications, such as engine control, braking control and flight surface control. Consequently, computer errors can have severe impact on the safety of such systems. Addressing the coupling of control performance with computer related errors, this paper develops a methodology for analyzing the impacts data errors have on control system dependability. The impact of a data error is measured as the resulting control error. We use maximum bounds on this measure as the criterion for control system failure (i.e., if the control error exceeds a certain threshold, the system has failed). In this paper we a) develop suitable models of computer faults for analysis of control level effects and related analysis methods, and b) apply traditional control theory analysis methods for understanding the impacts of data errors on system dependability. An automobile slip-control brake-system is used as an example showing the viability of our approach.

Usually, paintings are more appealing than photographic images. This is because paintings can incorporate styles based on the artist's subjective view of motif. This style can be distinguished by looking at elements such as motif, color, shape deformation and brush texture. In our work, we focus on the effect of "color" element and devise a method for transforming the color of an input photograph according to a reference painting. To do this, we consider basic color category concepts in the color transformation process. We assume that color transformations from one basic color category to another may cause peculiar feelings. Therefore, we restrict each color transformation within the same basic color category. For this, our algorithm first categorizes each pixel color of a photograph into one of eleven basic color categories. Next, for every pixel color of the photograph, the algorithm finds its corresponding color in the same category of a reference painting. Finally, the algorithm substitutes the pixel color with its corresponding color. In this way, we achieve large but natural color transformations of an image.

In databases based on a multi-aspects object data model whcih enables multiple aspects of a real-world entity to be represented and to be acquired/lost dynamically, Object Migration (OM) updating membership relationships between an object and classes occurs, as the properties of the object evolve in its lifetime. We have proposed an OM behavior modeling framework using Colored Petri Nets (CPN) to analyze OM behavior. Based on the proposed framework, this paper presents a technique for constructing OM behavior models from OM constraint descriptions and class schemas as its input. The presented technique makes it easy to construct consistent and complete OM behavior models, since OM constraints are described in a simple, modular, and declarative form.

A Java execution environment is implemented, in which a hardware engine is operated in parallel with an embedded processor. This pair of hardware facilities together with an additional software kernel are devised for existing embedded systems, so as to execute Java applications more efficiently in such a way that 39 instructions are added to the original Java Virtual Machine to implement the software kernel. The exploration of design parameters is also attempted to attain a low hardware cost and high performance. The proposed hardware engine of a 6-stage pipeline can be integrated in a single chip using 30 k gates together with the instruction and data cache memories. The proposed approach improves the execution speed by a factor of 5 in comparison with the J2ME software implementation.

We have developed a planarization method applicable to large-scale superconductive Nb device fabrication. A planarized multi-layer wiring structure is obtained independently of the wiring size (width, length, and density) by combining three steps for fabricating an SiO2 insulator layer: bias-sputtering, chemical mechanical polishing, and etching with a reversal mask. Fabricated three-level wiring structures, consisting of 200- or 300-nm-thick Nb and SiO2 layers, had excellent layer flatness, and the leakage current (< 0.1 µA/cm2) between the Nb layers was sufficiently low. Two hundred chains of stepwise and stacked contacts yielded a sufficiently large critical current, typically more than 10 mA at 4.2 K.

In this paper, the method of locating multiple transmission zeros by the tap-coupling technique is described for bandpass filters (BPFs), using short-ended λ/2 resonators and its application to a duplexer. First, the method of locating the transmission zero using the short-ended λ/2 resonators is examined with various excitation methods. We focus on four types of short-ended λ/2 resonators: the end-coupling type, tap-coupling type, capacitive tap-coupling type and inductive tap-coupling type. Secondly, the BPFs based on the basic characteristics of the respective resonators are proposed and designed on the basis of a general filter theory with narrow band approximation. Lastly, we propose and design new duplexers consisting of the proposed BPFs. The results lead to the conclusion that the basic characteristics of the short-ended λ/2 resonators are useful for realizing a BPF with multiple transmission zeros and a high-performance duplexer fabricated without increasing the number of elements.

A negative thermal expansion ceramic substrate and an athermal fiber Bragg grating component with the substrate were subjected to reliability tests. We confirmed that the component has adequate durability for use as optical filters in the WDM system, under test conditions of damp heat, low temperature, mechanical shock and vibration. (50 words)

A new algorithm for fast detection and tracking of moving targets using a mobile video camera is presented. Our algorithm is based on image feature detection and matching. To detect features, we used edge points and their accumulated curvature. When the features are detected they are matched with their corresponding points using a new method called fuzzy-edge based feature matching. The proposed algorithm has two modes: detection and tracking. In the detection mode, background motion is estimated and compensated using an affine transformation. The resultant motion-rectified image is used for detection of the target location using split and merge algorithm. We also checked other features for precise detection of the target. When the target is identified, algorithm switches to the tracking mode, which also has two phases. In the first phase, the algorithm tracks the target with the intention to recover the target bounding-box more precisely and when the target bounding-box is determined precisely, the second phase of tracking algorithm starts to track the specified target more accurately. The algorithm has good performance in the environment with noise and illumination change.

Critical path selection is an indispensable step for AC delay test and timing validation. Traditionally, this step relies on the construction of a set of worse-case paths based upon discrete timing models. However, the assumption of discrete timing models can be invalidated by timing defects and process variation in the deep sub-micron domain, which are often continuous in nature. As a result, critical paths defined in a traditional timing analysis approach may not be truly critical in reality. In this paper, we propose using a statistical delay evaluation framework for estimating the quality of a path set. Based upon the new framework, we demonstrate how the traditional definition of a critical path set may deviate from the true critical path set in the deep sub-micron domain. To remedy the problem, we discuss improvements to the existing path selection strategies by including new objectives. We then compare statistical approaches with traditional approaches based upon experimental analysis of both defect-free and defect-injected cases.

As the CMOS technology enters the very deep submicron era, inter-wire coupling capacitance becomes the dominant part of load capacitance. The coupling effects have brought new challenges to routing algorithms on both delay estimation and optimization. In this paper, we propose a timing-driven global routing algorithm with consideration of coupling effects. Our two-phase algorithm based on timing-relax method includes a heuristic Steiner tree algorithm to guarantee the timing performance of the initial solution and an optimization algorithm based on coupling-effect-transference. Experimental results are given to demonstrate the efficiency and accuracy of the algorithm.

In this paper, as an important technology for the software-defined radio, a novel scheme of adaptive array antenna utilizing bandpass sampling technique is proposed. For adaptive signal processing, it is necessary to convert the radio frequency signal received by the antenna that is given by real number into baseband region, i.e., complex number region. Then, the method for dividing the bandpass sampled signal to in-phase and quadrature components is analyzed. The sampling scheme is called the IQ-division bandpass sampling. An adaptive array antenna based on the IQ-division bandpass sampling is characterized by the signal processing at the bandpass sampled signal stage, namely, intermediate frequency stage, not baseband. Finally, we will confirm the validity of the proposed scheme through an experiment in a radio anechoic chamber.

The discrete nature of data in a functional domain can generally be replaced by the global nature of data in the spectrum domain. In this paper we propose a fast procedure to detect autosymmetric function as an application of the spectrum technique. The autosymmetric function differs from the usual symmetric function and strongly relates with EXOR-based representations. It is known that many practical logical networks are autosymmetric, and this nature allows a useful functional class to realize a compact network with EXOR gates. Our procedure is able to detect autosymmetric functions quickly by using spectral coefficients. In experiments, our technique can detect the autosymmetry of most networks with a small number of checks of the spectrum.

A novel double-image Green's function approach is proposed to compute the frequency- dependent capacitance and conductance for the general CMOS oriented transmission lines with one protective layer. The ε-algorithm of Pade approximation is adopted to reduce the time for establishing coefficient matrix in this letter. The parameters gained from this new approach are shown to be in good agreement with the data obtained by the full-wave method and the total charge Green's function method.

A novel audio watermarking based on wavelet modulation is presented. The watermark signals are constructed by M-band wavelet modulation that can increase redundancy to improve the detection performance. In order to maximize the watermarking strength within the perceptual constraints, the watermark signals synthesized from different subbands are separately masked using a frequency auditory model. CDMA technique is implemented to achieve watermarking capacity. Experimental results show that this method is very robust.

Floating-point units (FPUs) are indispensable in processors, 3D-graphic engines, etc. To improve design productivity of these LSIs, FPU IPs are strongly desired. However, it is impossible to cover wide range of needs by an FPU IP, because there are various kind of options in specifications (e.g., operating frequency, latency, and ability of pipeline operation) and implementations (e.g., hardware algorithms). Thus, multiple IPs are needed even for the same functionality. In this paper, we propose to build an IP Library which consists of large number of FPU IPs with various kind of specifications and implementations, and which has catalogue data that shows not only specifications but also post-layout area and power dissipation of each IP. As the first step of the project, we have developed an IP Library targeted to Rohm 0.35 µm triple-metal process, which consists of 20 IPs for IEEE-754-standard single-precision floating-point division with 5 operating frequencies (50 MHz, 75 MHz, 100 MHz, 125 MHz, and 150 MHz), with two options whether pipelined or not, and with two hardware algorithms (the restoring method and the SRT method). We have also developed a catalogue for the IP Library, which shows post-layout area and power dissipation as well as specification of each IP. We have introduced two metrics "performance-area ratio (MFLOPS/mm2)" and "performance-power ratio (MFLOPS/W)" to afford a good insight into efficiency of implementations. From the catalogue data, the restoring method is, on the average, 1.4 times and 2.3 times better than the SRT method in terms of performance-area ratio and performance-power ratio, respectively. The developed catalogue is usable not only for selection of the optimal IP for a specific application, but also for quantitative analysis at the early stage of architecture design. It is also expected that the catalogue data based on an actual process technology is valuable for education.

In this paper, we propose a fault-tolerance mechanism for microprocessors, which detects transient faults and recovers from them. The investigation of fault-tolerance techniques for microprocessors is driven by two issues: One regards deep submicron fabrication technologies. Future semiconductor technologies could become more susceptible to alpha particles and other cosmic radiation. The other is the increasing popularity of mobile platforms. Cellular telephones are currently used for applications which are critical to our financial security, such as mobile banking, mobile trading, and making airline ticket reservations. Such applications demand that computer systems work correctly. In light of this, we propose a mechanism which is based on an instruction reissue technique for incorrect data speculation recovery and utilizes time redundancy, and evaluate our proposal using a timing simulator.

Reseeding technique is proposed to improve the fault coverage in pseudo-random testing. However most of previous works on reseeding is based on storing the seeds in an external tester or in a ROM. In this paper we present a built-in reseeding technique for LFSR-based test pattern generation. The proposed structure can run both in pseudorandom mode and in reseeding mode. Besides, our method requires no storage for the seeds since in reseeding mode the seeds can be generated automatically in hardware. In this paper we also propose an efficient grouping algorithm based on simulated annealing to optimize test vector grouping. Experimental results for benchmark circuits indicate the superiority of our technique against other reseeding methods with respect to test length and area overhead. Moreover, since the theoretical properties of LFSRs are preserved, our method could be beneficially used in conjunction with any other techniques proposed so far.

We propose an efficient algorithm for making multi-layered neural networks (MLN) fault-tolerant to all multiple weight faults in a multi-dimensional interval by injecting intentionally two extreme multi-dimensional values in the interval into the weights of the selected multiple links in a learning phase. The degree of fault-tolerance to a multiple weight fault is measured by the number of essential multiple links. First, we analytically discuss how to choose effectively the multiple links to be injected, and present a learning algorithm for making MLNs fault tolerant to all multiple (i.e., simultaneous) faults in the interval defined by two multi-dimensional extreme points. Then it is proved that after the learning algorithm successfully finishes, MLNs become fault tolerant to all multiple faults in the interval. It is also shown that the time in a weight modification cycle depends little on multiplicity of faults k for small k. These are confirmed by simulation.