In this paper, a new approach is proposed to improve the channel estimation accuracy with channel tracking capability for adaptive multicarrier equalization systems under time-variant multipath fading channel. The improvement is carried out based on the assumption that the channel is static over a transmitted block period, and slowly linearly changing over several block periods. By applying IFFT to the concatenated channel transfer function derived from different blocks, the noise-averaging improvement is achieved, and a better estimation of the channel coefficients with some delay can be obtained. A multi-step channel predictor and a smoothing filter is utilized to compensate for the delay and make the system more robust in terms of channel tracking performance. Adaptive time domain equalization is jointly performed with this approach to avoid the channel invertibility problem found in the frequency domain approach. A short period of training sequences is utilized resulting in more efficient use of available communication capacity. The effectiveness of the proposed approach is evaluated through simulation for multicarrier systems in time-variant multipath fading channels. Results show improvement over previous channel estimation schemes.

This paper proposes and investigates a coding and decoding scheme to achieve adaptive channel coding using a Finite State Machine (FSM) for Software Defined Radio (SDR). Adaptive channel coding and decoding systems that can switch between different coding rates and error correcting capabilities in order to adapt to changing applications and environments, are effective for SDR. However, in these systems, a receiver cannot always select the correct decoder which causes decoding errors, usually referred to as Decoder-Selection-Errors (DSE). We propose a trellis encoder estimation scheme that compensates for this problem. This scheme uses the circuit of FSM to limit the encoder transition and the Viterbi algorithm for maximum likelihood trellis encoder estimation. Computer simulations are applied for evaluating the DSE rate, the Bit Error Rate (BER) and Throughput of the proposed scheme in comparison with a conventional scheme.

Using the finite-difference time-domain method, we evaluated the performance of apertured near-field fiber probes with a double-tapered structure, which have exhibited, in recent experiments, a much higher collection efficiency of localized light in comparison with single-tapered probes. We clarified that this high collection efficiency could be attributed to the shortening of the cutoff region, and the efficient coupling to the guiding mode of the optical fiber. By reproducing the experimental results in terms of the spatial resolution and the collection efficiency as a function of the aperture diameter, our calculation was confirmed to be valid and useful for the design of probes in a variety of applications.

This paper presents a novel system-level design methodology, called quality-driven design, by which application-specific optimization can be achieved; furthermore the entire functionality can be shared to maximize design reuse. As a case of study, this paper focuses on quality-driven design for video applications and introduces an output quality adaptive approach based on variable bitwidth optimization to explore a new design space. MPEG2 video is used as the driver application to illustrate the potential of the presented methodology. Experimental results show the effectiveness of the methodology.

In this paper, we propose a floorplanning method for VLSI building block layout. The proposed method produces a floorplan under the timing constraint for a given netlist. To evaluate the wiring delay, the proposed method estimates the global routing cost for each net with buffer insertion and wire sizing. The slicing structure is adopted to represent a floorplan, and the Elmore delay model is used to estimate the wiring delay. The proposed method is based on simulated annealing. To shorten the computation time, a table look-up method is adopted to calculate the wiring delay. Experimental results show that the proposed algorithm performs well for producing satisfactory floorplans for industrial data.

This paper discusses a statistical effect of performance optimization to uncertainty in circuit delay. Performance optimization has an effect of balancing the delay of each path in a circuit, i.e. the delay times of long paths are shortened and the delay times of short paths are lengthened. In these path-balanced circuits, the uncertainty in circuit delay, which is caused by delay calculation error, manufacturing variability, fluctuation of operating condition, etc., becomes worse by a statistical characteristic of circuit delay. Thus, a highly-optimized circuit may not satisfy delay constraints. In this paper, we demonstrate some examples that uncertainty in circuit delay is increased by path-balancing, and we then raise a problem that performance optimization increases statistically-distributed circuit delay.

In this paper, we present a novel algorithm to the alternative wiring problem by analyzing the implication relationship between nodes of alternative wires. Alternative wiring, or rewiring, refers to the process of adding a redundant connection to a circuit so as to make a target connection redundant and removable from the circuit without altering the functionality of the circuit. The well-known ATPG-based alternative wiring scheme, Redundancy Addition and Removal for Multi-level Boolean Optimization (RAMBO), has shown its effectiveness in solving the problem in the last decade. But, the deficiency of RAMBO lies in its long execution time for redundancy identification among a large set of candidate alternative wires. Our approaches of redundancy identification by source node and destination node implication relationship indicate that a large subset of unnecessary redundancy check processes can be further avoided to improve the efficiency significantly. We propose an algorithm, the Implication Based Alternative Wiring Logic Transformation (IBAW), to integrate the two adroit techniques. IBAW provides a competent solution to the alternative wiring problem and shows an outstanding efficiency in our experiments. Experiments were performed on MCNC benchmark circuits. Results show that IBAW runs 6.8 times faster than the original RAMBO in locating alternative wires and solution quality is maintained.

An L-Band high efficiency and low distortion multi-stage amplifier using self phase distortion compensation technique is presented. In this amplifier, the bias condition of the driver-stage transistor is tuned to compensate the phase distortion of the power-stage transistor, and the load and source impedances of the driver-stage and power-stage transistors are optimized to achieve the maximum efficiency with a specified adjacent channel leakage power (ACP) for multi-stage amplifier. The developed amplifier achieves a power added efficiency (Eadd) of 42.8% and an output power (Pout) of 26.8 dBm with an ACP of -38 dBc at 1.95 GHz for wide-band code-division multiple-access (W-CDMA) cellular phones.

This paper proposes a high-level energy-optimizing algorithm which can synthesize low energy system VLSIs. Given an initial system hardware obtained from an abstract behavioral description, the proposed algorithm applies to it the three energy reduction techniques, 1) reducing supply voltage, 2) selecting lower energy modules, and 3) applying gated clocks. By incorporating our area/delay/power estimation, the proposed algorithm can obtain low energy system VLSIs meeting the constraints of area, delay, and execution time. The proposed algorithm has been incorporated into a high-level synthesis system and experimental results demonstrate effectiveness and efficiency of the algorithm.

A shared binary decision diagram (SBDD) represents a multiple-output function, where nodes are shared among BDDs representing the various outputs. A partitioned SBDD consists of two or more SBDDs that share nodes. The separate SBDDs are optimized independently, often resulting in a reduction in the number of nodes over a single SBDD. We show a method for partitioning a single SBDD into two parts that reduces the node count. Among the benchmark functions tested, a node reduction of up to 23% is realized.

This paper describes an automatic interface insertion scheme for in-system verification of algorithm models. To insert the interface, an algorithm model described in C is translated into another source code that includes the communication with hardware components in the target system to be validated with the algorithm model. The communication between the algorithm model and hardware components is achieved using transactors that perform transformation between access operations and bus cycle transactions. I/O terminal is introduced as an interface model to relate the transactions to access operations during the execution of the algorithm model, i.e., accesses to I/O terminals invoke bus cycle transactions in hardware and vice versa. An automatic interface insertion tool is developed using the source-to-source translation to identify the I/O terminals and insert interface function calls in the source code. The proposed automatic interface insertion scheme is validated by emulating several multimedia algorithms written in C on real target systems.

Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behavior. Asynchronous speed-independent (SI) circuits, whose behavior is only robust to gate delay variations, may be too optimistic. On the other hand, building circuits totally delay-insensitive (DI), for both gates and wires, is impractical because of the lack of effective synthesis methods. The paper presents a new approach for synthesis of globally DI and locally SI circuits. The method, working in two possible design scenarios, either starts from a behavioral specification called Signal Transition Graph (STG) or from the SI implementation of the STG specification. The method locally modifies the initial model in such a way that the resultant behavior of the system does not depend on delays in the input wires. This guarantees delay-insensitivity of the system-environment interface. The suggested approach was successfully tested on a set of benchmarks. Experimental results show that DI interfacing is realized with a relatively moderate cost in area and speed (costs about 40% area penalty and 20% speed penalty).

This paper describes special-purpose hardware for large-scale logic simulation, called SP2, which executes an event driven algorithm and can simulate up to sixteen million gates. SP2 was developed, in 1992, for system verification of large-scale computer designs as a successor to SP1, which was developed in 1987. SP2 provides enhanced performance, throughput, and delay accuracy over SP1. Since 1992, SP2 has been widely used for system-level simulation of mainframes, super computers, UNIX servers and microprocessors. It is used as a powerful simulator, in all stages of design verification, or in early stages, before regression testing, by using emulators.

The network duplicating can achieve significant improvements of the Local Area Network (LAN)'s performance, availability, and security. For LAN duplicating, a Dual-Path Ethernet Module (DPEM) is developed. Since a DPEM is simply located at the front end of any network device as a transparent add-on type independent hardware machine, it does not require sophisticated server reconfiguration. We examine the desirable properties and the characteristics on the Dual-LAN structure. Our evaluation results show that the developed scheme is more efficient than the conventional Single-LAN structures in various aspects.

In the case of personal computers (PCs), interoperability among PCs are sufficiently realized with the advent of Microsoft Windows to take the position of mainstream OS, and major software applications following the mainstream for standardization, for more and more user-friendly human machine interface. Considering the case for PCs as above, it is not surprising to us at all, if the same concept is pursued in a radio communications terminal, which can freely access to different radio systems just by replacing the embedded software. This means that the prospective end user will gain the benefit to be able to change his radio set to one of the desired systems in the field, by installing the software of his choice. Such radio equipment is called Software Defined Radio (SDR), and various kinds of applications are expected for development in many fields. However, for the SDR to be in widespread use, we have many outstanding issues to be solved, which are not limited only in the technical matters. One barrier is interoperability among manufacturers. Namely, even when a technical problem is solved, the appropriate technical solution should be shared for the interoperability among as many manufacturers as possible. If such interoperability is unachievable, that technical solution could only be for internal use within the specific manufacturer, failing to take advantage of the true value of the SDR. Another barrier might be the Radio Law of Japan. Unless overcoming this barrier, the commercial implementation of the SDR is unachievable, resulting in the failure to entertain the real benefit from the SDR implication. Under such a background, this paper first describes the concept of and definition for the SDR to make them clearer for the readers. Then, the interoperability issue, which would be the key to the widespread use of SDR, is taken up as next topic. The last topic is focused on the legal and regulatory issue, to discuss what would be the problem under the Radio Law of Japan.

In this paper, an online SNR estimator is proposed for parallel combinatorial SS (PC/SS) systems in Nakagami fading channels. The PC/SS systems are called as partial-code-parallel multicode DS/SS systems, which have the higher-speed data transmission capability comparing with conventional multicode DS/SS systems referred to as all-code-parallel systems. We propose an SNR estimator based on a statistical ratio of correlator outputs at the receiver. The SNR at the correlator output is estimated through a simple polynomial from the statistical ratio. We investigate the SNR estimation accuracy in Nakagami fading channels through computer simulations. In addition, we apply it to the convolutional coded PC/SS systems with iterative demodulation and decoding to evaluate the estimation performance from the viewpoint of error rate. Numerical results show that the PC/SS systems with the proposed SNR estimator have superior estimation performance to conventional DS/SS systems. It is also shown that the bit error rate performance using our SNR estimation method is close to the performance with perfect knowledge of channel state information in Nakagami fading channels and correlated Rayleigh fading channels.

When we use an adaptive array antenna (AAA) with the minimum mean square error (MMSE) criterion under the multipath environment, where the receiving signal level varies, it is difficult for the AAA to converge because of the distortion of the desired wave. Then, we need the equalization both in space and time domains. A tapped-delay-line adaptive array antenna (TDL-AAA) and the AAA with linear equalizer (AAA-LE) have been proposed as simple space-temporal equalization. The AAA-LE has not utilized the recursive least square (RLS) algorithm. In this paper, we propose a space-temporal simultaneous processing equalizer (ST-SPE) that is an AAA-LE with the RLS algorithm. We proposed that the first tap weight of the LE should be fixed and the necessity of that is derived from a normal equation in the MMSE criterion. We achieved the space-temporal simultaneous equalization with the RLS algorithm by this configuration. The ST-SPE can reduce the computational complexity of the space-temporal joint equalization in comparison to the TDL-AAA, when the ST-SPE has almost the same performance as the TDL-AAA in multipath environment with minimum phase condition such as appeared at line-of-sight (LOS).

In this paper, we analyze the convergence and steady-state behavior of the least mean-square (LMS) adaptive filtering algorithm for a finite-length phase-splitting hybrid-type decision feedback equalizer (H-DFE). With some approximations, we derive an iterative expression for the excess mean-square error (MSE) of the H-DFE, which is composed of three statistically dependent excess MSEs; that is, the excess MSEs of the feedforward filter (FFF), intersymbol interference predictive feedback filter (ISI-FBF), and noise predictive feedback filter (NP-FBF) taps. Computer simulation and analytical results show that the average eigenvalue of the input signal for the NP-FBF taps of the H-DFE is time-varying, whereas those for the FFF and ISI-FBF taps are fixed. Nevertheless, the H-DFE can be implemented with fixed step sizes that ensure the convergence of the LMS algorithm without performance degradation from the standpoint of convergence speed, as well as steady-state performance for digital subscriber line (xDSL) applications.

To promote the commercial implementation of software download for software defined radio (SDR) terminals, a secure method of download is vital. This paper examines the needs of software download for SDR, and proposes a comprehensive system framework within which secure download can be carried out. The features of the proposed system include unique individual encryption to each terminal and secure exchangeability of any cryptographic components. The main goals of the security system are the following: (i) verification of the identity of the source of the software; (ii) control and verification of the integrity of the downloaded data; (iii) disabling of the ability to run unauthorized software on the software defined terminal; (iv) secrecy of the transmitted data. The proposed system is flexible and in harmony with current requirements regarding the SDR security issues.

This paper investigates an accurate channel estimation method using the common pilot channel (CPICH) in addition to a dedicated pilot channel (PICH) when the fading correlation between the dedicated PICH and CPICH is high, and clarifies the area in which the proposed channel estimation method is effective for adaptive antenna array transmit diversity (AAA-TD) in the forward link. Computer simulation results elucidate that although a more precise channel estimation is possible by using the primary-CPICH (P-CPICH) transmitted from an omni-directional antenna in addition to the dedicated PICH for the area where the distance, d, between a base station and a mobile terminal is longer than approximately 200 m, no improvement is obtained for the area where the value of d is shorter than approximately 200 m. Meanwhile, by employing the secondary-CPICH (S-CPICH) transmitted with several directional beams in addition to the dedicated PICH, the required average received Eb/N0 at the average BER of 10-3 is decreased by approximately 0.4 (0.2-0.4) dB compared to the channel estimation method using only the dedicated PICH regardless of the value of d when the number of antennas is 4 (8).