A new learning algorithm is proposed to enhance fault tolerance ability of the feedforward neural networks. The algorithm focuses on the links (weights) that may cause errors at the output when they are open faults. The relevances of the synaptic weights to the output error (i.e. the sensitivity of the output error to the weight fault) are estimated in each training cycle of the standard backpropagation using the Taylor expansion of the output around fault-free weights. Then the weight giving the maximum relevance is decreased. The approach taken by the algorithm described in this paper is to prevent the weights from having large relevances. The simulation results indicate that the network trained with the proposed algorithm do have significantly better fault tolerance than the network trained with the standard backpropagation algorithm. The simulation results show that the fault tolerance and the generalization abilities are improved.

The convergence characteristics of the adaptive beamformer with the RLS algorithm are analyzed in this paper. In case of the RLS adaptive beamformer, the convergence characteristics are significantly affected by the spatial characteristics of the signals/noises in the environment. The purpose of this paper is to show how these physical parameters affect the convergence characteristics. In this paper, a typical environment where a few directional noises are accompanied by background noise is assumed, and the influence of each component of the environment is analyzed separately using rank analysis of the correlation matrix. For directional components, the convergence speed is faster for a smaller number of noise sources since the effective rank of the input correlation matrix is reduced. In the presence of background noise, the convergence speed is slowed down due to the increase of the effective rank. However, the convergence speed can be improved by controlling the initial matrix of the RLS algorithm. The latter section of this paper focuses on the physical interpretation of this initial matrix, in an attempt to elucidate the mechanism of the convergence characterisitics.

This paper evaluate the performance of a PN (pseudonoise) code acquisition for a direct-sequence/code-division-multiple-access (DS/CDMA) system in a mobile satellite environment. The acquisition scheme considered consists of a parallel matched-filter and a FFT processor. The uplink of mobile satellite channel is modeled as shadowed Rayleigh fading channel. The effects of power control error and shadowing are considered in the analysis of acquisition performance. It is shown that the power control error causes acquisition to be slower than the case of perfect power control, and for high SNR/chip, the effect of power control error becomes less significant. It is also shown that the case with heavy shadowing takes longer time to achieve acquisition than that with light shadowing. For the subinterval-based PN code search, the parallel MF scheme is thought to be more appropriate than the serial MF scheme at the cost of complexity. The analysis in the paper can be applied to the uplink of a DS/CDMA system for packet-type services in a mobile satellite channel.

In this paper, we propose a new transaction numbering scheme and a new validation scheme for controlling transactions optimistically in client-server architectural mobile distributed database systems (MDDBSs). In the system, mobile units (MUs) request transaction-related services, e.g., concurrency control, commit process, then the mobile support stations (MSSs) provide the required services. The mobile computing environment makes it very difficult for each MU to assign unique transaction number to transactions since it is allowed to move in communication disconnected states. Besides, validating transactions numbered by the previous transaction numbering scheme could wait indefinitely in the case of data transfer delay. Thus, we propose a new transaction numbering scheme called datatransfer time oriented transaction numbering scheme (DATTO) ,in which we can remove waiting time for validation by determining validation-start time with data-transfer completion time. However, if the previous validation scheme for the static environment is directly applied transactions numbered by DATTO, undesirable results could occur in abnormal cases due to latency on the wireless communication. Thus, we also propose a new validation scheme, called commit-order oriented validation (COOV) ,which is always able to produce correct results by applying backward validation to the abnormal cases.

Hankel's asymptotic expansions are frequently used for numerical calculation of cylindrical functions of complex order. We beforehand need to estimate the precisions of the cylindrical functions calculated with Hankel's asymptotic expansions in order to use these expansions. This letter presents comparatively simple expressions for rough estimations of the errors of the cylindrical functions calculated with the asymptotic expansions, and features of the errors are discussed.

Recurrent neural networks have the potential of performing parallel computation for associative memory and optimization, which is realized by the electronic implementation of neural networks in VLSI technology. Since the time delays in real electronic implementation of neural networks are unavoidably encountered and they can cause systems to oscillate, it is thus practically important to investigate the qualitative properties of neural networks with time delays. In this paper, a class of sufficient conditions is obtained, under which neural networks are globally asymptotically stable independent of time delays.

In this letter, we propose a blind adaptation method for the decision feedback equalizer (DFE). In the proposed scheme, a DFE is divided into two parts: a front-end linear equalizer (LE), and a prediction error filter (PEF) followed by a feedback part. The coefficients of the filters in each part are updated using constant modulus algorithm and decision feedback prediction algorithm, respectively. The front-end LE removes intersymbol interference ISI, and the PEF with feedback part whitens the noise to reduce noise power enhanced by the LE. Pre-processing by the LE enables the DFE to equalize nonminimum phase channels. Simulation results show that the proposed scheme provides reliable convergence, and the resulting symbol error rate is much less than that of the conventional LE and very close to that of the DFE using a training sequence.

This paper presents fully digital high speed (17.6Mb/s) burst modem for Offset Quadrature Phase Shift Keying (OQPSK), which employs novel digital modem VLSICs. The modulator VLSIC directly generates modulated intermediate frequency (IF) signals in a fully digitalized manner. A newly proposed digital reverse-modulation and pre-filtered carrier filter-limiter scheme realizes low power consumption and stable operation in a low Eb/No condition. The demodulator VLSIC also achieves fast bit-timing acquisition in burst mode. Moreover, it supports stable initial burst acquisition by a novel automatic frequency control (AFC) acquisition detector and a digital burst detector. A digital burst automatic gain control (AGC) compensates burst-to-burst level differences without analog circutits. Performance evaluation results show that the new modem achieves satisfactory bit-error-rate performance in severe environments. The developed modem has been employed in a commercial portable earth station for ISDN services and reduces the hardware size to one third that of the conventional one.

In this paper, we show an entropy-based approach to the privacy of multi-party protocols. First, we formulate the amount of leaked information by using mutual information for a two-party case. This is a better measure for some situations than the combinatorial measure known so far. Next, we apply multi-terminal information theoty to more than two parties and give the first formulation of the leaked information for more than two parties.

The response time of adders is mainly determined by the carry propagation delay. This letter deals with a scheme which combines the address addition and decoding together. Although addition is involved in the process, we show that it can be computed without carry propagation. Memory latency is one of the most performance limiting factors. The authors present a new decoder logic named fused add-decoder (FADEC), which performs address addition and decoding in a single process. FADEC can reduce memory latency by eliminating separate address addition cycle.

An insertion loss, branching deviation and polarization dependent loss (PDL) as to a 2 N optical splitter using silica-based planar lightwave circuits has been investigated. New key technologies such as (1) a novel wedge type Y-branch, (2) an offset waveguide at the junction between the curved input waveguide and the Y-branch, and (3) low birefringence waveguides due to the appropriate dopant concentration of a cladding, have been devised and incorporated into the splitter. As a result, 2 N optical splitters with low average insertion loss ( 13.2 dB), low branching deviation ( 0.4 dB) and low PDL ( 0.2 dB) have been successfully developed.

This paper presents a method of multiple fault diagnosis in sequential circuits by input-sequence pairs having sensitizing input pairs. We, first, introduce an input-sequence pair having sensitizing input pairs to diagnose multiple faults in a sequential circuit represented by a combinational array model. We call such input-sequence pair the sensitizing sequence pair in this paper. Next, we describe a diagnostic method for multiple faults in sequential circuits by the sensitizing sequence pair. From a relation between a sensitizing path generated by a sensitizing sequence pair and a subcircuit, the proposed method deduces the suspected faults for the subcircuits, one by one, based on the responses observed at primary outputs without probing any internal line. Experimental results show that our diagnostic method identifies fault locations within small numbers of suspected faults.

With the scale-down of VLSI chip size and the reduction of switching time of logic gates, crosstalk faults become an important problem in testing of VLSI. For synchronous sequential circuits, the crosstalk pulses on data lines will be considered to be harmless, because they can be invalidated by a clocking phase. However, crosstalk pulses generated on clock lines or reset lines will cause an erroneous operation. In this work, we have analyzed a crosstalk fault scheme, and developed a fault simulator based on the scheme. Throughout this work, we considered the crosstalk fault as unexpected strong capacitive coupling between one data line and one clock line. Since we must consider timing in addition to a logic value, the unit delay model is used in our fault simulation. Our experiments on some benchmark circuits show that fault activation rates and fault detection rates vary widely depending on circuit characteristics. Fault detection rates of up to 80% are obtained from our simulation with test vectors generated at random.

The storage utilizations of existing similar key search files based on B+-tree and extensible hashing were under 70% and should be improved. A similar key search file based on extensible hashing with partial expansion and that on linear hashing with partial expansion are proposed. Computer simulations on about 230 thousand English words show that the storage utilizations of the files with 32 expansive steps are about 97%.

This paper deals with the synthesis of Petri nets. Partial languages adequately represent the concurrent behaviors of Petri nets. We first propose a construction problem for Petri nets, in which the objective is to synthesize a Petri net to exhibit the desired behavior specified as a partial language. We next discuss the solvability of this problem and last present the cutline of a solution technique.

This paper describes new problems in delay analysis for high-performance LSI design and presents a static delay analysis tool PCHECK. PCHECK is characterized by (1) a new critical path trace algorithm for avoiding the error caused by signal transient time and (2) a precise delay calculation model for resistive shielding. Experimental results show that the delay calculation error in the worst case is less than 20 ps.

A design methodology of high performance deep submicron CMOS in very low voltage operation has been proposed from low power dissipation point of view. In low voltage operation, threshold voltage is restricted by performance, stability of CMOS circuits and power dissipation caused by standby and switching transient current. As a result, threshold voltage is established to be 0.15 V even at 1 V operation from these requirements. Moreover, according to this design, 0.15 µm CMOS was fabricated with reduction of parasitic effects. It achieved propagation delay time 50 psec at 1 V operation. This results confirms that this design methodology is promising to achieve high performance deep submicron CMOS devices for low power dissipation.

The local wiring structure which is known as a technique for reducing junction capacitance due to the area reduction of the Source/Drain junction by the "on-field" contact scheme was constructed. Its effect on speed/power improvement was evaluated with a ring oscillator. A speed improvement of 15% and a 17% reduction in power dissipation was obtained as compared with conventional non-local wiring structures. This technique was applied to a practical device application, that is, a 0.35 µm embedded dual port SRAM used as a buffer memory in an asynchronous transfer mode switch (ATM-SW) LSI. In order to suppress the coupling noise between the write and read bitlines with the small cell realized by the local wiring scheme, a new divided layer 'bitline architecture was developed. As a result, reduction of SRAM macro size of 31% was attained by also applying the local wiring scheme to peripheral circuits, such as decoder, sense amplifier, and driver. A detailed analysis on this embedded dual port SRAM revealed a 15.2% reduction of write port power at 3.3 V. It is also shown that the local wiring technique is more effective with low power supply voltages to allow for further power reduction.

Mechanism of the noise generation caused by the optical feedback in semiconductor laser was experimentally determined. Two types of the mode competition phenomena were confirmed to be the generating mechanisms. Applicability of the self-sustained pulsation to be a noise reduction method was also discussed.

To evaluate DRAM memory-cell data retention characteristics, measuring the leakage current of the individual memory-cell is important. However, the leakage current of a DRAM memory-cell cannot be measured directly, because its value is on the order of femtoamperes. This paper describes a Plate Bumping (PB) method that can measure the leakage current of a specific memory-cell using the relationship between the shifted value of memory-cell-plate potential and the retention period. By using the PB method, it can be confirmed that the leakage current of the short-retention cell (bad cell) depends on its storage-node potential. With regards to cells with "0" data stored in them ("0" cells), it appears that the relaxed junction biasing (RJB) scheme which can extend refresh interval increases the number of misread "0" cells due to the lowering of the sense amplifier's sensing threshold.