We present a 64-b adder having a 2.6-ns delay time at 3.3 V power supply within 0.27 mm2 using 0.5-µm CMOS technology. We derived our adder design from architectural level considerations. The considerations include not only the gate intrinsic delay but also the wiring delay and the gate capacitance delay. As a result, a 64-b adder, (56-b Carry Look-ahead Adder(CLA) +8-b Carry Select Adder (CSA)), was designed. In this design, a new carry select scheme called Modified Carry Select (MCS) is also proposed.

A new superresolution technique is proposed for high-resolution estimation of the scattering analysis. For complicated multipath propagation environment, it is not enough to estimate only the delay-times of the signals. Some other information should be required to identify the signal path. The proposed method can estimate the frequency characteristic of each signal in addition to its delay-time. One method called modified (Root) MUSIC algorithm is known as a technique that can treat both of the parameters (frequency characteristic and delay-time). However, the method is based on some approximations in the signal decorrelation, that sometimes make problems. Therefore, further modification should be needed to apply the method to the complicated scattering analysis. In this paper, we propose to apply a time-domain null filtering scheme to reduce some of the dominant signal components. It can be shown by a simple experiment that the new technique can enhance estimation accuracy of the frequency characteristic in the Root-MUSIC algorithm.

It is demonstrated with the Berlekamp-Massey shift-register synthesis algorithm that the linear complexity value of binary complementary sequences is at least 3/4 of the sequence length. For some sequence pairs the linear complexity value can be even 0.98 times the sequence length. In the light of these results strongly non-linear complementary sequences are considered suitable for information security applications employing the spread-spectrum (SS) technique.

It is known that the problem of determining, given a planar graph G with maximum vertex degree at most 4 and integers m and n, whether G is embeddable in an m n grid with unit congestion is NP-hard. In this paper, we show that it is also NP-complete to determine whether G is embeddable in ak n grid with unit congestion for any fixed integer k 3. In addition, we show a necessary and sufficient condition for G to be embeddable in a 2 grid with unit congestion, and show that G satisfying the condition is embeddable in a 2 |V(G)| grid. Based on the characterization, we suggest a linear time algorithm for recognizing graphs embeddable in a 2 grid with unit congestion.

This paper proposes a new formulation which minimizes the differential entropy for an optimal control problem. The conventional criterion of the optimal regulator control is a standard quadratic cost function E[M{x(t)}2} + N{v(t)}2], where x(t) is a state variable, u(t) is an input value, and M and N are positive weights. However, increasing the number of the variables of the system it is complex to find the solution of the optimal regulator control. Therefore, the simplicity of the solution is required. In contrast to the optimal regulator control, we propose the minimum entropy control which minimizes a differential entropy of the weighted sum of x(t) and u(t). This solution is derived on the assumptions that the linear control and x(t)u(t) 0 are satisfied. As the result, the formula of the minimum entropy control is very simple and clear. This result will be useful for the further work with multi variables of simple control formulation.

This paper investigates some fundamental properties of alternating one-way (or two-way) pushdown automata (pda's) with sublogarithmic space. We first show that strongly (weakly) sublogarithmic space-bounded two-way alternating pda's are more powerful than one-way alternating pda's with the same space-bound. Then, we show that weakly sublogarithmic space-bounded two-way (one-way) alternating pda's are more powerful than two-way (one-way) nondeterministic pda's and alternating pda's with only universal states using the same space, and we also show that weakly sublogarithmic space-bounded one-way nondeterministic Turing machines are incomparable with one-way alternating Turing machines with only universal states using the same space. Furthermore, we investigate several fundamental closure properties, and show that the class of languages accepted by weakly sublogarithmic space-bounded one-way alternating pda's and the class of languages accepted by sublogarithmic space-bounded two-way deterministic pda's (nondeterministic pda's, alternating pda's with only universal states) are not closed under concatenation, Kleene closure, and length preserving homomorphism. Finally, we briefly investigate a relationship between 'strongly' and 'weakly'.

An ordered binary decision diagram (OBDD) is a directed acyclic graph for representing a Boolean function. OBDDs are widely used in various areas which require Boolean function manipulation, since they can represent efficiently many practical Boolean functions and have other desirable properties. However, there is very little theoretical research on the complexity of constructing an OBDD. In this paper, we prove that the optimal variable ordering problem of a shared BDD is NP-complete, and briefly discuss the approximation hardness of this problem and related OBDD problems.

For the purpose of automatic speech recognition, language models (LMs) are used to predict possible succeeding words for a given partial word sequence and thereby to reduce the search space. In this paper several kinds of stochastic language models (SLMs) are evaluated-bigram, trigram, hidden Markov model (HMM), bigram-HMM, stochastic context-free grammar (SCFG) and hand-written Bunsetsu Grammar. To compare the predictive power of these SLMs, the evaluation was conducted from two points of views: (1) relationship between the number of model parameters and entropy, (2) predictive rate of succeeding part of speech (POS) and succeeding word. We propose a new type of bigram-HMM and compare it with the other models. Two kinds of approximations are tried and examined through experiments. Results based on both of English Brown-Corpus and Japanese ATR dialog database showed that the extended bigram-HMM had better performance than the others and was more suitable to be a language model.

In this paper, we present some contributions to improve a previous work's approach presented for the segmentation of magnetic resonance images of the human brain, based on the unsupervised Hopfield neural network. We formulate the segmentation problem as a minimization of an energy function constructed with two terms, the cost-term as a sum of errors' squares, and the second term is a temporary noise added to the cost-term as an excitation to the network to escape from certain local minimums and be more close to the global minimum. Also, to ensure the convergence of the network and its utility in clinic with useful results, the minimization is achieved with a step function permitting the network to reach its stability corresponding to a local minimum close to the global minimum in a prespecified period of time. We present here our approach segmentations results of a patient data diagnosed with a metastatic tumor in the brain, and we compare them to those obtained based on, previous works using Hopfield neural networks, Boltzmann machine and the conventional ISODATA clustering technique.

Various kinds of new architectures have been proposed to enhance operating performance of the DRAM. This paper reviews these architectures including EDO, SDRAM, RDRAM, EDRAM, and CDRAM. The EDO slightly modifies the output control of the conventional DRAM architecture. Other innovative architectures try to enhance the performance by taking advantage of DRAM's internal multiple bits architecture with internal pipeline, parallel-serial conversion, or static buffers/on-chip cache. A quantitative analysis based on an assumption of wait cycles was made to compare PC system performance with some architectures. The calculation indicated the effectiveness of external or on-chip cache. Future trends cover high-speed I/O interface, unified memory architecture, and system integrated memory. The interface includes limited I/O swing such as HSTL and SSTL to realize more than 100MHz operation. Also, Ramlink and SyncLink are briefly reviewed as candidates for next generation interface. Unified memory architecture attempts to save total memory capacity by combining graphics and main memory. Advanced device technology enables system integration which combine system logic and memory. It suggests one potential direction towards system on a chip in the future.

Using fundamental device and circuits, we have realized three functions required for synaptic connections in self-organizing neural networks: long term memory of synaptic weights, fixed total amount of synaptic weights in a neuron, and lateral inhibition. The first two functions have been condensed into an optical adaptive device and circuits with floating gates. Lateral inhibition has been realized by a winner-take-all circuit and a following lateral excitatory connection circuit. We have fabricated these devices and circuits using CMOS technology and confirmed the three functions. In addition, topological mapping, which is essential for feature extraction, has been formed in a primitive network constructed with the fundamental device and circuits.

Discussed here is progress achieved in the development of video codec LSIs.First, the amount of computation for various standards, and signal handling capability (throughput) and power dissipation for video codec LSIs are described. Then, general technologies for improving throughtput are briefly summarized. The paper also reviews three approaches (i.e., video signal processor, building block and monolithic codes) for implementing video codes standards. The second half of the paper discusses various high-throughput technologies developed for programmable Video Signal Processor (VSP) LSIs. A number of VSP LSIs are introduced, including the world's first programmable VSP, developed in February 1987 and a monolithic codec ship, built in February 1993 that is sufficient in itself for the construction of a video encoder for encoding full-CIF data at 30 frames per second. Technologies for reduction of power dissipation while keeping maintaining throughput are also discussed.

This paper proposes a mutual exclusion method that is unified for the parallel and distributed systems. The method partially serializes requests into partial queues of requests, which are next totally serialized into a main queue. A request in the main queue is authorized to enter the critical section (CS) when the request receives the privilege token from the previous request in the queue. In the distributed system of N sites that each is a parallel system, mutual exclusion is performed by cooperation of two algorithms based on the same method. The algorithm for the distributed system works on a logical network (that is a directed tree) of S ( N) sites. The algorithm for each site produces a local-main queue of requests. The chunk of requests in the local queue is concatenated at a time to the partial queue of the distributed system. The the cost of mutual exclusion -- the number of intersite messages required per CS entry -- is reduced to O(1) (between 0 and 3).

This paper describes a new active pull-up (APU) interface for high-speed point-to-point transmission. The APU circuit is used to speed up a low-power-consumption open-drain-type interface. It pulls up the output at a fixed duration and this limiting of the pull-up duration prevents the pull-up operation from going into a counter phase at over 1-Gbps operation. Measurements of test chips fabricated with 0.25-µm bulk CMOS show. 1.7-Gbps error-free operation for the APU interface and 1.2-Gbps operation for the open-drain-type interface: The APU interface is 1.4 faster than the open-drain type. The application of a 0.25-µm SIMOX-CMOS device to the APU interface increases the bit rate 1.5 times compared with 0.25-µm bulk CMOS. Altogether the interface covers the bit rate of 2.4 Gbps, which is a layer of the communication hierarchy. The APU interface circuit can be applied to large-pin-count LSIs because of its full-CMOS single-rail structure.

A novel method of multichannel surface EMG processing has been developed to compensate for the distortion in bipolar surface EMG signals due to the movement of innervation zones. The distortion of bipolar surface EMG signals was mathematically described as a filtering function. A compensating technique for such distorted bipolar surface EMG signals was developed for the brachial biceps during dynamic contractions in which the muscle length and tension change. The technique is based on multichannel surface EMG measurement, a method for estimating the movement of an innervation zone, and the inverse filtering technique. As a result, the distorted EMG signals were compensated and transformed into nearly identical waveforms, independent of the movement of the innervation zone.

The realization of scientific manufacturing of ULSIs in the 21st century will require the development of a technical infrastructure of "Ultra Clean Technology" and the firm establishment of the three principles of high performance processes. Three principles are 1)Ultra Clean Si Wafer Surface, 2)Ultra Clean Processing Environment, and 3)Perfect Parameter controlled process. This paper describes the methods of resolving the problems inherent in Ultra Clean Technology, taking as examples issues in quarter-micron or more advanced semiconductor process and manufacturing equipment, particularly when faced with the challenges of plasma dry etching. Issues indispensable to the development of tomorrow's highly accurate and reliable plasma dry etching equipment are the development of technologies for the accurate measurement of plasma parameters, ultra clean gas delivery systems, chamber cleaning technology on an in-situ basis, and simulating the plasma chemistry.This paper also discusses the standardization of semiconductor manufacturing equipment, which is considered one of the ways to reduce the steep rise in production line construction costs. The establishment of Ultra Clean Technology also plays a vital role in this regard.

A regeneration technology of fluorite (CaF2) from spent HF and Buffered HF (BHF) has been investigated. The mechanism of "direct conversion" of granular calcite (CaCO3) into granular fluorite has revealed and several special phenomena are first found to be efficient. An advanced system has been developed. This system regenerates granular fluorite by conversion of granular calcite filled in a column. High purity and low water fluorite is recovered as a substitute for natural fluorspar (CaF2). The fluorine concentration in the processed effluent is minimized to a level of 5 ppm. The separation of the HF processing line and BHF processing line equipped ammonia stripper is an important to system design because ammonia generated from BHF significantly retards the conversion efficiency from CaCO3 to CaF2. The new system reforming the conventional slaked lime processing solves long-pending problem, resulting in a very compact system with a very small amount of product.

An adaptive algorithm for a single sinusoid detection using IIR bandpass filter with parallel block structure has been proposed by Nishimura et al. However, the algorithm has three problems: First, it has several input frequencies being impossible to converge. Secondly, the convergence rate can not be higher than that of the scalar structure. Finally, it has a large amount of computation. In this paper, a new algorithm is proposed to solve these problems. In addition, a new structure is proposed to reduce the amount of computation, in which the adaptive control signal generator is realized by the paralel block structure. Simulation results are given to illustrate the performance of the proposed algorithm.

Optical Feedering between Base Stations and Control Station is an effective technique for future microcellular mobile communication systems. The use of Laser Diode (LD) in such a system leads to the generation of intermodulation products, which consequently affect a system performance and ultimately restrain the maximum number of users that the system can serve. The problem becomes further intensified in case of CDMA system which is a candidate for future cellular mobile and personal communication systems. In this paper LD's Nonlinearity compensation technique for Direct Sequence spread spectrum CDMA signals in optical communication system is presented. This technique involves the implementation of a nonlinear block herein after called Post Nonlinearity Recovery Block (PNRB). This block is designed to exhibit the characteristics inverse to those of LD. The block is designed theoretically by deriving the complete expressions for Transfer functions. Some useful results of theoretical investigation of a proposed scheme have been presented, which form the basis for the experimental test system. The work is novel because, (i) Compensation analysis has been carried out for DS-CDMA signals for the first time, and (ii) Compensation has been proposed on the control station instead of base station, which is different from the conventional techniques and offers several additional advantages. Performance of the system with and without PNRB is evaluated by Intermodulation Distortion (IMD) and SNR Analysis. The results show that LDs' nonlinearity distortion level can be compensated to a remarkable extent.

This paper proposes an algorithm for the design of FIR digital filters whose coefficients have CSD representations. The total number of nonzero digits is specified. A set of filters whose frequency responses have less than or equal to a given Chebyshev error have their coefficients in a convex polyhedron in the Euclid space. The proposed algorithm searches points where a coefficient is maximum or minimum in the convex polyhedron by using linear programing. These points are connected whih the origin to make a convex cone. Then the algorithm evaluates CSD points near these edges of the cone. Moving along these edges means the scaling of frequency responses. The point where the frequency response is the best among all the candidates under the condition of specified total number of nonzero digits is selected as the solution. Several techniques are used to reduce the calculation time. Design examples show that the proposed method can design better frequency responses than the conventional methods.