A cumulant-based lattice algorithm for multichannel adaptive filtering is proposed in this paper. Proposed algorithm takes into account the advantages of higer-order statistics, that is, improvement of estimation accuracy, blindness to colored Gaussian noise and the possibility to estimate the nonminimum-phase system etc. Without invoking the Instrumental Variable () method as used in other papers [1], [2], the algorithm is derived directly from the recursive pseudo-inverse matrix. The behavior of the algorithm is illustrated by numerical examples.

This paper proposes an adaptive modulation system with a punctured convolutional code for land mobile communications to achieve high quality, high bit rate, and high spectral efficient data transmission in multipath fading environments. The proposed system adaptively controls the coding rate of the punctured convolutional code, symbol rate, and modulation level according to the instantaneous fading channel conditions. During good channel conditions, the modulation parameters are selected to increase the transmission rate as much as possible with satisfying a certain transmission quality. As channel conditions become worse, lower rate modulation parameters are applied or transmission is stopped. The performances in fading environments are evaluated theoretically and by computer simulations. The results show that the proposed system can realize higher quality transmission without the degradation in average bit rate compared to conventional adaptive modulation systems.

In an adaptive load balancing, the location policy to determine a destination node for transferring tasks can be classified into three categories: dynamic selection, random selection, and state polling. The dynamic selection immediately determines a destination node by exploiting the state information broadcasted from other nodes. It not only requires the overheads of collecting the state information, but may cause an unpredictable behavior unless the state information is accurate. Also, it may not guarantee even load distribution. The random selection determines a destination node at random. The state polling determines a destination node by polling other nodes. It may cause some problems such as useless polling, unachievable load balancing, and system instability. A new Sender-initiated Adaptive LOad balancing scheme (SALO) is presented to remedy the above problems. It determines a destination node by exploiting the predictable state knowledge and by polling the destination node. It can determine a good destination with minimal useless polling and guarantee even load distribution. Also, it has an efficient mechanism and good data structure to collect the state information simply. An analytic model is developed to compare with other well known schemes. The validity of the model is checked with an event-driven simulation. With the model and the simulation result, it is shown that SALO yields a significant improvement over other schemes, especially at high system loads.

In this paper, we study three-dimensional motion estimation using optical flow. We construct a weighted quotient-form objective function that provides an unbiased estimator. Using this objective function with a certain projection operator as a weight drastically reduces the computational cost for estimation compared with using the maximum likelihood estimator. To reduce the variance of the estimator, we examine the weight, and we show by theoretical evaluations and simulations that, with an appropriate projection function, and when the noise variance is not too small, this objective function provides an estimator whose variance is smaller than that of the maximum likelihood estimator. The use of this projection is based on the knowledge that the depth function has a positive value (i. e., the object is in front of the camera) and that it is generally smooth.

A regeneration technology of fluorite (CaF2) from spent HF and Buffered HF (BHF) has been investigated. The mechanism of "direct conversion" of granular calcite (CaCO3) into granular fluorite has revealed and several special phenomena are first found to be efficient. An advanced system has been developed. This system regenerates granular fluorite by conversion of granular calcite filled in a column. High purity and low water fluorite is recovered as a substitute for natural fluorspar (CaF2). The fluorine concentration in the processed effluent is minimized to a level of 5 ppm. The separation of the HF processing line and BHF processing line equipped ammonia stripper is an important to system design because ammonia generated from BHF significantly retards the conversion efficiency from CaCO3 to CaF2. The new system reforming the conventional slaked lime processing solves long-pending problem, resulting in a very compact system with a very small amount of product.

A new observation technique for process-induced micro-defects in ULSI using a combination of anodic oxidation and chemical removal of the oxide has been developed. Enhanced oxidation has occurred at the defect region due to the stress field and then craterlike delineation has been formed after oxide removal. AFM and SEM observation of the micro-defects induced by ion implantation and applications using this tech-nique to the failure analysis of MOS device fabrication are presented.

According as the fine LSI process technique develops, the technique to reduce power dissipation of high-frequency integrated analog circuits is getting more important. This paper describes a design of high-frequency integrator with low power dissipation for monolithic leapfrog filters. In the design of the conventional monolithic integrators, there has been a great dfficulty that a high-frequency integrator which can operate at low supply voltage cannot be realized without additional circuits, such as unbalanced-to-balanced conversion circuits and common-mode feedback circuits. The proposed integrator is based on the Miller integrator. By a PNP current mirror circuit, high CMRR is realized. However, the high-frequency characteristic of the integrator is independent of PNP transistors. In addition, it can operate at low supply voltage. The excess phase shift of the integrator is compensated by insertion of the compensation capacitance. The effectiveness of the proposed technique is confirmed by PSPICE simulation. The simulation results of the integrator shows that the common-mode gain is efficiently low and the virtual ground is realized, and that moderate phase compensation can be achieved. The simulation results of the 3rd-order leapfrog filter using the integrator shows that the 50 MHz-cutoff frequency filter is obtained. Its power dissipation in operating 2 V-supply voltage is 5.22 mW.

A novel technique for evaluation of charge build-up in semiconductor wafer processing such as ion implantation, plasma etching and plasma enhanced chemical vapor deposition by using the breakdown of MOS capacitors with charge collecting electrodes (antenna) is proposed. The charge build-up during high beam current ion implantation is successfully evaluated by using this technique. The breakdown sensitivity of a MOS capacitor is improved by using a small area MOS capacitor with a large area antenna electrode. To estimate charge build-up on wafers quantitatively, the best combination of gate oxide thickness, substrate type, MOS capacitor area and antenna ratio should be carefully chosen for individual charge build-up situation. The optimum structured antenna MOS capacitors which relationship between QBD and stressing current density was well characterized give us very simple and quantitative charge build-up evaluation. This technique is very simple and useful to estimate charge build-up as compared with conventional technique by suing EEPROM devices or large area MOS capacitors.

An architecture for a high-density nonvolatile memory with ferroelectric capacitors is proposed and simulated. The architecture includes: (1) the operation procedure for DRAM-like memory cells with a Vcc/2 common plate, (2) commands and pin arrangement compatible with those of DRAMs. The resulting ferroelectric memory is expected to show, in addition to nonvolatility, high performance in terms of speed, active power dissipation, and read endurance. In addition, the memory can be handled in the same way as DRAMs. The proposed basic operations are confirmed by using circuit simulations, in which an equivalent circuit model for ferroelectirc capacitors is incorporated. A problem remaining with the architecture is low write endurance due to fatigue along with polarization switching. Designing the reference-voltage generator for 1T1C (one-transistor and one-capacitor) cells, while considering signal reduction along with fatigue, will be another issue for achieving high-density comparable to that of DRAMs.

This paper proposes a topology-independent predistortion for filters using integrators. This employs integrators having the same structure, the same-value elements and an electrically controllable unity-gain frequency and compensates for the deviation of frequency characteristics due to excess phase shifts of integrators without knowledge of a filter topology. The effectiveness of the proposed method is demonstrated through SPICE simulations.

In this paper, a new encoding/decoding scheme of multiple-valued separable balanced codes is presented. These codes have 2m information digits and m (R - 2) check digits in radices R 4, 2m - 1 information digits and m + 1 check digits in R = 3, where code-length n = Rm. In actual use of code-lengths and radices, it is shown that the presented codes are relatively efficient in comparison with multiple-valued Berger codes which are known as optimal unordered codes. Meanwhile, the optimality of multiple-valued Berger codes is discussed.

This letter shows that a portable visual stimulator for MEG measurements can be realized using an optical fiber bundle and a CRT display system offering high brightness and high speed raster scanning, and that MEGs with neither magnetic contamination nor jitter can be measured by the stimulator.

A novel reactive congestion control scheme based on Dynamic UPC/NPC (Usage/Network Parameter Control) in ATM networks is proposed. In this scheme, policing parameters at the UPC/NPC are dynamically modified in response to the reception of RM (Resource Management) cells. In a congested state, traffic volume submitted to the network is regulated by Dynamic UPC/NPC, while providing negotiated QoS (Quality of Service) for each ATM connection. When end-stations (or edge-entities between network segments) operate according to ER-based (Explicit Rate based) behavior, a UPC/NPC function will indicate (send) an ER value toward each source end-station using backward RM cells. In this case, the policing parameter at the UPC/NPC should take the same value as the ER value. When end-stations (or edge-entities) operate according to EFCI-based (Explicit Forward Congestion Indication based) behavior, the modified policing parameter at the UPC/NPC point must be harmonized with the modified cell transmission rate at the source end-stations (or at the edge-entities). In order to improve the control performance for the long distance connections, backward RM cells will be generated by the NPC function (UPC function will be optional) at the egress of a congested network in response to the reception of EFCI marked cells (or forward RM cells) as a proxy destination end-station, and they will be sent back toward the UPC/NPC function at the ingress of the network. As a result, the proposed control scheme enables the network to recover from the congested state securely and provide the negotiated service quality, even if cooperation of (rate-based) flow control at each source end-station (and at edge-entities between network segments) is not expected.

New series expressing the radiation fields from both axial and circumferential slots on a circular conducting cylinder are derived. These new series converge rapidly even for near fields. This letter includes useful figures showing characteristics of near fields calculated numerically using the new series.

This work addresses the problems of bit allocation and coding gain in subband coding system with non-paraunitary filter banks. Since energy conservation does not hold in non-paraunitary filter banks, the model to be adopted for quantizers is important to evaluate the output distortion introduced by subband signal quantization. To evaluate the overall distortion we start with adopting the gain plus additive noise model for quantizers, which is more reliable than the additive noise model. With this model, the expression for overall reconstruction error variance becomes so complicated that the problem of optimum bit allocation, as required for evaluation of the coding gain, must be numerically solved. So, we propose an approximation method in which we neglect the terms due to correlation among quantization errors in calculating the bit allocation but take them into consideration in evaluating the coding gain, assuming sufficiently high bitrate coding. Application of this approximation method to the SSKF subband coding systems with AR (1) input source shows that the method is very accurate even at low bit rate coding (1 bit/sample).

The electrical characteristics of sealed CMOSFETs with gates crossing sources/drains at 90 and 45 are experimentally investigated using test devices fabricated by an n-well CMOS process with trench isolation. Gain factors of surface-channel 90 and 45 n-MOSFETs can be estimated by a simple correction theory based on the combination of a center MOSFET and two edge MOSFETs. However, relatively large departures from the theory are observed in buried-channel 90 and 45 p-MOSFETs with widths less than the channel length. The difference between n- and p-MOSFETs is mainly due to the channel type. Other basic device parameters such as saturation drain currents, threshold voltages, subthreshold swings, maximum substrate currents and substrate-voltage dependence of threshold voltages are also measured and qualitatively explained.

This paper describes the new analog-digital merged circuit architecture which utilizes the pulse modulation signals. By reconsidering the information representing and processing principles, and the circuit operations governed by the physical law, the new circuit architecture is proposed to overcome the limitations of existent VLSI technologies. The proposed architecture utilizes the pulse width modulation (PWM) signal which has analog information in the time domain, and be constructed with the novel PWM circuits which carry out the multi-input arithmetic operations, the signal conversions and the data storage. It has a potential to exploit the high speed switching capability of deep sub-µm devices, and to reduce the number of devices and the power dissipation to one-tenth of those of the binary digital circuits. Therefore it will effectively implement the intelligent processing systems utilizing 0.5-0.2µm scaled CMOS devices.

We study the capacity assignment and routing procedure for a simultaneous multipoint-to-point communication network called convergence cast communication (con-cast). In capacity assignment, we analyse the network in two different application model, single destination and variable destination concast group. In each model, we determine the optimal capacity and network configuration. In routing procedure, since the problem is computationally intractable[1], [2], we present a heuristic algorithm that, under condition of the capacity constraint, selects a set of connections for n-1 separated points to one point. This is accomplished by considering a hierarchical structure and a flow decomposition technique in the network. The algorithm finds a solution for connection assignment in convergence-type communications. Theoretical analysis and computer simulation of the proposed method are given.

An ATM network design algorithm is treated as a resource allocation problem. As an effective way to facilitate a coexistence of traffic with its diverse characteristics and different quality of service (QOS) requirements in ATM networks, a virtual path (VP) concept has been proposed. In attempting to design the VP (Virtual Path)-based ATM network, it requires to consider a network topology and traffic pattern generated from users for minimizing a network construction cost while satisfying QOS requirements such as cell / call loss probabilities and cell delay times. In this paper, we propose a new heuristic design algorithm for the VP-based ATM network under QOS constraints. A minimum bandwidth required to transfer a given amount of traffic is first obtained by utilizing an equivalent bandwidth method. After all the routes of VPs are temporarily established by means of the shortest paths, we try to minimize the network cost through the alternation of VP route, the separation of a single VP into several VPs, and the introduction of VCX nodes. To evaluate our design algorithm, we consider two kinds of traffic; voice traffic as low speed service and still picture traffic as high speed service. Through numerical examples, we demonstrate that our design method can achieve an efficient use of network resources, which results in the cost-effective VP-based ATM network.

In this article, a new multiplication type D/A conversion system using CCD is proposed and the result of simulations for evaluating its performance is reported. The system consists of a recursive charge divider which divides input charge-packet Qin sequentially into output charge-packets Qin2-i and two charge-packet accumulators which accumulates output charge-packets from the recursive divider selectively according to digital input signal bits atarting from MSB. The system converts input digital signal bit by bit, fully in chargedomain, thus the power consumption for this system is supposed to be very low. Also in this article, an effective method to achieve higher accuracy for splitting a charge-packet into two equal-sized packets using very simple hard-ware structure is proposed. As the result of simulations, we have found that the upper limit of accuracy for the conversion is determined by transfer efficiency of CCD, and within this range a trade-off relationship exists among conversion-accuracy, circuit-size and conversion-rate. This unique relationship enables to reduce the circuit size of D/A converter significantly maintaining the accuracy of conversion by slowing down the conversion-rate. This D/A converter is appropriate especially for the system integration because of its simple structure, tolerance to the fabrication error and low power consumption inherrent in the nature of CCD. By using of this system, it is expected to be possible to realize a focal plane image processor performing parallel analog operations such as DCT conversion with CCD imager incorporated on the same Si chip by the same MOS process technology.