Discussed here is progress achieved in the development of video codec LSIs.First, the amount of computation for various standards, and signal handling capability (throughput) and power dissipation for video codec LSIs are described. Then, general technologies for improving throughtput are briefly summarized. The paper also reviews three approaches (i.e., video signal processor, building block and monolithic codes) for implementing video codes standards. The second half of the paper discusses various high-throughput technologies developed for programmable Video Signal Processor (VSP) LSIs. A number of VSP LSIs are introduced, including the world's first programmable VSP, developed in February 1987 and a monolithic codec ship, built in February 1993 that is sufficient in itself for the construction of a video encoder for encoding full-CIF data at 30 frames per second. Technologies for reduction of power dissipation while keeping maintaining throughput are also discussed.

Various kinds of new architectures have been proposed to enhance operating performance of the DRAM. This paper reviews these architectures including EDO, SDRAM, RDRAM, EDRAM, and CDRAM. The EDO slightly modifies the output control of the conventional DRAM architecture. Other innovative architectures try to enhance the performance by taking advantage of DRAM's internal multiple bits architecture with internal pipeline, parallel-serial conversion, or static buffers/on-chip cache. A quantitative analysis based on an assumption of wait cycles was made to compare PC system performance with some architectures. The calculation indicated the effectiveness of external or on-chip cache. Future trends cover high-speed I/O interface, unified memory architecture, and system integrated memory. The interface includes limited I/O swing such as HSTL and SSTL to realize more than 100MHz operation. Also, Ramlink and SyncLink are briefly reviewed as candidates for next generation interface. Unified memory architecture attempts to save total memory capacity by combining graphics and main memory. Advanced device technology enables system integration which combine system logic and memory. It suggests one potential direction towards system on a chip in the future.

This paper describes a new active pull-up (APU) interface for high-speed point-to-point transmission. The APU circuit is used to speed up a low-power-consumption open-drain-type interface. It pulls up the output at a fixed duration and this limiting of the pull-up duration prevents the pull-up operation from going into a counter phase at over 1-Gbps operation. Measurements of test chips fabricated with 0.25-µm bulk CMOS show. 1.7-Gbps error-free operation for the APU interface and 1.2-Gbps operation for the open-drain-type interface: The APU interface is 1.4 faster than the open-drain type. The application of a 0.25-µm SIMOX-CMOS device to the APU interface increases the bit rate 1.5 times compared with 0.25-µm bulk CMOS. Altogether the interface covers the bit rate of 2.4 Gbps, which is a layer of the communication hierarchy. The APU interface circuit can be applied to large-pin-count LSIs because of its full-CMOS single-rail structure.

Based on the test method proposed by Sub-Committee G of the International Special Committee on Radio Interference, most telephone receivers in Japan have insufficient immunity to acoustic noise caused by radio-frequency fields. This is because the modulation depth of the RF signal used is too high to accurately simulate the audio-frequency components of TV video signals. Reducing the modulation depth from 80% to 5% produces a more realistic simulation.

A directed graph G = (V,E) is called the n-rotator graph if V = {a1a2an|a1a2an is a permutation of 1,2,,n} and E = {(a1a2an,b1b2bn)| for some 2 i n, b1b2bn = a2aia1ai+1an}. We show that for any pair of distinct nodes in the n-rotator graph, we can construct n - 1 disjoint paths, each length < 2n, connecting the two nodes. We propose a nonadaptive fault-tolerant file transmission algorithm which uses these disjoint paths. Then the probabilistic analysis of its reliability is given.

The synergistic effects obtained by adopting both space diversity reception and adaptive equalization play a very important role in circuit outage reduction. This paper quantitatively analyzes these synergistic effects when dispersive and flat fading occur simultaneously. Analytical results show that the synergistic effects are of the same magnitude as the adaptive equalizer improvement factor when only dispersive fading causes outage. The synergistic effects gradually disappear when noise is the predominant cause of outage.

We present a new method for the self-tuning control (STC) of nonminimum phase continuous-time systems based on the pole-zero placement. The long division method is used to decompose a polynomial into a stable and unstable polynomials. It is also shown that the effect of unstable zeros on the magnitude of the desired output can be cancelled. Finally, the results of computer simulation are presented to illustrate the effectiveness of the proposed method.

In anonymous survey, statistical information by attributes of respondents -such as his gender, age or adress-plays an important role in the interpretation of data. However, giving away all his attributes may cause privacy problem. That is, gathering many attributes may help identifying specifically who responded to the anonymous survey. In this paper, we propose a protocol executed among several `entities in charge' in order to compute statistical information for surveys. The advantage of adopting this protocol is that it does not release extra information of attributes on calculating statistical results. We can show that this protocol is a secure computation in the sense of Micali-Rogaway if played by semi-honest entities. We furthurly give a protocol with zero-knowledge proofs to ensure that the entities are indeed semi-honest.

In the business systems design learning environment, there may be more than one solution to any given problem. For instance, the data model will be different depending on each learner's perspective. Accordingly, group learning systems are very effective in this domain. We have developed CAMELOT (Collaborative and Multimedia Environment for Learners on Teams) [18] using the Nominal Group Technique for group problem solving. In this paper, the basic framework of the collaborative learning system and the effectiveness of collaborative learning in designing the Data Model are described. By using CAMELOT, each learner learns how to analyze through case studies and how to cooperate with his or her group in problem solving. Learners come to a deeper understanding from using CAMELOT than from studying independently because they are enabled to reach better solutions through discussion, tips from other learners, and examination of one another's works.

In this paper, we give an algorithm which, given a set F of at most (n - 1) - k faulty nodes, and two sets S = {s1,..., sk} and T = {t1,..., tk}, 1 k n - 1, of nonfaulty nodes in n-dimensional star graphs Gn, finds k fault-free node disjoint paths si tji, where (j1,..., jk) is a permutation of (1,..., k), of length at most d(Gn) + 5 in O(kn) optimal time, where d(Gn) = 3(n-1)/2 is the diameter of Gn.

A novel method of multichannel surface EMG processing has been developed to compensate for the distortion in bipolar surface EMG signals due to the movement of innervation zones. The distortion of bipolar surface EMG signals was mathematically described as a filtering function. A compensating technique for such distorted bipolar surface EMG signals was developed for the brachial biceps during dynamic contractions in which the muscle length and tension change. The technique is based on multichannel surface EMG measurement, a method for estimating the movement of an innervation zone, and the inverse filtering technique. As a result, the distorted EMG signals were compensated and transformed into nearly identical waveforms, independent of the movement of the innervation zone.

The coupling response of an external transient electromagnetic field to a transmission line is considered. An experiment has been conducted to verify the line equations for a transmission line excited externally by a transient near field. The model field is generated by a monopole antenna installed in the vicinity of the transmission line and driven by a step waveform. The waveform is analyzed into discrete spectrum components using a Fourier transform. The frequency-domain field components affecting the transmission line are estimated by the moment method, and then the induced frequency-domain voltage at the terminal load is converted into a time-domain voltage using an inverse Fourier transform. Comparison between the measured and the computed values provides verification of the line equations. The coupling mechanism is discussed from the experimental results. It seems equivalently that the transmission line picks up the field, generated at the feed point and the top point of the monopole antenna, at both terminal ends.

We define the Reallocation Problem to determine whether we can move products from their current store-houses to target storehouses in a number of moves which is less than or equal to a given number. This problem is defined simply and can be applied to many practical problems. We give necessary and sufficient conditions for feasibility for Reallocation Problems under various conditions, and propose liner time algorithms, when the volume of the products is restricted to 1. Moreover, we show that the Reallocation Problem is NP-complete in the strong sense, when the volume of the products is not restricted.

This paper proposes a method to predict and control noise voltage caused by electrostatic discharge (ESD) to electronic equipment. The relationship of grounding system configurations for a typical set of equipment to ESD immunity has been derived using a mechanism of ground potential variations. The equivalent circuit representing ground elements as lumped constants enables us to predict the transient ground potential differences between PCB (Printed Circuit Board) ground planes connected via signal cables and induced noise voltage at the receiving end. The calculation shows that the contribution of ground potential differences to noise voltage is comparable to that of the electromagnetic coupling between the discharge current on the enclosure and the circuit loops. The calculation also shows some characteristic results, such as; the induced noise voltage is remarkably dependent on the unbalance in ground cable lengths and on the impedance of ground conductors connecting PCBs, especially when the equipment uses a single-point grounding system. These characteristics were confirmed by measurements of induced ground potential differences, noise voltage and immunity levels. Thus the proposed method is shown to be very effective to analyze the dependency of grounding conditions on ESD immunity and to improve ESD immunity in equipment design.

The recurrence method is useful for numerical calculation of the Bassel function Jv(x) of complex order v. The necessary total number of the recurrences in this method has been examined for the real order v, but it is known only for limited ranges of the real order v and the variable x, and it is not known for the complex order v. This letter proposes a new algorithm which increases the total number of the recurrences gradually, and which stops the calculation automatically when the approximate Bessel function with a necessary precision is obtained.

Digital halftoning is a well-known technique in image processing to convert an image having several bits for brightness levels into a binary image consisting only of black and white dots. A great number of algorithms have been presented for this problem, some of which have only been evaluated just by comparison with human eyes. In this paper we formulate the digital halftoning problem as a combinatiorial problem which allows an exact solution with graph-theoretic tools. For this, we consider a d-dimensional grid of n := Nd pixels (d 1). For each pixel, we define a so-called k-neighborhood, k {0,...N - 1}, which is the set of at most (2k + 1)d pixels that can be reached from the current pixel in a distance of k. Now, in order to solve the digital halftoning problem, we are going to minimize the sum of distances of all k-neighborhoods between the original picture and the halftoned one. We show that the problem can be solved in linear time in the one-dimensional case while it looks hopeless to have a polynomial-time algorithm in higher dimension including the usual two-dimensional case. We present an exact algorithm for the one-dimensional case which runs in O(n) time if k is regarded to be a constant. For two-dimensional case we present fast approximation techniques based on space filling curves. An experimental comparison of several implementations of approximate algorithms proves that our algorithms are of practical interest.

We propose a new algorithm for minimizing the number of vertices of an approximate curve by keeping the error within a given bound (min-# problem) with the parallel-strip error criterion. The best existing algorithm which solves this problem has O (n2 log n) time complexity. Our algorithm which uses the Cone Intersection Method does not have an improved time complexity, but does have a high efficiency. In particular, for practical data such as those which represent the boundaries or the skeletons of an object, the new algorithm can solve the min-# problem in nearly O(n2) time.

Recently, a number of concurrency control algorithms have been proposed for multidatabase system (MDBS) concurrency control methods (CCMs) and the most challenging issue of them has been a concern about how to ensure global serializability (GSR). In this paper, we examine two concurrency control algorithms of MDBS through simulation approach: optimistic ticket method (OTM) and global ticket method (GTM). In historical note, OTM is known to be the first practical solution, since this approach ensures GSR by way of automatically resolving indirect conflicts among global transactions without making any restrictions on local CCMs. However, OTM is expected to yield poor performance since it enforces all global transactions to take a local ticket which causes direct conflicts between them. In GTM, the global transaction manager in an MDBS assigns a global ticket to global transactions rather than accessing a local ticket as in OTM. Our experimental results showed that GTM outperforms OTM in cases that short timeout values are given. However, in case that the timeout value relatively becomes long, our results demonstrated that OTM outperforms GTM.

GaAs 10 Gb/s 64:1 Multiplexer/Demultiplexer chip sets have been successfully developed. The 64-bit 156 Mb/s parallel data output or input of these chip sets can be directly connected to CMOS LSIs. These chip sets consist of a 10Gb/s 4: 1 MUX IC, a 10 Gb/s 1: 4 DEMUX IC, four 2.5 Gb/s 16: 1 MUX LSIs and four 2.5 Gb/s 1: 16 DEMUX LSIs. This multi-chip construction is adopted for low power dissipation and high yield. The basic circuit employed in the 10 Gb/s4: 1 MUX/DEMUX ICs is an SCFL circuit using 0.4 µm-gate FETs with a power supply of -5.2 V, and that in 2.5 Gb/s 16: 1 MUX/DEMUX LSIs is a DCFL circuit using 0.6 µm-gate FETs with a power supply of -2.0 V. These chip sets have functions for synchronization among these ICs and to enable bit shift to make the system design easier. In the 10 Gb/s 4: 1 MUX IC, a timing adjuster is adopted. This timing adjuster can delay the timing of the most critical path by 50 ps. Even if the delay times are out of order due to fluctuations in process, temperature, power supply voltage and other factors, this timing can be revised and the 4: 1 MUX IC can operate at 10 Gb/s. Furthermore, a 48-pin quad flat package for 10 Gb/s 4: 1 MUX/DEMUX ICs has been newly developed. The measured insertion loss is 1.7 dB (at 10 GHz), and the isolation is less than -20 dB (at 10 GHz). These values are sufficient in practical usage. Measurements of these chip sets show desirable performance at the target 10 Gb/s. The power dissipations of the 64: 1 MUX/DEMUX chip sets are 10.3 W and 8.2 W, respectively. These chip sets is expected to contribute to high speed telecommunication systems.

This paper discusses the design of a small sensing device for EMI measurement which has equivalent characteristics to the absorbing clamp method, and reports the results on evaluation of the device. The device can be applied to the inspection apparatus for products such as power tools to examine conformance to EMI regulations of electromagnetic radiation spectrum. For reducing the scale of the EMI inspection apparatus, new matching circuit being replaced with the absorbing clamp method is adopted in the sensing device. Length of the sensing device is smaller than one twelfth of a wavelength of the measuring frequency in order to regard the sensing device as a concentrated constant circuit. The matching circuit is a resonant circuit which consists of a coaxial coupled transformer and a variable capacitor, and the transformer is a spiral copper tube in which a pair of AC power line wires passes. Resonant frequency of the circuit is tuned to the measuring frequency by adjusting the variable capacitor so that the circuit would terminate the power line by impedance zero. Thus interference current propagating along the power line from a product is absorbed, and observed by means of a VHF current probe which is settled in the matching circuit. A simple circuit for measurement of noise amplitude distribution (NAD) of interference current was developed as well as an equation to estimate quasi-peak value from the NAD. Result of measurement by the sensing device and proposed procedure confirmed good correlation with the standard absorbing clamp method, and deviation was within 3dB. Measurement time was reduced to 25 s per product, and the in-line EMI checker with new sensing device can be employed in a mass production line.