This paper presents a novel and successful logic synthesis method for optimizing ternary logic functions of any given number of input variables. A new optimization algorithm to synthesize and minimize an arbitrary ternary logic function of n-input variables can always lead this function to optimal or very close to optimal solution, where [n (n1)/2]1 searches are necessary to achieve the optimal solution. Therefore, the complexity number of this algorithm has been greatly reduced from O(3n) into O(n2). The advantages of this synthesis and optimization algorithm are: (1) Very easy logic synthesis method. (2) Algorithm complexity is O(n2). (3) Optimal solution can be obtained in very short time. (4) The method can solve the interconnection problems (interconnection delay) of VLSI and ULSI processors, where very fast and parallel operations can be achieved. A transformation method between operational and polynomial domains of ternary logic functions of n-input variables is also discussed. This transformation method is very effective and simple. Design of the circuits of GF(3) operators, addition and multiplication mod-3, have been proposed, where these circuits are composed of Josephson junction devices. The simulation results of these circuits and examples show the following advantages: very good performances, very low power consumption, and ultra high speed switching operation.

We modified the adaptive fuzzy classification algorithm (AFC), which allows fuzzy clusters to grow to meet the demands of a given task during training. Every fuzzy cluster is defined by a reference vector and a fuzzy cluster radius, and it is represented as a shape of hypersphere in pattern space. Any pattern class is identified by overlapping plural hyperspherical fuzzy clusters so that it is possible to approximate complex decision boundaries among pattern classes. The modified AFC was applied to recognize handwritten digits, and performances were shown compared with other neural networks.

We have studied in detail the effect of gas flow rates on the film properties of low-temperature (300) polycrystalline silicon (poly-Si) films prepared by conventional plasma enhanced chemical vapor deposition (13.56 MHz) with SiF4/SiH4/H2 gases. The effect of SiH4 flow rate on crystallization is shown to be large. A small amount of SiH4 with high SiF4 and H2 flow rates (50[H2]/[SiH4]1200, 20[SiF4]/[SiH4]150, 1[H2]/[SiF4]16) is important to form poly-Si films. The poly-Si films deposited under such optimized conditions had shown preferential 〈110〉-orientation and the crystalline fraction is estimated to be more than 80%. The deposition rates are in the range of 5-30 nm/min. The conductivity is in the range of 10-8-10-6 S/cm. Further, the electrical conduction indicates an activation type, and the activation energy is in the range of 0.5-0.6 eV.

A globally and quadratically convergent algorithm is presented for solving nonlinear resistive networks containing transistors modeled by the Gummel-Poon model or the Shichman-Hodges model. This algorithm is based on the Katzenelson algorithm that is globally convergent for a broad class of piecewise-linear resistive networks. An effective restart technique is introduced, by which the algorithm converges to the solutions of the nonlinear resistive networks quadratically. The quadratic convergence is proved and also verified by numerical examples.

This paper considers algebraic basic processes, a subset of communicating processes in CCS by Milner, and presents a synthesis algorithm to infer a process that satisfies the properties of the process, represented as fomulae in Hennessy-Milner Logic. The validity of the proposed algorithm can be stated that it synthesizes a process in the limit, which cannot be distinguished from the target one with respect to the strong equivalence.

Measuring mechanical characteristics of optical disks is significant not only for designing drives but also for assuring disk interchangeability. This paper shows that the lens-movement detection method has the greatest overall potential and thus fits to a practical system for measuring mechanical characteristics. A system based on this method was constructed by developing simple and accurate capacitive sensors that can be built into an optical head to detect lens movement. The system configuration includes a precision turntable and a high-duarability reference disk to fully extract the potential. Test results show that this measuring system has adequate measuring range, accuracy, and stability. Some applications of this system are described in this paper. They show that the system is useful for evaluating and improving optical disk mechanical characteristics.

We predict that chemical waves can propagate as a guided mode in a reaction-diffusion system that consists of two regions with different wave speeds. In comparison with electromagnetic waveguides, unique features of the guided chemical waves can be seen in their dispersion characteristics. Conditions for supporting lowest-loss guided waves are discussed.

State space explosion is a serious problem in analyzing discrete event systems that allow concurrent occurring of events. A new method is proposed for generating reduced state spaces of systems. This method is an improvement of Valmari's stubborn set method. The generated state space preserves liveness, livelocks, and terminal states of the ordinary state space. Petri nets are used as a model of systems, and a method is shown for generating a reduced state space from a given Petri net.

It is desirable to design an ATM switch that is nonblocking at the connection level by using simple connection admission control (CAC) schemes. To accomplish this goal, it is necessary to consider the relationships between CAC, cell-level quality-of-services (QOS), and the structure of multistage switches as well as switch modules. In this paper, we formulate a framework to design a multistage nonblocking ATM switch. We show that if a switch has the property of the Sufficiency of Knowledge of External Loads (SKEL), i.e., the property that its cell-level performance is robust to the distribution of incoming traffic among all inputs, then the switch is also nonblocking at the connection-level by using a simplified CAC that guarantees QOS of a connection by controlling the aggregate loads on outputs. Furthermore, we show that a Clos three-stage network using SKEL switch modules and Multipath Self-Routing (MPSR) also has the SKEL property and is a nonblocking switching network that needs CAC only at its outputs. We also demonstrate a design of multistage nonblocking ATM switches with Knockout switch modules.

A radial line slot antenna (RLSA) is a slotted waveguide planar array for the direct broadcast from satellite (DBS) subscriber antennas. A single-layered RLSA (SL-RLSA) is excited by a radially outward traveling wave. The antenna efficiency of more than 85% has already been realized. These antennas are designed on the assumption of perfectly rotationally symmetrical traveling wave excitation; the slot design is based upon the analysis of a slot pair on the rectangular waveguide model with periodic boundary walls. However, the slots perturb the inner field and the actual antenna operation is not perfectly symmetrical. This causes the efficiency reduction especially for very small size antenna. This paper presents a fundamental analysis of the inner field of the radial waveguide. It is impossible to analyze all the slot pairs in the aperture as it is and only the slots in the inner few turns are considered since these provide dominant perturbation. The calculated results are verified by the experiments and reasonable agreement is demonstrated. Some design policies are suggested for enhancing the rotational symmetry.

This paper describes a preconstrained compaction method and its application to the direct design-rule conversion of CMOS layouts. This approach can convert already designed physical patterns into compacted layouts that satisfy user-specified design rules. Furthermore, preconstrained compaction can eliminate unnecessarily extended diffusion areas and polysilicon wires which tend to be created with conventional longest path based compactions. Preconstrained compaction can be constructed by combining a longest path algorithm with forward and backward slack processes and a preconstraint generation process. This contrasts with previously proposed approaches based on longest path algorithms followed by iterative improvement processes, which include applications of linear programming. The layout styles in those approaches are usually limited to a model where fixed-shaped rectilinear blocks are moved so as to minimize the total length of rectilinear interconnections among the blocks. However, preconstrained compaction can be applied to reshaping polygonal patterns such as diffusion and channel areas. Thus, this compaction method makes it possible to reuse CMOS leaf and macro cell layouts even if design rules change. The proposed preconstrained compaction approach has been applied to direct design-rule conversion from 0.8-µm to 0.5-µm rules of CMOS layouts containing from several to 10,195 transistors. Experimental results demonstrate that a 10.6% reduction in diffusion areas can be achieved without unnecessary extensions of polysilicon wires with a 39% increase in processing times compared with conventional approaches.

Given a sorted set S of n points in the plane, the prefix convex hulls problem of S is to compute the convex hull for every prefix set of S. We present a parallel algorithm for this problem. Our algorithm runs in O(logn) time using n/logn processors in the CREW PRAM computational model. The algorithm is shown to be time and cost optimal. One of the techniques we adopt to achieve these optimal bounds is the use of a new parallel data structure Array-Tree.

Creating a bandwidth abundant B-ISDN requires the further development of path technologies. Optical path cross-connect nodes (OXCs) will be required that offer very high levels of expandability. The present limited traffic demands must be efficiently supported while permitting easy step-wise expansion in capacity. This paper proposes two OXC architectures that offer high modularity with regard to incoming/outgoing links or the number of multiplexed wavelengths in each link. This paper briefly reviews, for optical path realization, the wavelength path (WP) and the virtual wavelength path (VWP) techniques. The proposed OXC architectures provide flexibility and minimum investment to encourage introduction but support incremental network growth and investment to match traffic demand. The architectures make it easy to upgrade a WP network to a VWP network, simply by replacing some optical components. It is also shown that the proposed OXC architectures ensure effective optical signal detection after a long-haul optical fiber transmission because they minimizes signal power losses within the OXC. Therefore, the proposed OXC architecture can be applied to global area networks. The proposed OXC architectures will play a key role in realizing the optical path infrastructure for the future bandwidth abundant B-ISDN.

The methodology for latchup-free design in bipolar and PMOS merged gates, so-called BiPMOS gates, is considered. Although BiPMOS gates can provide higher switching characteristics than conventional, individually drawn, BiCMOS gates even when the supply voltage is reduced, the general methodology to prevent latchup has been lacking. This paper presents an approximate, but sufficiently correct, mathematical technique to solve the Laplace equation, which gives the distribution of latchup trigger current for the given BiPMOS drawings. It is shown that the resistances of the collector plug and the spreading resistance under the base-collector junction greatly influence latchup, and that the well-emitter overlapping space becomes a problem in the case of a single collector. The distribution of latchup triggering current for the double-emitter double collector NPN transistor indicates the optimum position of the source diffusion area.

This paper presents a support method for specifying communication systems. Generally, a set of requirements for a target system is partial and ambiguous to construct the whole system, namely it lacks certain necessary descriptions for the target system. To attack this problem, our method enables a designer to obtain such necessary descriptions from specifications stored in a knowledge base, namely by reusing specifications, and helps the designer to specify the target system completely. In our support method, we adopt labelled transition systems (LTSs) which are state transition graphs and are shared as a common notion by most FDTs. Therefore, our method is the common approach to FDTs. We propose a new idea about similarity berween LTSs, and propose an algorithm to suggest similar LTSs to the designer.

We have systematically studied the characteristics of Si doping in GaAs grown on (311)A GaAs substrates by molecular beam epitaxy. The growth temperature dependence of Si doping has been investigated. It is found that the conduction-type sharply changes from p-type to n-type with decreasing growth temperature at a critical temperature of 430-480. The highest hole density obtained for uniformly doped layers was 1.51020 cm-3, while for δ-doped layers the sheet hole density as high as 2.61013 cm-2 was achieved. This is the highest hole density ever reported for δ-doped GaAs.

This paper presents an approach for assembly plan generation from an assembly illustration. Previously, we have already proposed an approach for the assembly plan related information acquisition from an assembly illustration, in which auxiliary lines were taken as clues. However, some ambiguity remains in dynamic information such as assembly operations and their execution order. We have verified through experiments that the ambiguity could be made clear by referring to the feedback information from the completed assemblage after the assembly operations shown in the current illustration. But in fact, in an assembly illustration there are not only the figures of mechanical parts and the auxiliary lines for visualizing their assembly relations, but explanatory words and explanatory lines as well. Explanatory words can basically be classified into two categories: instructions on assembly operations and mechanical part names. The former explicitly describes dynamic information such as the details of assembly operations. The latter also implies dynamic information such as the function of a mechanical part. Explanatory lines are usually drawn for making clear the explanatory relations. Naturally we consider that to integrate the information from explanatory words with that already obtained through the extraction of auxiliary lines will probably enable us to generate an unambiguous assembly plan from the currently observing illustration.

Exact analytical solutions for the steady-state transmission and reflection characteristics of a nonlinear Fabry-Perot resonator applicable to bistable optical devices are derived. The resonator consists of a Kerr-like nonlinear film sandwiched by reflection mirrors made of a quarter-wave dielectric stack. An equivalent mirrorless model has been introduced to facilitate the analysis. For both positive and negative nonlinear coefficients, the rigorous solutions have been simply expressed in terms of Jacobian elliptic functions.

A rigorous radar cross section (RCS) analysis of a two-dimensional parallel-plate waveguide cavity with three-layer material loading is carried out for the E- and H-polarized planc wave incidence using the Wiener-Hopf technique. Introducing the Fourier transform for the scattered field and applying boundary conditions in the transform domain, the problem is formulated in terms of the simultaneous Wiener-Hopf equations satisfied by the unknown spectral functions. The Wiener-Hopf equations are solved via the factorization and decomposition procedure together with rigorous asymptotics, leading to the efficient approximate solution. The scattered field in the real space is evaluated by taking the inverse Fourier transform and applying the saddle point method. Representative numerical examples on the RCS are given for various physical parameters. It is shown that the three-layer lossy material loading inside the cavity results in significant RCS reduction over broad frequency range.

In this paper we estimate the number of permutations realizable in fault-tolerant multistage interconnection networks designed to tolerate faults on any switching element. The Parallel Omega network and the INDRA network are representative types of fault-tolerate multistage interconnection networks designed to tolerate a single fault. In order to evaluate the enhancement in the function of network by preparing the hardware redundancy for fault-tolerance, we estimate the number of permutations realizable in fault-tolerant networks. This result enables us to set up a standard to evaluate the hardware redundancy required to tolerate multifaults from the viewpoint of the enhancement of network function. This paper concludes that in the case where the number of inputs is up to 32 the increase ratio of the number of realizable permutations is no more than 1/0.73 even if the tolerance to multifaults is prepared instead of the tolerance to a single fault.